98 lines
2.9 KiB
Diff
98 lines
2.9 KiB
Diff
From 95713978b0a2929b72933235bb07c0a793e71afa Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
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Date: Fri, 2 May 2014 17:57:16 +0200
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Subject: [PATCH 2/2] clk: sunxi: Implement MMC phase control
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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HdG: add header exporting clk_sunxi_mmc_phase_control
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Signed-off-by: Emilio López <emilio@elopez.com.ar>
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Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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Signed-off-by: Mike Turquette <mturquette@linaro.org>
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---
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drivers/clk/sunxi/clk-sunxi.c | 36 ++++++++++++++++++++++++++++++++++++
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include/linux/clk/sunxi.h | 22 ++++++++++++++++++++++
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2 files changed, 58 insertions(+)
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create mode 100644 include/linux/clk/sunxi.h
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diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
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index bd7dc73..59f9040 100644
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--- a/drivers/clk/sunxi/clk-sunxi.c
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+++ b/drivers/clk/sunxi/clk-sunxi.c
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@@ -507,6 +507,42 @@ CLK_OF_DECLARE(sun7i_a20_gmac, "allwinner,sun7i-a20-gmac-clk",
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/**
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+ * clk_sunxi_mmc_phase_control() - configures MMC clock phase control
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+ */
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+
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+void clk_sunxi_mmc_phase_control(struct clk_hw *hw, u8 sample, u8 output)
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+{
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+ #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
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+ #define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw)
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+
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+ struct clk_composite *composite = to_clk_composite(hw);
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+ struct clk_hw *rate_hw = composite->rate_hw;
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+ struct clk_factors *factors = to_clk_factors(rate_hw);
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+ unsigned long flags = 0;
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+ u32 reg;
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+
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+ if (factors->lock)
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+ spin_lock_irqsave(factors->lock, flags);
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+
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+ reg = readl(factors->reg);
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+
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+ /* set sample clock phase control */
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+ reg &= ~(0x7 << 20);
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+ reg |= ((sample & 0x7) << 20);
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+
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+ /* set output clock phase control */
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+ reg &= ~(0x7 << 8);
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+ reg |= ((output & 0x7) << 8);
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+
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+ writel(reg, factors->reg);
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+
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+ if (factors->lock)
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+ spin_unlock_irqrestore(factors->lock, flags);
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+}
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+EXPORT_SYMBOL(clk_sunxi_mmc_phase_control);
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+
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+
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+/**
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* sunxi_factors_clk_setup() - Setup function for factor clocks
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*/
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diff --git a/include/linux/clk/sunxi.h b/include/linux/clk/sunxi.h
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new file mode 100644
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index 0000000..1ef5c89
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--- /dev/null
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+++ b/include/linux/clk/sunxi.h
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@@ -0,0 +1,22 @@
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+/*
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+ * Copyright 2013 - Hans de Goede <hdegoede@redhat.com>
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; either version 2 of the License, or
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+ * (at your option) any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ */
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+
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+#ifndef __LINUX_CLK_SUNXI_H_
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+#define __LINUX_CLK_SUNXI_H_
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+
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+#include <linux/clk.h>
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+
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+void clk_sunxi_mmc_phase_control(struct clk_hw *hw, u8 sample, u8 output);
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+
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+#endif
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--
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1.9.0
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