38 lines
2.0 KiB
Diff
38 lines
2.0 KiB
Diff
From: Ben Hutchings <ben@decadent.org.uk>
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Date: Thu, 08 Aug 2019 02:40:23 +0100
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Subject: x86/cpufeatures: Move swapgs feature bits to existing scattered words
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Forwarded: not-needed
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Renumbering CPU feature bits is a kABI change (even if genksyms
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doesn't notice it). Move the new feature bits for the mitigations to
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spare bits in the existing "scattered" feature words.
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---
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--- a/arch/x86/include/asm/cpufeatures.h
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+++ b/arch/x86/include/asm/cpufeatures.h
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@@ -108,6 +108,7 @@
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#define X86_FEATURE_EXTD_APICID ( 3*32+26) /* Extended APICID (8 bits) */
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#define X86_FEATURE_AMD_DCM ( 3*32+27) /* AMD multi-node processor */
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#define X86_FEATURE_APERFMPERF ( 3*32+28) /* P-State hardware coordination feedback capability (APERF/MPERF MSRs) */
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+#define X86_FEATURE_FENCE_SWAPGS_USER ( 3*32+29) /* "" LFENCE in user entry SWAPGS path */
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#define X86_FEATURE_NONSTOP_TSC_S3 ( 3*32+30) /* TSC doesn't stop in S3 state */
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#define X86_FEATURE_TSC_KNOWN_FREQ ( 3*32+31) /* TSC has known frequency */
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@@ -221,6 +222,7 @@
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#define X86_FEATURE_ZEN ( 7*32+28) /* "" CPU is AMD family 0x17 (Zen) */
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#define X86_FEATURE_L1TF_PTEINV ( 7*32+29) /* "" L1TF workaround PTE inversion */
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#define X86_FEATURE_IBRS_ENHANCED ( 7*32+30) /* Enhanced IBRS */
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+#define X86_FEATURE_FENCE_SWAPGS_KERNEL ( 7*32+31) /* "" LFENCE in kernel entry SWAPGS path */
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/* Virtualization flags: Linux defined, word 8 */
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#define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */
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@@ -279,8 +281,6 @@
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#define X86_FEATURE_CQM_OCCUP_LLC (11*32+ 1) /* LLC occupancy monitoring */
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#define X86_FEATURE_CQM_MBM_TOTAL (11*32+ 2) /* LLC Total MBM monitoring */
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#define X86_FEATURE_CQM_MBM_LOCAL (11*32+ 3) /* LLC Local MBM monitoring */
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-#define X86_FEATURE_FENCE_SWAPGS_USER (11*32+ 4) /* "" LFENCE in user entry SWAPGS path */
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-#define X86_FEATURE_FENCE_SWAPGS_KERNEL (11*32+ 5) /* "" LFENCE in kernel entry SWAPGS path */
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/* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
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#define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */
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