125 lines
3.8 KiB
Diff
125 lines
3.8 KiB
Diff
From: Nicolas Pitre <nico@cam.org>
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The implementation for memory copy functions on ARM had a (disabled)
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provision for aligning the source pointer before loading registers with
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data. Turns out that aligning the _destination_ pointer is much more
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useful, as the read side is already sufficiently helped with the use of
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preload.
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So this changes the definition of the CALGN() macro to target the
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destination pointer instead, and turns it on for Feroceon processors
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where the gain is very notable.
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Signed-off-by: Nicolas Pitre <nico@marvell.com>
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---
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arch/arm/lib/copy_template.S | 12 ++----------
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arch/arm/lib/memmove.S | 12 ++----------
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include/asm-arm/assembler.h | 15 +++++++++++++++
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3 files changed, 19 insertions(+), 20 deletions(-)
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Index: linux-2.6.26-rc5/arch/arm/lib/copy_template.S
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===================================================================
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--- linux-2.6.26-rc5.orig/arch/arm/lib/copy_template.S
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+++ linux-2.6.26-rc5/arch/arm/lib/copy_template.S
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@@ -13,14 +13,6 @@
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*/
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/*
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- * This can be used to enable code to cacheline align the source pointer.
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- * Experiments on tested architectures (StrongARM and XScale) didn't show
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- * this a worthwhile thing to do. That might be different in the future.
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- */
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-//#define CALGN(code...) code
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-#define CALGN(code...)
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-
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-/*
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* Theory of operation
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* -------------------
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*
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@@ -82,7 +74,7 @@
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stmfd sp!, {r5 - r8}
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blt 5f
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- CALGN( ands ip, r1, #31 )
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+ CALGN( ands ip, r0, #31 )
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CALGN( rsb r3, ip, #32 )
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CALGN( sbcnes r4, r3, r2 ) @ C is always set here
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CALGN( bcs 2f )
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@@ -168,7 +160,7 @@
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subs r2, r2, #28
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blt 14f
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- CALGN( ands ip, r1, #31 )
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+ CALGN( ands ip, r0, #31 )
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CALGN( rsb ip, ip, #32 )
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CALGN( sbcnes r4, ip, r2 ) @ C is always set here
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CALGN( subcc r2, r2, ip )
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Index: linux-2.6.26-rc5/arch/arm/lib/memmove.S
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===================================================================
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--- linux-2.6.26-rc5.orig/arch/arm/lib/memmove.S
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+++ linux-2.6.26-rc5/arch/arm/lib/memmove.S
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@@ -13,14 +13,6 @@
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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-/*
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- * This can be used to enable code to cacheline align the source pointer.
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- * Experiments on tested architectures (StrongARM and XScale) didn't show
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- * this a worthwhile thing to do. That might be different in the future.
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- */
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-//#define CALGN(code...) code
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-#define CALGN(code...)
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-
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.text
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/*
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@@ -55,7 +47,7 @@ ENTRY(memmove)
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stmfd sp!, {r5 - r8}
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blt 5f
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- CALGN( ands ip, r1, #31 )
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+ CALGN( ands ip, r0, #31 )
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CALGN( sbcnes r4, ip, r2 ) @ C is always set here
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CALGN( bcs 2f )
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CALGN( adr r4, 6f )
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@@ -139,7 +131,7 @@ ENTRY(memmove)
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subs r2, r2, #28
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blt 14f
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- CALGN( ands ip, r1, #31 )
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+ CALGN( ands ip, r0, #31 )
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CALGN( sbcnes r4, ip, r2 ) @ C is always set here
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CALGN( subcc r2, r2, ip )
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CALGN( bcc 15f )
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Index: linux-2.6.26-rc5/include/asm-arm/assembler.h
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===================================================================
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--- linux-2.6.26-rc5.orig/include/asm-arm/assembler.h
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+++ linux-2.6.26-rc5/include/asm-arm/assembler.h
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@@ -56,6 +56,21 @@
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#endif
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/*
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+ * This can be used to enable code to cacheline align the destination
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+ * pointer when bulk writing to memory. Experiments on StrongARM and
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+ * XScale didn't show this a worthwhile thing to do when the cache is not
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+ * set to write-allocate (this would need further testing on XScale when WA
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+ * is used).
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+ *
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+ * On Feroceon there is much to gain however, regardless of cache mode.
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+ */
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+#ifdef CONFIG_CPU_FEROCEON
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+#define CALGN(code...) code
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+#else
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+#define CALGN(code...)
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+#endif
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+
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+/*
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* Enable and disable interrupts
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*/
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#if __LINUX_ARM_ARCH__ >= 6
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