663 lines
20 KiB
Diff
663 lines
20 KiB
Diff
From 226068a83722c5cf3da300cce9bab7201088a061 Mon Sep 17 00:00:00 2001
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From: Iyappan Subramanian <isubramanian@apm.com>
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Date: Thu, 9 Oct 2014 18:32:06 -0700
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Subject: [PATCH 02/11] drivers: net: xgene: Add 10GbE support
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Origin: https://git.kernel.org/linus/0148d38d36b76b190ddddff68f02d2617ada3bcb
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- Added 10GbE support
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- Removed unused macros/variables
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- Moved mac_init call to the end of hardware init
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Signed-off-by: Iyappan Subramanian <isubramanian@apm.com>
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Signed-off-by: Keyur Chudgar <kchudgar@apm.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/ethernet/apm/xgene/Makefile | 3 +-
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drivers/net/ethernet/apm/xgene/xgene_enet_hw.h | 14 +-
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drivers/net/ethernet/apm/xgene/xgene_enet_main.c | 58 ++--
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drivers/net/ethernet/apm/xgene/xgene_enet_main.h | 5 +-
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drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.c | 331 ++++++++++++++++++++++
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drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.h | 57 ++++
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6 files changed, 438 insertions(+), 30 deletions(-)
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create mode 100644 drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.c
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create mode 100644 drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.h
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diff --git a/drivers/net/ethernet/apm/xgene/Makefile b/drivers/net/ethernet/apm/xgene/Makefile
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index c643e8a..589b352 100644
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--- a/drivers/net/ethernet/apm/xgene/Makefile
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+++ b/drivers/net/ethernet/apm/xgene/Makefile
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@@ -2,5 +2,6 @@
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# Makefile for APM X-Gene Ethernet Driver.
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#
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-xgene-enet-objs := xgene_enet_hw.o xgene_enet_main.o xgene_enet_ethtool.o
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+xgene-enet-objs := xgene_enet_hw.o xgene_enet_xgmac.o \
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+ xgene_enet_main.o xgene_enet_ethtool.o
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obj-$(CONFIG_NET_XGENE) += xgene-enet.o
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diff --git a/drivers/net/ethernet/apm/xgene/xgene_enet_hw.h b/drivers/net/ethernet/apm/xgene/xgene_enet_hw.h
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index 084ac68..15ec426 100644
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--- a/drivers/net/ethernet/apm/xgene/xgene_enet_hw.h
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+++ b/drivers/net/ethernet/apm/xgene/xgene_enet_hw.h
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@@ -42,6 +42,11 @@ static inline u32 xgene_get_bits(u32 val, u32 start, u32 end)
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return (val & GENMASK(end, start)) >> start;
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}
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+enum xgene_enet_rm {
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+ RM0,
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+ RM3 = 3
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+};
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+
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#define CSR_RING_ID 0x0008
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#define OVERWRITE BIT(31)
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#define IS_BUFFER_POOL BIT(20)
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@@ -52,7 +57,6 @@ static inline u32 xgene_get_bits(u32 val, u32 start, u32 end)
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#define CSR_RING_WR_BASE 0x0070
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#define NUM_RING_CONFIG 5
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#define BUFPOOL_MODE 3
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-#define RM3 3
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#define INC_DEC_CMD_ADDR 0x002c
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#define UDP_HDR_SIZE 2
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#define BUF_LEN_CODE_2K 0x5000
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@@ -94,11 +98,9 @@ static inline u32 xgene_get_bits(u32 val, u32 start, u32 end)
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#define BLOCK_ETH_CSR_OFFSET 0x2000
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#define BLOCK_ETH_RING_IF_OFFSET 0x9000
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-#define BLOCK_ETH_CLKRST_CSR_OFFSET 0xC000
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#define BLOCK_ETH_DIAG_CSR_OFFSET 0xD000
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#define BLOCK_ETH_MAC_OFFSET 0x0000
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-#define BLOCK_ETH_STATS_OFFSET 0x0014
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#define BLOCK_ETH_MAC_CSR_OFFSET 0x2800
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#define MAC_ADDR_REG_OFFSET 0x00
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@@ -107,12 +109,6 @@ static inline u32 xgene_get_bits(u32 val, u32 start, u32 end)
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#define MAC_READ_REG_OFFSET 0x0c
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#define MAC_COMMAND_DONE_REG_OFFSET 0x10
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-#define STAT_ADDR_REG_OFFSET 0x00
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-#define STAT_COMMAND_REG_OFFSET 0x04
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-#define STAT_WRITE_REG_OFFSET 0x08
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-#define STAT_READ_REG_OFFSET 0x0c
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-#define STAT_COMMAND_DONE_REG_OFFSET 0x10
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-
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#define MII_MGMT_CONFIG_ADDR 0x20
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#define MII_MGMT_COMMAND_ADDR 0x24
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#define MII_MGMT_ADDRESS_ADDR 0x28
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diff --git a/drivers/net/ethernet/apm/xgene/xgene_enet_main.c b/drivers/net/ethernet/apm/xgene/xgene_enet_main.c
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index c432644..9b85239 100644
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--- a/drivers/net/ethernet/apm/xgene/xgene_enet_main.c
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+++ b/drivers/net/ethernet/apm/xgene/xgene_enet_main.c
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@@ -21,6 +21,7 @@
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#include "xgene_enet_main.h"
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#include "xgene_enet_hw.h"
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+#include "xgene_enet_xgmac.h"
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static void xgene_enet_init_bufpool(struct xgene_enet_desc_ring *buf_pool)
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{
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@@ -390,7 +391,7 @@ static int xgene_enet_process_ring(struct xgene_enet_desc_ring *ring,
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}
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}
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- return budget;
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+ return count;
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}
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static int xgene_enet_napi(struct napi_struct *napi, const int budget)
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@@ -456,8 +457,10 @@ static int xgene_enet_open(struct net_device *ndev)
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return ret;
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napi_enable(&pdata->rx_ring->napi);
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- if (pdata->phy_dev)
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+ if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII)
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phy_start(pdata->phy_dev);
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+ else
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+ schedule_delayed_work(&pdata->link_work, PHY_POLL_LINK_OFF);
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netif_start_queue(ndev);
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@@ -471,8 +474,10 @@ static int xgene_enet_close(struct net_device *ndev)
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netif_stop_queue(ndev);
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- if (pdata->phy_dev)
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+ if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII)
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phy_stop(pdata->phy_dev);
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+ else
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+ cancel_delayed_work_sync(&pdata->link_work);
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napi_disable(&pdata->rx_ring->napi);
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xgene_enet_free_irq(ndev);
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@@ -615,7 +620,6 @@ static struct xgene_enet_desc_ring *xgene_enet_create_desc_ring(
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ring->cmd_base = pdata->ring_cmd_addr + (ring->num << 6);
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ring->cmd = ring->cmd_base + INC_DEC_CMD_ADDR;
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- pdata->rm = RM3;
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ring = xgene_enet_setup_ring(ring);
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netdev_dbg(ndev, "ring info: num=%d size=%d id=%d slots=%d\n",
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ring->num, ring->size, ring->id, ring->slots);
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@@ -805,8 +809,13 @@ static int xgene_enet_get_resources(struct xgene_enet_pdata *pdata)
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pdata->phy_mode = of_get_phy_mode(pdev->dev.of_node);
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if (pdata->phy_mode < 0) {
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- dev_err(dev, "Incorrect phy-connection-type in DTS\n");
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- return -EINVAL;
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+ dev_err(dev, "Unable to get phy-connection-type\n");
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+ return pdata->phy_mode;
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+ }
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+ if (pdata->phy_mode != PHY_INTERFACE_MODE_RGMII &&
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+ pdata->phy_mode != PHY_INTERFACE_MODE_XGMII) {
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+ dev_err(dev, "Incorrect phy-connection-type specified\n");
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+ return -ENODEV;
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}
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pdata->clk = devm_clk_get(&pdev->dev, NULL);
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@@ -821,12 +830,18 @@ static int xgene_enet_get_resources(struct xgene_enet_pdata *pdata)
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pdata->eth_csr_addr = base_addr + BLOCK_ETH_CSR_OFFSET;
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pdata->eth_ring_if_addr = base_addr + BLOCK_ETH_RING_IF_OFFSET;
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pdata->eth_diag_csr_addr = base_addr + BLOCK_ETH_DIAG_CSR_OFFSET;
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- pdata->mcx_mac_addr = base_addr + BLOCK_ETH_MAC_OFFSET;
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- pdata->mcx_stats_addr = base_addr + BLOCK_ETH_STATS_OFFSET;
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- pdata->mcx_mac_csr_addr = base_addr + BLOCK_ETH_MAC_CSR_OFFSET;
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+ if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII) {
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+ pdata->mcx_mac_addr = base_addr + BLOCK_ETH_MAC_OFFSET;
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+ pdata->mcx_mac_csr_addr = base_addr + BLOCK_ETH_MAC_CSR_OFFSET;
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+ pdata->rm = RM3;
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+ } else {
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+ pdata->mcx_mac_addr = base_addr + BLOCK_AXG_MAC_OFFSET;
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+ pdata->mcx_mac_csr_addr = base_addr + BLOCK_AXG_MAC_CSR_OFFSET;
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+ pdata->rm = RM0;
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+ }
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pdata->rx_buff_cnt = NUM_PKT_BUF;
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- return ret;
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+ return 0;
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}
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static int xgene_enet_init_hw(struct xgene_enet_pdata *pdata)
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@@ -836,8 +851,7 @@ static int xgene_enet_init_hw(struct xgene_enet_pdata *pdata)
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u16 dst_ring_num;
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int ret;
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- pdata->mac_ops->tx_disable(pdata);
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- pdata->mac_ops->rx_disable(pdata);
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+ pdata->port_ops->reset(pdata);
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ret = xgene_enet_create_desc_rings(ndev);
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if (ret) {
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@@ -856,14 +870,23 @@ static int xgene_enet_init_hw(struct xgene_enet_pdata *pdata)
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dst_ring_num = xgene_enet_dst_ring_num(pdata->rx_ring);
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pdata->port_ops->cle_bypass(pdata, dst_ring_num, buf_pool->id);
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+ pdata->mac_ops->init(pdata);
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return ret;
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}
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static void xgene_enet_setup_ops(struct xgene_enet_pdata *pdata)
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{
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- pdata->mac_ops = &xgene_gmac_ops;
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- pdata->port_ops = &xgene_gport_ops;
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+ switch (pdata->phy_mode) {
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+ case PHY_INTERFACE_MODE_RGMII:
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+ pdata->mac_ops = &xgene_gmac_ops;
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+ pdata->port_ops = &xgene_gport_ops;
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+ break;
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+ default:
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+ pdata->mac_ops = &xgene_xgmac_ops;
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+ pdata->port_ops = &xgene_xgport_ops;
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+ break;
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+ }
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}
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static int xgene_enet_probe(struct platform_device *pdev)
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@@ -895,8 +918,6 @@ static int xgene_enet_probe(struct platform_device *pdev)
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goto err;
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xgene_enet_setup_ops(pdata);
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- pdata->port_ops->reset(pdata);
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- pdata->mac_ops->init(pdata);
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ret = register_netdev(ndev);
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if (ret) {
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@@ -916,7 +937,10 @@ static int xgene_enet_probe(struct platform_device *pdev)
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napi = &pdata->rx_ring->napi;
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netif_napi_add(ndev, napi, xgene_enet_napi, NAPI_POLL_WEIGHT);
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- ret = xgene_enet_mdio_config(pdata);
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+ if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII)
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+ ret = xgene_enet_mdio_config(pdata);
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+ else
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+ INIT_DELAYED_WORK(&pdata->link_work, xgene_enet_link_state);
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return ret;
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err:
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diff --git a/drivers/net/ethernet/apm/xgene/xgene_enet_main.h b/drivers/net/ethernet/apm/xgene/xgene_enet_main.h
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index ac180f9..86cf68b 100644
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--- a/drivers/net/ethernet/apm/xgene/xgene_enet_main.h
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+++ b/drivers/net/ethernet/apm/xgene/xgene_enet_main.h
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@@ -105,18 +105,17 @@ struct xgene_enet_pdata {
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void __iomem *eth_ring_if_addr;
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void __iomem *eth_diag_csr_addr;
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void __iomem *mcx_mac_addr;
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- void __iomem *mcx_stats_addr;
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void __iomem *mcx_mac_csr_addr;
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void __iomem *base_addr;
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void __iomem *ring_csr_addr;
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void __iomem *ring_cmd_addr;
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u32 phy_addr;
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int phy_mode;
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- u32 speed;
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- u16 rm;
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+ enum xgene_enet_rm rm;
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struct rtnl_link_stats64 stats;
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struct xgene_mac_ops *mac_ops;
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struct xgene_port_ops *port_ops;
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+ struct delayed_work link_work;
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};
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/* Set the specified value into a bit-field defined by its starting position
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diff --git a/drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.c b/drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.c
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new file mode 100644
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index 0000000..cd64b9f
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--- /dev/null
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+++ b/drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.c
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@@ -0,0 +1,331 @@
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+/* Applied Micro X-Gene SoC Ethernet Driver
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+ *
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+ * Copyright (c) 2014, Applied Micro Circuits Corporation
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+ * Authors: Iyappan Subramanian <isubramanian@apm.com>
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+ * Keyur Chudgar <kchudgar@apm.com>
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License as published by the
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+ * Free Software Foundation; either version 2 of the License, or (at your
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+ * option) any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
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+ */
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+
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+#include "xgene_enet_main.h"
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+#include "xgene_enet_hw.h"
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+#include "xgene_enet_xgmac.h"
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+
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+static void xgene_enet_wr_csr(struct xgene_enet_pdata *pdata,
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+ u32 offset, u32 val)
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+{
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+ void __iomem *addr = pdata->eth_csr_addr + offset;
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+
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+ iowrite32(val, addr);
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+}
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+
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+static void xgene_enet_wr_ring_if(struct xgene_enet_pdata *pdata,
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+ u32 offset, u32 val)
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+{
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+ void __iomem *addr = pdata->eth_ring_if_addr + offset;
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+
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+ iowrite32(val, addr);
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+}
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+
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+static void xgene_enet_wr_diag_csr(struct xgene_enet_pdata *pdata,
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+ u32 offset, u32 val)
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+{
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+ void __iomem *addr = pdata->eth_diag_csr_addr + offset;
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+
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+ iowrite32(val, addr);
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+}
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+
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+static bool xgene_enet_wr_indirect(void __iomem *addr, void __iomem *wr,
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+ void __iomem *cmd, void __iomem *cmd_done,
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+ u32 wr_addr, u32 wr_data)
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+{
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+ u32 done;
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+ u8 wait = 10;
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+
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+ iowrite32(wr_addr, addr);
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+ iowrite32(wr_data, wr);
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+ iowrite32(XGENE_ENET_WR_CMD, cmd);
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+
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+ /* wait for write command to complete */
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+ while (!(done = ioread32(cmd_done)) && wait--)
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+ udelay(1);
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+
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+ if (!done)
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+ return false;
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+
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+ iowrite32(0, cmd);
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+
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+ return true;
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+}
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+
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+static void xgene_enet_wr_mac(struct xgene_enet_pdata *pdata,
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+ u32 wr_addr, u32 wr_data)
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+{
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+ void __iomem *addr, *wr, *cmd, *cmd_done;
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+
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+ addr = pdata->mcx_mac_addr + MAC_ADDR_REG_OFFSET;
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+ wr = pdata->mcx_mac_addr + MAC_WRITE_REG_OFFSET;
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+ cmd = pdata->mcx_mac_addr + MAC_COMMAND_REG_OFFSET;
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+ cmd_done = pdata->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET;
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+
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+ if (!xgene_enet_wr_indirect(addr, wr, cmd, cmd_done, wr_addr, wr_data))
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+ netdev_err(pdata->ndev, "MCX mac write failed, addr: %04x\n",
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+ wr_addr);
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+}
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+
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+static void xgene_enet_rd_csr(struct xgene_enet_pdata *pdata,
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+ u32 offset, u32 *val)
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+{
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+ void __iomem *addr = pdata->eth_csr_addr + offset;
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+
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+ *val = ioread32(addr);
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+}
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+
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+static void xgene_enet_rd_diag_csr(struct xgene_enet_pdata *pdata,
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+ u32 offset, u32 *val)
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+{
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+ void __iomem *addr = pdata->eth_diag_csr_addr + offset;
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+
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+ *val = ioread32(addr);
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+}
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+
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+static bool xgene_enet_rd_indirect(void __iomem *addr, void __iomem *rd,
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+ void __iomem *cmd, void __iomem *cmd_done,
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+ u32 rd_addr, u32 *rd_data)
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+{
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+ u32 done;
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+ u8 wait = 10;
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+
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+ iowrite32(rd_addr, addr);
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+ iowrite32(XGENE_ENET_RD_CMD, cmd);
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+
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+ /* wait for read command to complete */
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+ while (!(done = ioread32(cmd_done)) && wait--)
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+ udelay(1);
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+
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+ if (!done)
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+ return false;
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+
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+ *rd_data = ioread32(rd);
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+ iowrite32(0, cmd);
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+
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+ return true;
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+}
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+
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+static void xgene_enet_rd_mac(struct xgene_enet_pdata *pdata,
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+ u32 rd_addr, u32 *rd_data)
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+{
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+ void __iomem *addr, *rd, *cmd, *cmd_done;
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+
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+ addr = pdata->mcx_mac_addr + MAC_ADDR_REG_OFFSET;
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+ rd = pdata->mcx_mac_addr + MAC_READ_REG_OFFSET;
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+ cmd = pdata->mcx_mac_addr + MAC_COMMAND_REG_OFFSET;
|
|
+ cmd_done = pdata->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET;
|
|
+
|
|
+ if (!xgene_enet_rd_indirect(addr, rd, cmd, cmd_done, rd_addr, rd_data))
|
|
+ netdev_err(pdata->ndev, "MCX mac read failed, addr: %04x\n",
|
|
+ rd_addr);
|
|
+}
|
|
+
|
|
+static int xgene_enet_ecc_init(struct xgene_enet_pdata *pdata)
|
|
+{
|
|
+ struct net_device *ndev = pdata->ndev;
|
|
+ u32 data;
|
|
+ u8 wait = 10;
|
|
+
|
|
+ xgene_enet_wr_diag_csr(pdata, ENET_CFG_MEM_RAM_SHUTDOWN_ADDR, 0x0);
|
|
+ do {
|
|
+ usleep_range(100, 110);
|
|
+ xgene_enet_rd_diag_csr(pdata, ENET_BLOCK_MEM_RDY_ADDR, &data);
|
|
+ } while ((data != 0xffffffff) && wait--);
|
|
+
|
|
+ if (data != 0xffffffff) {
|
|
+ netdev_err(ndev, "Failed to release memory from shutdown\n");
|
|
+ return -ENODEV;
|
|
+ }
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static void xgene_enet_config_ring_if_assoc(struct xgene_enet_pdata *pdata)
|
|
+{
|
|
+ xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIWQASSOC_ADDR, 0);
|
|
+ xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIFPQASSOC_ADDR, 0);
|
|
+ xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIQMLITEWQASSOC_ADDR, 0);
|
|
+ xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIQMLITEFPQASSOC_ADDR, 0);
|
|
+}
|
|
+
|
|
+static void xgene_xgmac_reset(struct xgene_enet_pdata *pdata)
|
|
+{
|
|
+ xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_0, HSTMACRST);
|
|
+ xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_0, 0);
|
|
+}
|
|
+
|
|
+static void xgene_xgmac_set_mac_addr(struct xgene_enet_pdata *pdata)
|
|
+{
|
|
+ u32 addr0, addr1;
|
|
+ u8 *dev_addr = pdata->ndev->dev_addr;
|
|
+
|
|
+ addr0 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
|
|
+ (dev_addr[1] << 8) | dev_addr[0];
|
|
+ addr1 = (dev_addr[5] << 24) | (dev_addr[4] << 16);
|
|
+
|
|
+ xgene_enet_wr_mac(pdata, HSTMACADR_LSW_ADDR, addr0);
|
|
+ xgene_enet_wr_mac(pdata, HSTMACADR_MSW_ADDR, addr1);
|
|
+}
|
|
+
|
|
+static u32 xgene_enet_link_status(struct xgene_enet_pdata *pdata)
|
|
+{
|
|
+ u32 data;
|
|
+
|
|
+ xgene_enet_rd_csr(pdata, XG_LINK_STATUS_ADDR, &data);
|
|
+
|
|
+ return data;
|
|
+}
|
|
+
|
|
+static void xgene_xgmac_init(struct xgene_enet_pdata *pdata)
|
|
+{
|
|
+ u32 data;
|
|
+
|
|
+ xgene_xgmac_reset(pdata);
|
|
+
|
|
+ xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data);
|
|
+ data |= HSTPPEN;
|
|
+ data &= ~HSTLENCHK;
|
|
+ xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data);
|
|
+
|
|
+ xgene_enet_wr_mac(pdata, HSTMAXFRAME_LENGTH_ADDR, 0x06000600);
|
|
+ xgene_xgmac_set_mac_addr(pdata);
|
|
+
|
|
+ xgene_enet_rd_csr(pdata, XG_RSIF_CONFIG_REG_ADDR, &data);
|
|
+ data |= CFG_RSIF_FPBUFF_TIMEOUT_EN;
|
|
+ xgene_enet_wr_csr(pdata, XG_RSIF_CONFIG_REG_ADDR, data);
|
|
+
|
|
+ xgene_enet_wr_csr(pdata, XG_CFG_BYPASS_ADDR, RESUME_TX);
|
|
+ xgene_enet_wr_csr(pdata, XGENET_RX_DV_GATE_REG_0_ADDR, 0);
|
|
+ xgene_enet_rd_csr(pdata, XG_ENET_SPARE_CFG_REG_ADDR, &data);
|
|
+ data |= BIT(12);
|
|
+ xgene_enet_wr_csr(pdata, XG_ENET_SPARE_CFG_REG_ADDR, data);
|
|
+ xgene_enet_wr_csr(pdata, XG_ENET_SPARE_CFG_REG_1_ADDR, 0x82);
|
|
+}
|
|
+
|
|
+static void xgene_xgmac_rx_enable(struct xgene_enet_pdata *pdata)
|
|
+{
|
|
+ u32 data;
|
|
+
|
|
+ xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data);
|
|
+ xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data | HSTRFEN);
|
|
+}
|
|
+
|
|
+static void xgene_xgmac_tx_enable(struct xgene_enet_pdata *pdata)
|
|
+{
|
|
+ u32 data;
|
|
+
|
|
+ xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data);
|
|
+ xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data | HSTTFEN);
|
|
+}
|
|
+
|
|
+static void xgene_xgmac_rx_disable(struct xgene_enet_pdata *pdata)
|
|
+{
|
|
+ u32 data;
|
|
+
|
|
+ xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data);
|
|
+ xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data & ~HSTRFEN);
|
|
+}
|
|
+
|
|
+static void xgene_xgmac_tx_disable(struct xgene_enet_pdata *pdata)
|
|
+{
|
|
+ u32 data;
|
|
+
|
|
+ xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data);
|
|
+ xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data & ~HSTTFEN);
|
|
+}
|
|
+
|
|
+static void xgene_enet_reset(struct xgene_enet_pdata *pdata)
|
|
+{
|
|
+ clk_prepare_enable(pdata->clk);
|
|
+ clk_disable_unprepare(pdata->clk);
|
|
+ clk_prepare_enable(pdata->clk);
|
|
+
|
|
+ xgene_enet_ecc_init(pdata);
|
|
+ xgene_enet_config_ring_if_assoc(pdata);
|
|
+}
|
|
+
|
|
+static void xgene_enet_xgcle_bypass(struct xgene_enet_pdata *pdata,
|
|
+ u32 dst_ring_num, u16 bufpool_id)
|
|
+{
|
|
+ u32 cb, fpsel;
|
|
+
|
|
+ xgene_enet_rd_csr(pdata, XCLE_BYPASS_REG0_ADDR, &cb);
|
|
+ cb |= CFG_CLE_BYPASS_EN0;
|
|
+ CFG_CLE_IP_PROTOCOL0_SET(&cb, 3);
|
|
+ xgene_enet_wr_csr(pdata, XCLE_BYPASS_REG0_ADDR, cb);
|
|
+
|
|
+ fpsel = xgene_enet_ring_bufnum(bufpool_id) - 0x20;
|
|
+ xgene_enet_rd_csr(pdata, XCLE_BYPASS_REG1_ADDR, &cb);
|
|
+ CFG_CLE_DSTQID0_SET(&cb, dst_ring_num);
|
|
+ CFG_CLE_FPSEL0_SET(&cb, fpsel);
|
|
+ xgene_enet_wr_csr(pdata, XCLE_BYPASS_REG1_ADDR, cb);
|
|
+}
|
|
+
|
|
+static void xgene_enet_shutdown(struct xgene_enet_pdata *pdata)
|
|
+{
|
|
+ clk_disable_unprepare(pdata->clk);
|
|
+}
|
|
+
|
|
+void xgene_enet_link_state(struct work_struct *work)
|
|
+{
|
|
+ struct xgene_enet_pdata *pdata = container_of(to_delayed_work(work),
|
|
+ struct xgene_enet_pdata, link_work);
|
|
+ struct net_device *ndev = pdata->ndev;
|
|
+ u32 link_status, poll_interval;
|
|
+
|
|
+ link_status = xgene_enet_link_status(pdata);
|
|
+ if (link_status) {
|
|
+ if (!netif_carrier_ok(ndev)) {
|
|
+ netif_carrier_on(ndev);
|
|
+ xgene_xgmac_init(pdata);
|
|
+ xgene_xgmac_rx_enable(pdata);
|
|
+ xgene_xgmac_tx_enable(pdata);
|
|
+ netdev_info(ndev, "Link is Up - 10Gbps\n");
|
|
+ }
|
|
+ poll_interval = PHY_POLL_LINK_ON;
|
|
+ } else {
|
|
+ if (netif_carrier_ok(ndev)) {
|
|
+ xgene_xgmac_rx_disable(pdata);
|
|
+ xgene_xgmac_tx_disable(pdata);
|
|
+ netif_carrier_off(ndev);
|
|
+ netdev_info(ndev, "Link is Down\n");
|
|
+ }
|
|
+ poll_interval = PHY_POLL_LINK_OFF;
|
|
+ }
|
|
+
|
|
+ schedule_delayed_work(&pdata->link_work, poll_interval);
|
|
+}
|
|
+
|
|
+struct xgene_mac_ops xgene_xgmac_ops = {
|
|
+ .init = xgene_xgmac_init,
|
|
+ .reset = xgene_xgmac_reset,
|
|
+ .rx_enable = xgene_xgmac_rx_enable,
|
|
+ .tx_enable = xgene_xgmac_tx_enable,
|
|
+ .rx_disable = xgene_xgmac_rx_disable,
|
|
+ .tx_disable = xgene_xgmac_tx_disable,
|
|
+ .set_mac_addr = xgene_xgmac_set_mac_addr,
|
|
+};
|
|
+
|
|
+struct xgene_port_ops xgene_xgport_ops = {
|
|
+ .reset = xgene_enet_reset,
|
|
+ .cle_bypass = xgene_enet_xgcle_bypass,
|
|
+ .shutdown = xgene_enet_shutdown,
|
|
+};
|
|
diff --git a/drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.h b/drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.h
|
|
new file mode 100644
|
|
index 0000000..d2d59e7
|
|
--- /dev/null
|
|
+++ b/drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.h
|
|
@@ -0,0 +1,57 @@
|
|
+/* Applied Micro X-Gene SoC Ethernet Driver
|
|
+ *
|
|
+ * Copyright (c) 2014, Applied Micro Circuits Corporation
|
|
+ * Authors: Iyappan Subramanian <isubramanian@apm.com>
|
|
+ * Keyur Chudgar <kchudgar@apm.com>
|
|
+ *
|
|
+ * This program is free software; you can redistribute it and/or modify it
|
|
+ * under the terms of the GNU General Public License as published by the
|
|
+ * Free Software Foundation; either version 2 of the License, or (at your
|
|
+ * option) any later version.
|
|
+ *
|
|
+ * This program is distributed in the hope that it will be useful,
|
|
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
+ * GNU General Public License for more details.
|
|
+ *
|
|
+ * You should have received a copy of the GNU General Public License
|
|
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
|
|
+ */
|
|
+
|
|
+#ifndef __XGENE_ENET_XGMAC_H__
|
|
+#define __XGENE_ENET_XGMAC_H__
|
|
+
|
|
+#define BLOCK_AXG_MAC_OFFSET 0x0800
|
|
+#define BLOCK_AXG_MAC_CSR_OFFSET 0x2000
|
|
+
|
|
+#define AXGMAC_CONFIG_0 0x0000
|
|
+#define AXGMAC_CONFIG_1 0x0004
|
|
+#define HSTMACRST BIT(31)
|
|
+#define HSTTCTLEN BIT(31)
|
|
+#define HSTTFEN BIT(30)
|
|
+#define HSTRCTLEN BIT(29)
|
|
+#define HSTRFEN BIT(28)
|
|
+#define HSTPPEN BIT(7)
|
|
+#define HSTDRPLT64 BIT(5)
|
|
+#define HSTLENCHK BIT(3)
|
|
+#define HSTMACADR_LSW_ADDR 0x0010
|
|
+#define HSTMACADR_MSW_ADDR 0x0014
|
|
+#define HSTMAXFRAME_LENGTH_ADDR 0x0020
|
|
+
|
|
+#define XG_RSIF_CONFIG_REG_ADDR 0x00a0
|
|
+#define XCLE_BYPASS_REG0_ADDR 0x0160
|
|
+#define XCLE_BYPASS_REG1_ADDR 0x0164
|
|
+#define XG_CFG_BYPASS_ADDR 0x0204
|
|
+#define XG_LINK_STATUS_ADDR 0x0228
|
|
+#define XG_ENET_SPARE_CFG_REG_ADDR 0x040c
|
|
+#define XG_ENET_SPARE_CFG_REG_1_ADDR 0x0410
|
|
+#define XGENET_RX_DV_GATE_REG_0_ADDR 0x0804
|
|
+
|
|
+#define PHY_POLL_LINK_ON (10 * HZ)
|
|
+#define PHY_POLL_LINK_OFF (PHY_POLL_LINK_ON / 5)
|
|
+
|
|
+void xgene_enet_link_state(struct work_struct *work);
|
|
+extern struct xgene_mac_ops xgene_xgmac_ops;
|
|
+extern struct xgene_port_ops xgene_xgport_ops;
|
|
+
|
|
+#endif /* __XGENE_ENET_XGMAC_H__ */
|
|
--
|
|
2.1.0
|
|
|