65 lines
1.9 KiB
Diff
65 lines
1.9 KiB
Diff
From 8069b501d43784d45c8e89bb75083397281b90aa Mon Sep 17 00:00:00 2001
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From: Corentin Labbe <clabbe.montjoie@gmail.com>
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Date: Tue, 31 Oct 2017 09:19:11 +0100
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Subject: [PATCH 8/8] ARM: dts: sunxi: h3/h5: represent the mdio switch used by
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sun8i-h3-emac
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Since dwmac-sun8i could use either an integrated PHY or an external PHY
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(which could be at same MDIO address), we need to represent this selection
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by a MDIO switch.
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Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
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Acked-by: Florian Fainelli <f.fainelli@gmail.com>
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Reviewed-by: Andrew Lunn <andrew@lunn.ch>
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Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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---
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arch/arm/boot/dts/sunxi-h3-h5.dtsi | 31 +++++++++++++++++++++++++++----
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1 file changed, 27 insertions(+), 4 deletions(-)
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diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
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index eb200622afac..6919a0544fe7 100644
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--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
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+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
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@@ -408,11 +408,34 @@
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mdio: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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- int_mii_phy: ethernet-phy@1 {
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- compatible = "ethernet-phy-ieee802.3-c22";
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+ compatible = "snps,dwmac-mdio";
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+ };
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+
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+ mdio-mux {
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+ compatible = "allwinner,sun8i-h3-mdio-mux";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ mdio-parent-bus = <&mdio>;
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+ /* Only one MDIO is usable at the time */
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+ internal_mdio: mdio@1 {
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+ compatible = "allwinner,sun8i-h3-mdio-internal";
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reg = <1>;
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- clocks = <&ccu CLK_BUS_EPHY>;
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- resets = <&ccu RST_BUS_EPHY>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ int_mii_phy: ethernet-phy@1 {
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+ compatible = "ethernet-phy-ieee802.3-c22";
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+ reg = <1>;
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+ clocks = <&ccu CLK_BUS_EPHY>;
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+ resets = <&ccu RST_BUS_EPHY>;
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+ };
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+ };
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+
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+ external_mdio: mdio@2 {
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+ reg = <2>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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};
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};
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};
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--
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2.11.0
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