62 lines
1.9 KiB
Diff
62 lines
1.9 KiB
Diff
From 303b9462705deb7f35fef42497f6153a9477d3da Mon Sep 17 00:00:00 2001
|
|
From: Corentin Labbe <clabbe.montjoie@gmail.com>
|
|
Date: Tue, 31 Oct 2017 09:19:10 +0100
|
|
Subject: [PATCH 7/8] arm: dts: sunxi: h3/h5: Restore EMAC changes
|
|
|
|
The original dwmac-sun8i DT bindings have some issue on how to handle
|
|
integrated PHY and was reverted in last RC of 4.13.
|
|
But now we have a solution so we need to get back that was reverted.
|
|
|
|
This patch restore sunxi-h3-h5.dtsi
|
|
This reverts partially commit fe45174b72ae ("arm: dts: sunxi: Revert EMAC changes")
|
|
|
|
Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
|
|
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
|
|
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
|
|
---
|
|
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 28 +++++++++++++++++++++++++++-
|
|
1 file changed, 27 insertions(+), 1 deletion(-)
|
|
|
|
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
|
|
index 11240a8313c2..eb200622afac 100644
|
|
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
|
|
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
|
|
@@ -391,7 +391,33 @@
|
|
clocks = <&osc24M>;
|
|
};
|
|
|
|
- spi0: spi@01c68000 {
|
|
+ emac: ethernet@1c30000 {
|
|
+ compatible = "allwinner,sun8i-h3-emac";
|
|
+ syscon = <&syscon>;
|
|
+ reg = <0x01c30000 0x10000>;
|
|
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "macirq";
|
|
+ resets = <&ccu RST_BUS_EMAC>;
|
|
+ reset-names = "stmmaceth";
|
|
+ clocks = <&ccu CLK_BUS_EMAC>;
|
|
+ clock-names = "stmmaceth";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ status = "disabled";
|
|
+
|
|
+ mdio: mdio {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ int_mii_phy: ethernet-phy@1 {
|
|
+ compatible = "ethernet-phy-ieee802.3-c22";
|
|
+ reg = <1>;
|
|
+ clocks = <&ccu CLK_BUS_EPHY>;
|
|
+ resets = <&ccu RST_BUS_EPHY>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ spi0: spi@1c68000 {
|
|
compatible = "allwinner,sun8i-h3-spi";
|
|
reg = <0x01c68000 0x1000>;
|
|
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
|
--
|
|
2.11.0
|
|
|