120 lines
4.0 KiB
Diff
120 lines
4.0 KiB
Diff
From: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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Subject: [PATCH] ARM: orion: provide C-style interrupt handler for
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MULTI_IRQ_HANDLER
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Date: Thu, 16 Jan 2014 09:10:31 +0100
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Message-Id: <1389859831-9883-1-git-send-email-sebastian.hesselbarth@gmail.com>
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DT-enabled Marvell Kirkwood and Dove SoCs make use of an irqchip
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driver. As expected for irqchip drivers, it uses a C-style
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interrupt handler and therefore selects MULTI_IRQ_HANDLER.
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Now, compiling a kernel with both non-DT and DT support enabled,
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selecting MULTI_IRQ_HANDLER will break ASM irq handler used by
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non-DT boards.
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Therefore, we provide a C-style irq handler even for non-DT boards,
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if MULTI_IRQ_HANDLER is set. By installing the C-style irq handler
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in orion_irq_init this is transparent to all non-DT board files.
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While the regression report was filed on Marvell Kirkwood, also
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Marvell Dove non-DT boards are affected and fixed by this patch.
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Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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Tested-by: Ian Campbell <ijc@hellion.org.uk>
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Reported-by: Ian Campbell <ijc@hellion.org.uk>
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Fixes: 2326f04321a9 ("ARM: kirkwood: convert to DT irqchip and clocksource")
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Fixes: f07d73e33d0e ("ARM: dove: convert to DT irqchip and clocksource")
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---
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Compared to the two patch version sent on Ian's regression report,
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I cooked this down to a single patch only touching plat-orion/irq.c.
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I also dropped Orion5x and MV78x00, as they not yet select MULTI_IRQ_HANDLER
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at all. Instead I added a comment about taking care of them, as soon as
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they move over to an irqchip driver themselves.
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I have not yet Cc'ed this patch to -stable to get some discussion and
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an Acked-by from Jason or Andrew, too.
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Cc: Jason Cooper <jason@lakedaemon.net>
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Cc: Andrew Lunn <andrew@lunn.ch>
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Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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Cc: Russell King <linux@arm.linux.org.uk>
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Cc: Ian Campbell <ijc@hellion.org.uk>
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Cc: linux-arm-kernel@lists.infradead.org
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Cc: linux-kernel@vger.kernel.org
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---
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arch/arm/plat-orion/irq.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++
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1 file changed, 47 insertions(+)
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diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c
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index c492e1b3dfdb..807df142444b 100644
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--- a/arch/arm/plat-orion/irq.c
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+++ b/arch/arm/plat-orion/irq.c
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@@ -15,8 +15,51 @@
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#include <linux/io.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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+#include <asm/exception.h>
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#include <plat/irq.h>
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#include <plat/orion-gpio.h>
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+#include <mach/bridge-regs.h>
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+
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+#ifdef CONFIG_MULTI_IRQ_HANDLER
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+/*
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+ * Compiling with both non-DT and DT support enabled, will
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+ * break asm irq handler used by non-DT boards. Therefore,
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+ * we provide a C-style irq handler even for non-DT boards,
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+ * if MULTI_IRQ_HANDLER is set.
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+ *
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+ * Notes:
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+ * - this is prepared for Kirkwood and Dove only, update
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+ * accordingly if you add Orion5x or MV78x00.
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+ * - Orion5x uses different macro names and has only one
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+ * set of CAUSE/MASK registers.
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+ * - MV78x00 uses the same macro names but has a third
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+ * set of CAUSE/MASK registers.
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+ *
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+ */
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+
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+static void __iomem *orion_irq_base = IRQ_VIRT_BASE;
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+
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+asmlinkage void
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+__exception_irq_entry orion_legacy_handle_irq(struct pt_regs *regs)
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+{
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+ u32 stat;
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+
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+ stat = readl_relaxed(orion_irq_base + IRQ_CAUSE_LOW_OFF);
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+ stat &= readl_relaxed(orion_irq_base + IRQ_MASK_LOW_OFF);
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+ if (stat) {
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+ unsigned int hwirq = __fls(stat);
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+ handle_IRQ(hwirq, regs);
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+ return;
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+ }
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+ stat = readl_relaxed(orion_irq_base + IRQ_CAUSE_HIGH_OFF);
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+ stat &= readl_relaxed(orion_irq_base + IRQ_MASK_HIGH_OFF);
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+ if (stat) {
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+ unsigned int hwirq = 32 + __fls(stat);
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+ handle_IRQ(hwirq, regs);
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+ return;
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+ }
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+}
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+#endif
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void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
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{
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@@ -35,6 +78,10 @@ void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
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ct->chip.irq_unmask = irq_gc_mask_set_bit;
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irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_MASK_CACHE,
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IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
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+
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+#ifdef CONFIG_MULTI_IRQ_HANDLER
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+ set_handle_irq(orion_legacy_handle_irq);
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+#endif
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}
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#ifdef CONFIG_OF
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--
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1.8.5.2
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