362 lines
10 KiB
Diff
362 lines
10 KiB
Diff
From: Frank Rowand <frank.rowand@am.sony.com>
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Date: Mon, 19 Sep 2011 14:51:14 -0700
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Subject: [PATCH] preempt-rt: Convert arm boot_lock to raw
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Origin: https://www.kernel.org/pub/linux/kernel/projects/rt/3.14/patches-3.14.0-rt1.tar.xz
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The arm boot_lock is used by the secondary processor startup code. The locking
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task is the idle thread, which has idle->sched_class == &idle_sched_class.
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idle_sched_class->enqueue_task == NULL, so if the idle task blocks on the
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lock, the attempt to wake it when the lock becomes available will fail:
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try_to_wake_up()
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...
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activate_task()
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enqueue_task()
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p->sched_class->enqueue_task(rq, p, flags)
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Fix by converting boot_lock to a raw spin lock.
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Signed-off-by: Frank Rowand <frank.rowand@am.sony.com>
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Link: http://lkml.kernel.org/r/4E77B952.3010606@am.sony.com
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Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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---
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arch/arm/mach-exynos/platsmp.c | 12 ++++++------
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arch/arm/mach-msm/platsmp.c | 10 +++++-----
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arch/arm/mach-omap2/omap-smp.c | 10 +++++-----
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arch/arm/mach-prima2/platsmp.c | 10 +++++-----
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arch/arm/mach-spear/platsmp.c | 10 +++++-----
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arch/arm/mach-sti/platsmp.c | 10 +++++-----
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arch/arm/mach-ux500/platsmp.c | 10 +++++-----
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arch/arm/plat-versatile/platsmp.c | 10 +++++-----
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8 files changed, 41 insertions(+), 41 deletions(-)
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--- a/arch/arm/mach-exynos/platsmp.c
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+++ b/arch/arm/mach-exynos/platsmp.c
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@@ -71,7 +71,7 @@ static void __iomem *scu_base_addr(void)
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return (void __iomem *)(S5P_VA_SCU);
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}
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-static DEFINE_SPINLOCK(boot_lock);
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+static DEFINE_RAW_SPINLOCK(boot_lock);
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static void exynos_secondary_init(unsigned int cpu)
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{
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@@ -84,8 +84,8 @@ static void exynos_secondary_init(unsign
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/*
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* Synchronise with the boot thread.
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*/
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- spin_lock(&boot_lock);
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- spin_unlock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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}
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static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
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@@ -97,7 +97,7 @@ static int exynos_boot_secondary(unsigne
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* Set synchronisation state between this boot processor
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* and the secondary one
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*/
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- spin_lock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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/*
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* The secondary processor is waiting to be released from
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@@ -126,7 +126,7 @@ static int exynos_boot_secondary(unsigne
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if (timeout == 0) {
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printk(KERN_ERR "cpu1 power enable failed");
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- spin_unlock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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return -ETIMEDOUT;
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}
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}
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@@ -165,7 +165,7 @@ static int exynos_boot_secondary(unsigne
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* now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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- spin_unlock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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return pen_release != -1 ? -ENOSYS : 0;
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}
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--- a/arch/arm/mach-msm/platsmp.c
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+++ b/arch/arm/mach-msm/platsmp.c
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@@ -30,7 +30,7 @@
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extern void msm_secondary_startup(void);
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-static DEFINE_SPINLOCK(boot_lock);
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+static DEFINE_RAW_SPINLOCK(boot_lock);
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static inline int get_core_count(void)
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{
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@@ -50,8 +50,8 @@ static void msm_secondary_init(unsigned
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/*
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* Synchronise with the boot thread.
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*/
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- spin_lock(&boot_lock);
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- spin_unlock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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}
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static void prepare_cold_cpu(unsigned int cpu)
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@@ -88,7 +88,7 @@ static int msm_boot_secondary(unsigned i
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* set synchronisation state between this boot processor
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* and the secondary one
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*/
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- spin_lock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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/*
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* The secondary processor is waiting to be released from
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@@ -121,7 +121,7 @@ static int msm_boot_secondary(unsigned i
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* now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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- spin_unlock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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return pen_release != -1 ? -ENOSYS : 0;
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}
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--- a/arch/arm/mach-omap2/omap-smp.c
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+++ b/arch/arm/mach-omap2/omap-smp.c
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@@ -42,7 +42,7 @@
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/* SCU base address */
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static void __iomem *scu_base;
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-static DEFINE_SPINLOCK(boot_lock);
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+static DEFINE_RAW_SPINLOCK(boot_lock);
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void __iomem *omap4_get_scu_base(void)
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{
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@@ -73,8 +73,8 @@ static void omap4_secondary_init(unsigne
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/*
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* Synchronise with the boot thread.
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*/
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- spin_lock(&boot_lock);
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- spin_unlock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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}
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static int omap4_boot_secondary(unsigned int cpu, struct task_struct *idle)
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@@ -88,7 +88,7 @@ static int omap4_boot_secondary(unsigned
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* Set synchronisation state between this boot processor
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* and the secondary one
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*/
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- spin_lock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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/*
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* Update the AuxCoreBoot0 with boot state for secondary core.
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@@ -165,7 +165,7 @@ static int omap4_boot_secondary(unsigned
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* Now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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- spin_unlock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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return 0;
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}
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--- a/arch/arm/mach-prima2/platsmp.c
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+++ b/arch/arm/mach-prima2/platsmp.c
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@@ -23,7 +23,7 @@
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static void __iomem *scu_base;
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static void __iomem *rsc_base;
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-static DEFINE_SPINLOCK(boot_lock);
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+static DEFINE_RAW_SPINLOCK(boot_lock);
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static struct map_desc scu_io_desc __initdata = {
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.length = SZ_4K,
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@@ -56,8 +56,8 @@ static void sirfsoc_secondary_init(unsig
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/*
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* Synchronise with the boot thread.
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*/
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- spin_lock(&boot_lock);
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- spin_unlock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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}
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static struct of_device_id rsc_ids[] = {
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@@ -95,7 +95,7 @@ static int sirfsoc_boot_secondary(unsign
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/* make sure write buffer is drained */
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mb();
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- spin_lock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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/*
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* The secondary processor is waiting to be released from
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@@ -127,7 +127,7 @@ static int sirfsoc_boot_secondary(unsign
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* now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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- spin_unlock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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return pen_release != -1 ? -ENOSYS : 0;
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}
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--- a/arch/arm/mach-spear/platsmp.c
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+++ b/arch/arm/mach-spear/platsmp.c
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@@ -20,7 +20,7 @@
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#include <mach/spear.h>
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#include "generic.h"
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-static DEFINE_SPINLOCK(boot_lock);
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+static DEFINE_RAW_SPINLOCK(boot_lock);
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static void __iomem *scu_base = IOMEM(VA_SCU_BASE);
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@@ -36,8 +36,8 @@ static void spear13xx_secondary_init(uns
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/*
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* Synchronise with the boot thread.
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*/
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- spin_lock(&boot_lock);
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- spin_unlock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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}
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static int spear13xx_boot_secondary(unsigned int cpu, struct task_struct *idle)
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@@ -48,7 +48,7 @@ static int spear13xx_boot_secondary(unsi
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* set synchronisation state between this boot processor
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* and the secondary one
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*/
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- spin_lock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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/*
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* The secondary processor is waiting to be released from
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@@ -75,7 +75,7 @@ static int spear13xx_boot_secondary(unsi
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* now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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- spin_unlock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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return pen_release != -1 ? -ENOSYS : 0;
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}
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--- a/arch/arm/mach-sti/platsmp.c
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+++ b/arch/arm/mach-sti/platsmp.c
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@@ -34,7 +34,7 @@ static void write_pen_release(int val)
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sync_cache_w(&pen_release);
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}
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-static DEFINE_SPINLOCK(boot_lock);
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+static DEFINE_RAW_SPINLOCK(boot_lock);
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void sti_secondary_init(unsigned int cpu)
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{
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@@ -49,8 +49,8 @@ void sti_secondary_init(unsigned int cpu
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/*
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* Synchronise with the boot thread.
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*/
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- spin_lock(&boot_lock);
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- spin_unlock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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}
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int sti_boot_secondary(unsigned int cpu, struct task_struct *idle)
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@@ -61,7 +61,7 @@ int sti_boot_secondary(unsigned int cpu,
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* set synchronisation state between this boot processor
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* and the secondary one
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*/
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- spin_lock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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/*
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* The secondary processor is waiting to be released from
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@@ -92,7 +92,7 @@ int sti_boot_secondary(unsigned int cpu,
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* now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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- spin_unlock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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return pen_release != -1 ? -ENOSYS : 0;
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}
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--- a/arch/arm/mach-ux500/platsmp.c
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+++ b/arch/arm/mach-ux500/platsmp.c
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@@ -51,7 +51,7 @@ static void __iomem *scu_base_addr(void)
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return NULL;
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}
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-static DEFINE_SPINLOCK(boot_lock);
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+static DEFINE_RAW_SPINLOCK(boot_lock);
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static void ux500_secondary_init(unsigned int cpu)
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{
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@@ -64,8 +64,8 @@ static void ux500_secondary_init(unsigne
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/*
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* Synchronise with the boot thread.
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*/
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- spin_lock(&boot_lock);
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- spin_unlock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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}
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static int ux500_boot_secondary(unsigned int cpu, struct task_struct *idle)
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@@ -76,7 +76,7 @@ static int ux500_boot_secondary(unsigned
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* set synchronisation state between this boot processor
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* and the secondary one
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*/
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- spin_lock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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/*
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* The secondary processor is waiting to be released from
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@@ -97,7 +97,7 @@ static int ux500_boot_secondary(unsigned
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* now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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- spin_unlock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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return pen_release != -1 ? -ENOSYS : 0;
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}
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--- a/arch/arm/plat-versatile/platsmp.c
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+++ b/arch/arm/plat-versatile/platsmp.c
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@@ -30,7 +30,7 @@ static void write_pen_release(int val)
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sync_cache_w(&pen_release);
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}
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-static DEFINE_SPINLOCK(boot_lock);
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+static DEFINE_RAW_SPINLOCK(boot_lock);
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void versatile_secondary_init(unsigned int cpu)
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{
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@@ -43,8 +43,8 @@ void versatile_secondary_init(unsigned i
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/*
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* Synchronise with the boot thread.
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*/
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- spin_lock(&boot_lock);
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- spin_unlock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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}
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int versatile_boot_secondary(unsigned int cpu, struct task_struct *idle)
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@@ -55,7 +55,7 @@ int versatile_boot_secondary(unsigned in
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* Set synchronisation state between this boot processor
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* and the secondary one
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*/
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- spin_lock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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/*
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* This is really belt and braces; we hold unintended secondary
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@@ -85,7 +85,7 @@ int versatile_boot_secondary(unsigned in
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* now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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- spin_unlock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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return pen_release != -1 ? -ENOSYS : 0;
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}
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