94 lines
3.5 KiB
Diff
94 lines
3.5 KiB
Diff
From foo@baz Mon May 21 21:56:07 CEST 2018
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From: Tom Lendacky <thomas.lendacky@amd.com>
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Date: Thu, 17 May 2018 17:09:18 +0200
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Subject: x86/speculation: Add virtualized speculative store bypass disable support
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From: Tom Lendacky <thomas.lendacky@amd.com>
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commit 11fb0683493b2da112cd64c9dada221b52463bf7 upstream
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Some AMD processors only support a non-architectural means of enabling
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speculative store bypass disable (SSBD). To allow a simplified view of
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this to a guest, an architectural definition has been created through a new
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CPUID bit, 0x80000008_EBX[25], and a new MSR, 0xc001011f. With this, a
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hypervisor can virtualize the existence of this definition and provide an
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architectural method for using SSBD to a guest.
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Add the new CPUID feature, the new MSR and update the existing SSBD
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support to use this MSR when present.
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Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
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Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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Reviewed-by: Borislav Petkov <bp@suse.de>
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Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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---
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arch/x86/include/asm/cpufeatures.h | 1 +
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arch/x86/include/asm/msr-index.h | 2 ++
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arch/x86/kernel/cpu/bugs.c | 4 +++-
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arch/x86/kernel/process.c | 13 ++++++++++++-
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4 files changed, 18 insertions(+), 2 deletions(-)
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--- a/arch/x86/include/asm/cpufeatures.h
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+++ b/arch/x86/include/asm/cpufeatures.h
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@@ -282,6 +282,7 @@
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#define X86_FEATURE_AMD_IBPB (13*32+12) /* "" Indirect Branch Prediction Barrier */
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#define X86_FEATURE_AMD_IBRS (13*32+14) /* "" Indirect Branch Restricted Speculation */
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#define X86_FEATURE_AMD_STIBP (13*32+15) /* "" Single Thread Indirect Branch Predictors */
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+#define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized Speculative Store Bypass Disable */
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/* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */
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#define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */
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--- a/arch/x86/include/asm/msr-index.h
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+++ b/arch/x86/include/asm/msr-index.h
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@@ -347,6 +347,8 @@
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#define MSR_AMD64_SEV_ENABLED_BIT 0
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#define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT)
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+#define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f
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+
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/* Fam 17h MSRs */
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#define MSR_F17H_IRPERF 0xc00000e9
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--- a/arch/x86/kernel/cpu/bugs.c
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+++ b/arch/x86/kernel/cpu/bugs.c
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@@ -205,7 +205,9 @@ static void x86_amd_ssb_disable(void)
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{
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u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask;
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- if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD))
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+ if (boot_cpu_has(X86_FEATURE_VIRT_SSBD))
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+ wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD);
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+ else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD))
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wrmsrl(MSR_AMD64_LS_CFG, msrval);
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}
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--- a/arch/x86/kernel/process.c
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+++ b/arch/x86/kernel/process.c
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@@ -388,6 +388,15 @@ static __always_inline void amd_set_core
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}
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#endif
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+static __always_inline void amd_set_ssb_virt_state(unsigned long tifn)
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+{
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+ /*
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+ * SSBD has the same definition in SPEC_CTRL and VIRT_SPEC_CTRL,
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+ * so ssbd_tif_to_spec_ctrl() just works.
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+ */
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+ wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn));
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+}
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+
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static __always_inline void intel_set_ssb_state(unsigned long tifn)
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{
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u64 msr = x86_spec_ctrl_base | ssbd_tif_to_spec_ctrl(tifn);
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@@ -397,7 +406,9 @@ static __always_inline void intel_set_ss
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static __always_inline void __speculative_store_bypass_update(unsigned long tifn)
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{
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- if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD))
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+ if (static_cpu_has(X86_FEATURE_VIRT_SSBD))
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+ amd_set_ssb_virt_state(tifn);
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+ else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD))
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amd_set_core_ssb_state(tifn);
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else
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intel_set_ssb_state(tifn);
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