67 lines
2.1 KiB
Diff
67 lines
2.1 KiB
Diff
From foo@baz Mon May 21 21:56:07 CEST 2018
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From: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
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Date: Wed, 25 Apr 2018 22:04:23 -0400
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Subject: x86/bugs: Whitelist allowed SPEC_CTRL MSR values
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From: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
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commit 1115a859f33276fe8afb31c60cf9d8e657872558 upstream
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Intel and AMD SPEC_CTRL (0x48) MSR semantics may differ in the
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future (or in fact use different MSRs for the same functionality).
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As such a run-time mechanism is required to whitelist the appropriate MSR
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values.
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[ tglx: Made the variable __ro_after_init ]
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Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
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Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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Reviewed-by: Ingo Molnar <mingo@kernel.org>
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Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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---
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arch/x86/kernel/cpu/bugs.c | 11 +++++++++--
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1 file changed, 9 insertions(+), 2 deletions(-)
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--- a/arch/x86/kernel/cpu/bugs.c
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+++ b/arch/x86/kernel/cpu/bugs.c
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@@ -35,6 +35,12 @@ static void __init ssb_select_mitigation
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*/
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static u64 __ro_after_init x86_spec_ctrl_base;
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+/*
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+ * The vendor and possibly platform specific bits which can be modified in
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+ * x86_spec_ctrl_base.
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+ */
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+static u64 __ro_after_init x86_spec_ctrl_mask = ~SPEC_CTRL_IBRS;
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+
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void __init check_bugs(void)
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{
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identify_boot_cpu();
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@@ -117,7 +123,7 @@ static enum spectre_v2_mitigation spectr
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void x86_spec_ctrl_set(u64 val)
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{
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- if (val & ~(SPEC_CTRL_IBRS | SPEC_CTRL_RDS))
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+ if (val & x86_spec_ctrl_mask)
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WARN_ONCE(1, "SPEC_CTRL MSR value 0x%16llx is unknown.\n", val);
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else
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wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base | val);
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@@ -459,6 +465,7 @@ static enum ssb_mitigation_cmd __init __
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switch (boot_cpu_data.x86_vendor) {
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case X86_VENDOR_INTEL:
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x86_spec_ctrl_base |= SPEC_CTRL_RDS;
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+ x86_spec_ctrl_mask &= ~SPEC_CTRL_RDS;
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x86_spec_ctrl_set(SPEC_CTRL_RDS);
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break;
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case X86_VENDOR_AMD:
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@@ -482,7 +489,7 @@ static void ssb_select_mitigation()
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void x86_spec_ctrl_setup_ap(void)
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{
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if (boot_cpu_has(X86_FEATURE_IBRS))
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- x86_spec_ctrl_set(x86_spec_ctrl_base & (SPEC_CTRL_IBRS | SPEC_CTRL_RDS));
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+ x86_spec_ctrl_set(x86_spec_ctrl_base & ~x86_spec_ctrl_mask);
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}
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#ifdef CONFIG_SYSFS
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