43 lines
1.6 KiB
Diff
43 lines
1.6 KiB
Diff
From foo@baz Mon May 21 21:56:07 CEST 2018
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From: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
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Date: Wed, 16 May 2018 23:18:09 -0400
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Subject: x86/bugs: Rename SSBD_NO to SSB_NO
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From: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
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commit 240da953fcc6a9008c92fae5b1f727ee5ed167ab upstream
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The "336996 Speculative Execution Side Channel Mitigations" from
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May defines this as SSB_NO, hence lets sync-up.
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Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
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Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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---
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arch/x86/include/asm/msr-index.h | 2 +-
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arch/x86/kernel/cpu/common.c | 2 +-
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2 files changed, 2 insertions(+), 2 deletions(-)
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--- a/arch/x86/include/asm/msr-index.h
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+++ b/arch/x86/include/asm/msr-index.h
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@@ -70,7 +70,7 @@
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#define MSR_IA32_ARCH_CAPABILITIES 0x0000010a
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#define ARCH_CAP_RDCL_NO (1 << 0) /* Not susceptible to Meltdown */
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#define ARCH_CAP_IBRS_ALL (1 << 1) /* Enhanced IBRS support */
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-#define ARCH_CAP_SSBD_NO (1 << 4) /*
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+#define ARCH_CAP_SSB_NO (1 << 4) /*
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* Not susceptible to Speculative Store Bypass
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* attack, so no Speculative Store Bypass
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* control required.
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--- a/arch/x86/kernel/cpu/common.c
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+++ b/arch/x86/kernel/cpu/common.c
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@@ -965,7 +965,7 @@ static void __init cpu_set_bug_bits(stru
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rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap);
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if (!x86_match_cpu(cpu_no_spec_store_bypass) &&
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- !(ia32_cap & ARCH_CAP_SSBD_NO))
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+ !(ia32_cap & ARCH_CAP_SSB_NO))
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setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS);
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if (x86_match_cpu(cpu_no_speculation))
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