137 lines
4.3 KiB
Diff
137 lines
4.3 KiB
Diff
From foo@baz Mon May 21 21:56:07 CEST 2018
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From: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
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Date: Wed, 25 Apr 2018 22:04:18 -0400
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Subject: x86/bugs: Read SPEC_CTRL MSR during boot and re-use reserved bits
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From: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
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commit 1b86883ccb8d5d9506529d42dbe1a5257cb30b18 upstream
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The 336996-Speculative-Execution-Side-Channel-Mitigations.pdf refers to all
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the other bits as reserved. The Intel SDM glossary defines reserved as
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implementation specific - aka unknown.
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As such at bootup this must be taken it into account and proper masking for
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the bits in use applied.
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A copy of this document is available at
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https://bugzilla.kernel.org/show_bug.cgi?id=199511
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[ tglx: Made x86_spec_ctrl_base __ro_after_init ]
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Suggested-by: Jon Masters <jcm@redhat.com>
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Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
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Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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Reviewed-by: Borislav Petkov <bp@suse.de>
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Reviewed-by: Ingo Molnar <mingo@kernel.org>
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Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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---
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arch/x86/include/asm/nospec-branch.h | 24 ++++++++++++++++++++----
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arch/x86/kernel/cpu/bugs.c | 28 ++++++++++++++++++++++++++++
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2 files changed, 48 insertions(+), 4 deletions(-)
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--- a/arch/x86/include/asm/nospec-branch.h
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+++ b/arch/x86/include/asm/nospec-branch.h
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@@ -217,6 +217,17 @@ enum spectre_v2_mitigation {
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SPECTRE_V2_IBRS,
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};
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+/*
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+ * The Intel specification for the SPEC_CTRL MSR requires that we
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+ * preserve any already set reserved bits at boot time (e.g. for
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+ * future additions that this kernel is not currently aware of).
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+ * We then set any additional mitigation bits that we want
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+ * ourselves and always use this as the base for SPEC_CTRL.
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+ * We also use this when handling guest entry/exit as below.
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+ */
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+extern void x86_spec_ctrl_set(u64);
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+extern u64 x86_spec_ctrl_get_default(void);
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+
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extern char __indirect_thunk_start[];
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extern char __indirect_thunk_end[];
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@@ -254,8 +265,9 @@ void alternative_msr_write(unsigned int
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static inline void indirect_branch_prediction_barrier(void)
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{
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- alternative_msr_write(MSR_IA32_PRED_CMD, PRED_CMD_IBPB,
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- X86_FEATURE_USE_IBPB);
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+ u64 val = PRED_CMD_IBPB;
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+
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+ alternative_msr_write(MSR_IA32_PRED_CMD, val, X86_FEATURE_USE_IBPB);
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}
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/*
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@@ -266,14 +278,18 @@ static inline void indirect_branch_predi
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*/
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#define firmware_restrict_branch_speculation_start() \
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do { \
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+ u64 val = x86_spec_ctrl_get_default() | SPEC_CTRL_IBRS; \
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+ \
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preempt_disable(); \
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- alternative_msr_write(MSR_IA32_SPEC_CTRL, SPEC_CTRL_IBRS, \
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+ alternative_msr_write(MSR_IA32_SPEC_CTRL, val, \
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X86_FEATURE_USE_IBRS_FW); \
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} while (0)
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#define firmware_restrict_branch_speculation_end() \
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do { \
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- alternative_msr_write(MSR_IA32_SPEC_CTRL, 0, \
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+ u64 val = x86_spec_ctrl_get_default(); \
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+ \
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+ alternative_msr_write(MSR_IA32_SPEC_CTRL, val, \
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X86_FEATURE_USE_IBRS_FW); \
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preempt_enable(); \
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} while (0)
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--- a/arch/x86/kernel/cpu/bugs.c
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+++ b/arch/x86/kernel/cpu/bugs.c
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@@ -28,6 +28,12 @@
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static void __init spectre_v2_select_mitigation(void);
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+/*
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+ * Our boot-time value of the SPEC_CTRL MSR. We read it once so that any
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+ * writes to SPEC_CTRL contain whatever reserved bits have been set.
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+ */
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+static u64 __ro_after_init x86_spec_ctrl_base;
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+
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void __init check_bugs(void)
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{
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identify_boot_cpu();
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@@ -37,6 +43,13 @@ void __init check_bugs(void)
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print_cpu_info(&boot_cpu_data);
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}
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+ /*
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+ * Read the SPEC_CTRL MSR to account for reserved bits which may
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+ * have unknown values.
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+ */
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+ if (boot_cpu_has(X86_FEATURE_IBRS))
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+ rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
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+
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/* Select the proper spectre mitigation before patching alternatives */
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spectre_v2_select_mitigation();
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@@ -95,6 +108,21 @@ static const char *spectre_v2_strings[]
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static enum spectre_v2_mitigation spectre_v2_enabled = SPECTRE_V2_NONE;
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+void x86_spec_ctrl_set(u64 val)
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+{
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+ if (val & ~SPEC_CTRL_IBRS)
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+ WARN_ONCE(1, "SPEC_CTRL MSR value 0x%16llx is unknown.\n", val);
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+ else
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+ wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base | val);
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+}
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+EXPORT_SYMBOL_GPL(x86_spec_ctrl_set);
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+
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+u64 x86_spec_ctrl_get_default(void)
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+{
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+ return x86_spec_ctrl_base;
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+}
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+EXPORT_SYMBOL_GPL(x86_spec_ctrl_get_default);
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+
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#ifdef RETPOLINE
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static bool spectre_v2_bad_module;
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