113 lines
3.8 KiB
Diff
113 lines
3.8 KiB
Diff
From foo@baz Mon May 21 21:56:07 CEST 2018
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From: Thomas Gleixner <tglx@linutronix.de>
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Date: Sat, 12 May 2018 20:49:16 +0200
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Subject: x86/bugs: Expose x86_spec_ctrl_base directly
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From: Thomas Gleixner <tglx@linutronix.de>
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commit fa8ac4988249c38476f6ad678a4848a736373403 upstream
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x86_spec_ctrl_base is the system wide default value for the SPEC_CTRL MSR.
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x86_spec_ctrl_get_default() returns x86_spec_ctrl_base and was intended to
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prevent modification to that variable. Though the variable is read only
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after init and globaly visible already.
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Remove the function and export the variable instead.
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Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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Reviewed-by: Borislav Petkov <bp@suse.de>
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Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
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Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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---
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arch/x86/include/asm/nospec-branch.h | 16 +++++-----------
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arch/x86/include/asm/spec-ctrl.h | 3 ---
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arch/x86/kernel/cpu/bugs.c | 11 +----------
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3 files changed, 6 insertions(+), 24 deletions(-)
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--- a/arch/x86/include/asm/nospec-branch.h
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+++ b/arch/x86/include/asm/nospec-branch.h
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@@ -217,16 +217,7 @@ enum spectre_v2_mitigation {
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SPECTRE_V2_IBRS,
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};
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-/*
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- * The Intel specification for the SPEC_CTRL MSR requires that we
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- * preserve any already set reserved bits at boot time (e.g. for
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- * future additions that this kernel is not currently aware of).
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- * We then set any additional mitigation bits that we want
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- * ourselves and always use this as the base for SPEC_CTRL.
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- * We also use this when handling guest entry/exit as below.
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- */
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extern void x86_spec_ctrl_set(u64);
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-extern u64 x86_spec_ctrl_get_default(void);
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/* The Speculative Store Bypass disable variants */
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enum ssb_mitigation {
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@@ -278,6 +269,9 @@ static inline void indirect_branch_predi
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alternative_msr_write(MSR_IA32_PRED_CMD, val, X86_FEATURE_USE_IBPB);
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}
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+/* The Intel SPEC CTRL MSR base value cache */
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+extern u64 x86_spec_ctrl_base;
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+
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/*
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* With retpoline, we must use IBRS to restrict branch prediction
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* before calling into firmware.
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@@ -286,7 +280,7 @@ static inline void indirect_branch_predi
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*/
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#define firmware_restrict_branch_speculation_start() \
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do { \
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- u64 val = x86_spec_ctrl_get_default() | SPEC_CTRL_IBRS; \
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+ u64 val = x86_spec_ctrl_base | SPEC_CTRL_IBRS; \
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\
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preempt_disable(); \
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alternative_msr_write(MSR_IA32_SPEC_CTRL, val, \
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@@ -295,7 +289,7 @@ do { \
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#define firmware_restrict_branch_speculation_end() \
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do { \
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- u64 val = x86_spec_ctrl_get_default(); \
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+ u64 val = x86_spec_ctrl_base; \
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\
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alternative_msr_write(MSR_IA32_SPEC_CTRL, val, \
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X86_FEATURE_USE_IBRS_FW); \
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--- a/arch/x86/include/asm/spec-ctrl.h
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+++ b/arch/x86/include/asm/spec-ctrl.h
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@@ -47,9 +47,6 @@ void x86_spec_ctrl_restore_host(u64 gues
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extern u64 x86_amd_ls_cfg_base;
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extern u64 x86_amd_ls_cfg_ssbd_mask;
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-/* The Intel SPEC CTRL MSR base value cache */
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-extern u64 x86_spec_ctrl_base;
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-
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static inline u64 ssbd_tif_to_spec_ctrl(u64 tifn)
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{
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BUILD_BUG_ON(TIF_SSBD < SPEC_CTRL_SSBD_SHIFT);
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--- a/arch/x86/kernel/cpu/bugs.c
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+++ b/arch/x86/kernel/cpu/bugs.c
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@@ -36,6 +36,7 @@ static void __init ssb_select_mitigation
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* writes to SPEC_CTRL contain whatever reserved bits have been set.
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*/
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u64 __ro_after_init x86_spec_ctrl_base;
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+EXPORT_SYMBOL_GPL(x86_spec_ctrl_base);
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/*
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* The vendor and possibly platform specific bits which can be modified in
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@@ -141,16 +142,6 @@ void x86_spec_ctrl_set(u64 val)
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}
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EXPORT_SYMBOL_GPL(x86_spec_ctrl_set);
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-u64 x86_spec_ctrl_get_default(void)
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-{
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- u64 msrval = x86_spec_ctrl_base;
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-
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- if (static_cpu_has(X86_FEATURE_SPEC_CTRL))
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- msrval |= ssbd_tif_to_spec_ctrl(current_thread_info()->flags);
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- return msrval;
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-}
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-EXPORT_SYMBOL_GPL(x86_spec_ctrl_get_default);
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-
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void
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x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest)
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{
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