188 lines
5.9 KiB
Diff
188 lines
5.9 KiB
Diff
From foo@baz Mon May 21 21:56:07 CEST 2018
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From: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
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Date: Wed, 25 Apr 2018 22:04:24 -0400
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Subject: x86/bugs/AMD: Add support to disable RDS on Fam[15,16,17]h if requested
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From: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
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commit 764f3c21588a059cd783c6ba0734d4db2d72822d upstream
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AMD does not need the Speculative Store Bypass mitigation to be enabled.
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The parameters for this are already available and can be done via MSR
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C001_1020. Each family uses a different bit in that MSR for this.
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[ tglx: Expose the bit mask via a variable and move the actual MSR fiddling
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into the bugs code as that's the right thing to do and also required
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to prepare for dynamic enable/disable ]
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Suggested-by: Borislav Petkov <bp@suse.de>
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Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
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Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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Reviewed-by: Ingo Molnar <mingo@kernel.org>
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Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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---
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arch/x86/include/asm/cpufeatures.h | 1 +
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arch/x86/include/asm/nospec-branch.h | 4 ++++
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arch/x86/kernel/cpu/amd.c | 26 ++++++++++++++++++++++++++
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arch/x86/kernel/cpu/bugs.c | 27 ++++++++++++++++++++++++++-
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arch/x86/kernel/cpu/common.c | 4 ++++
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5 files changed, 61 insertions(+), 1 deletion(-)
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--- a/arch/x86/include/asm/cpufeatures.h
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+++ b/arch/x86/include/asm/cpufeatures.h
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@@ -215,6 +215,7 @@
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#define X86_FEATURE_USE_IBPB ( 7*32+21) /* "" Indirect Branch Prediction Barrier enabled */
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#define X86_FEATURE_USE_IBRS_FW ( 7*32+22) /* "" Use IBRS during runtime firmware calls */
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#define X86_FEATURE_SPEC_STORE_BYPASS_DISABLE ( 7*32+23) /* "" Disable Speculative Store Bypass. */
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+#define X86_FEATURE_AMD_RDS (7*32+24) /* "" AMD RDS implementation */
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/* Virtualization flags: Linux defined, word 8 */
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#define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */
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--- a/arch/x86/include/asm/nospec-branch.h
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+++ b/arch/x86/include/asm/nospec-branch.h
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@@ -244,6 +244,10 @@ enum ssb_mitigation {
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SPEC_STORE_BYPASS_DISABLE,
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};
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+/* AMD specific Speculative Store Bypass MSR data */
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+extern u64 x86_amd_ls_cfg_base;
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+extern u64 x86_amd_ls_cfg_rds_mask;
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+
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extern char __indirect_thunk_start[];
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extern char __indirect_thunk_end[];
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--- a/arch/x86/kernel/cpu/amd.c
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+++ b/arch/x86/kernel/cpu/amd.c
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@@ -10,6 +10,7 @@
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#include <asm/processor.h>
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#include <asm/apic.h>
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#include <asm/cpu.h>
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+#include <asm/nospec-branch.h>
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#include <asm/smp.h>
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#include <asm/pci-direct.h>
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#include <asm/delay.h>
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@@ -554,6 +555,26 @@ static void bsp_init_amd(struct cpuinfo_
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rdmsrl(MSR_FAM10H_NODE_ID, value);
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nodes_per_socket = ((value >> 3) & 7) + 1;
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}
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+
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+ if (c->x86 >= 0x15 && c->x86 <= 0x17) {
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+ unsigned int bit;
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+
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+ switch (c->x86) {
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+ case 0x15: bit = 54; break;
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+ case 0x16: bit = 33; break;
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+ case 0x17: bit = 10; break;
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+ default: return;
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+ }
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+ /*
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+ * Try to cache the base value so further operations can
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+ * avoid RMW. If that faults, do not enable RDS.
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+ */
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+ if (!rdmsrl_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) {
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+ setup_force_cpu_cap(X86_FEATURE_RDS);
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+ setup_force_cpu_cap(X86_FEATURE_AMD_RDS);
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+ x86_amd_ls_cfg_rds_mask = 1ULL << bit;
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+ }
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+ }
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}
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static void early_detect_mem_encrypt(struct cpuinfo_x86 *c)
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@@ -898,6 +919,11 @@ static void init_amd(struct cpuinfo_x86
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/* AMD CPUs don't reset SS attributes on SYSRET, Xen does. */
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if (!cpu_has(c, X86_FEATURE_XENPV))
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set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS);
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+
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+ if (boot_cpu_has(X86_FEATURE_AMD_RDS)) {
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+ set_cpu_cap(c, X86_FEATURE_RDS);
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+ set_cpu_cap(c, X86_FEATURE_AMD_RDS);
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+ }
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}
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#ifdef CONFIG_X86_32
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--- a/arch/x86/kernel/cpu/bugs.c
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+++ b/arch/x86/kernel/cpu/bugs.c
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@@ -41,6 +41,13 @@ static u64 __ro_after_init x86_spec_ctrl
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*/
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static u64 __ro_after_init x86_spec_ctrl_mask = ~SPEC_CTRL_IBRS;
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+/*
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+ * AMD specific MSR info for Speculative Store Bypass control.
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+ * x86_amd_ls_cfg_rds_mask is initialized in identify_boot_cpu().
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+ */
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+u64 __ro_after_init x86_amd_ls_cfg_base;
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+u64 __ro_after_init x86_amd_ls_cfg_rds_mask;
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+
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void __init check_bugs(void)
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{
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identify_boot_cpu();
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@@ -52,7 +59,8 @@ void __init check_bugs(void)
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/*
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* Read the SPEC_CTRL MSR to account for reserved bits which may
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- * have unknown values.
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+ * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
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+ * init code as it is not enumerated and depends on the family.
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*/
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if (boot_cpu_has(X86_FEATURE_IBRS))
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rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
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@@ -154,6 +162,14 @@ void x86_spec_ctrl_restore_host(u64 gues
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}
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EXPORT_SYMBOL_GPL(x86_spec_ctrl_restore_host);
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+static void x86_amd_rds_enable(void)
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+{
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+ u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_rds_mask;
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+
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+ if (boot_cpu_has(X86_FEATURE_AMD_RDS))
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+ wrmsrl(MSR_AMD64_LS_CFG, msrval);
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+}
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+
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#ifdef RETPOLINE
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static bool spectre_v2_bad_module;
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@@ -443,6 +459,11 @@ static enum ssb_mitigation_cmd __init __
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switch (cmd) {
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case SPEC_STORE_BYPASS_CMD_AUTO:
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+ /*
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+ * AMD platforms by default don't need SSB mitigation.
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+ */
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+ if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
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+ break;
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case SPEC_STORE_BYPASS_CMD_ON:
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mode = SPEC_STORE_BYPASS_DISABLE;
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break;
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@@ -469,6 +490,7 @@ static enum ssb_mitigation_cmd __init __
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x86_spec_ctrl_set(SPEC_CTRL_RDS);
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break;
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case X86_VENDOR_AMD:
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+ x86_amd_rds_enable();
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break;
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}
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}
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@@ -490,6 +512,9 @@ void x86_spec_ctrl_setup_ap(void)
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{
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if (boot_cpu_has(X86_FEATURE_IBRS))
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x86_spec_ctrl_set(x86_spec_ctrl_base & ~x86_spec_ctrl_mask);
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+
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+ if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
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+ x86_amd_rds_enable();
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}
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#ifdef CONFIG_SYSFS
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--- a/arch/x86/kernel/cpu/common.c
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+++ b/arch/x86/kernel/cpu/common.c
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@@ -934,6 +934,10 @@ static const __initconst struct x86_cpu_
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{ X86_VENDOR_CENTAUR, 5, },
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{ X86_VENDOR_INTEL, 5, },
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{ X86_VENDOR_NSC, 5, },
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+ { X86_VENDOR_AMD, 0x12, },
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+ { X86_VENDOR_AMD, 0x11, },
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+ { X86_VENDOR_AMD, 0x10, },
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+ { X86_VENDOR_AMD, 0xf, },
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{ X86_VENDOR_ANY, 4, },
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{}
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};
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