280 lines
8.1 KiB
Diff
280 lines
8.1 KiB
Diff
Subject: preempt-rt: Convert arm boot_lock to raw
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From: Frank Rowand <frank.rowand@am.sony.com>
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Date: Mon, 19 Sep 2011 14:51:14 -0700
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The arm boot_lock is used by the secondary processor startup code. The locking
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task is the idle thread, which has idle->sched_class == &idle_sched_class.
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idle_sched_class->enqueue_task == NULL, so if the idle task blocks on the
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lock, the attempt to wake it when the lock becomes available will fail:
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try_to_wake_up()
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...
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activate_task()
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enqueue_task()
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p->sched_class->enqueue_task(rq, p, flags)
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Fix by converting boot_lock to a raw spin lock.
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Signed-off-by: Frank Rowand <frank.rowand@am.sony.com>
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Link: http://lkml.kernel.org/r/4E77B952.3010606@am.sony.com
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Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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---
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arch/arm/mach-exynos/platsmp.c | 12 ++++++------
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arch/arm/mach-msm/platsmp.c | 10 +++++-----
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arch/arm/mach-omap2/omap-smp.c | 10 +++++-----
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arch/arm/mach-spear13xx/platsmp.c | 10 +++++-----
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arch/arm/mach-ux500/platsmp.c | 10 +++++-----
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arch/arm/plat-versatile/platsmp.c | 10 +++++-----
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6 files changed, 31 insertions(+), 31 deletions(-)
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--- a/arch/arm/mach-exynos/platsmp.c
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+++ b/arch/arm/mach-exynos/platsmp.c
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@@ -71,7 +71,7 @@ static void __iomem *scu_base_addr(void)
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return (void __iomem *)(S5P_VA_SCU);
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}
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-static DEFINE_SPINLOCK(boot_lock);
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+static DEFINE_RAW_SPINLOCK(boot_lock);
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static void __cpuinit exynos_secondary_init(unsigned int cpu)
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{
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@@ -91,8 +91,8 @@ static void __cpuinit exynos_secondary_i
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/*
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* Synchronise with the boot thread.
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*/
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- spin_lock(&boot_lock);
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- spin_unlock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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}
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static int __cpuinit exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
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@@ -104,7 +104,7 @@ static int __cpuinit exynos_boot_seconda
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* Set synchronisation state between this boot processor
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* and the secondary one
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*/
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- spin_lock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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/*
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* The secondary processor is waiting to be released from
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@@ -133,7 +133,7 @@ static int __cpuinit exynos_boot_seconda
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if (timeout == 0) {
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printk(KERN_ERR "cpu1 power enable failed");
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- spin_unlock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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return -ETIMEDOUT;
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}
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}
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@@ -161,7 +161,7 @@ static int __cpuinit exynos_boot_seconda
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* now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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- spin_unlock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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return pen_release != -1 ? -ENOSYS : 0;
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}
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--- a/arch/arm/mach-msm/platsmp.c
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+++ b/arch/arm/mach-msm/platsmp.c
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@@ -31,7 +31,7 @@
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extern void msm_secondary_startup(void);
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-static DEFINE_SPINLOCK(boot_lock);
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+static DEFINE_RAW_SPINLOCK(boot_lock);
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static inline int get_core_count(void)
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{
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@@ -58,8 +58,8 @@ static void __cpuinit msm_secondary_init
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/*
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* Synchronise with the boot thread.
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*/
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- spin_lock(&boot_lock);
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- spin_unlock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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}
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static __cpuinit void prepare_cold_cpu(unsigned int cpu)
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@@ -96,7 +96,7 @@ static int __cpuinit msm_boot_secondary(
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* set synchronisation state between this boot processor
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* and the secondary one
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*/
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- spin_lock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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/*
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* The secondary processor is waiting to be released from
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@@ -130,7 +130,7 @@ static int __cpuinit msm_boot_secondary(
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* now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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- spin_unlock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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return pen_release != -1 ? -ENOSYS : 0;
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}
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--- a/arch/arm/mach-omap2/omap-smp.c
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+++ b/arch/arm/mach-omap2/omap-smp.c
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@@ -45,7 +45,7 @@ u16 pm44xx_errata;
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/* SCU base address */
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static void __iomem *scu_base;
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-static DEFINE_SPINLOCK(boot_lock);
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+static DEFINE_RAW_SPINLOCK(boot_lock);
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void __iomem *omap4_get_scu_base(void)
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{
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@@ -76,8 +76,8 @@ static void __cpuinit omap4_secondary_in
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/*
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* Synchronise with the boot thread.
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*/
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- spin_lock(&boot_lock);
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- spin_unlock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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}
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static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *idle)
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@@ -90,7 +90,7 @@ static int __cpuinit omap4_boot_secondar
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* Set synchronisation state between this boot processor
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* and the secondary one
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*/
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- spin_lock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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/*
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* Update the AuxCoreBoot0 with boot state for secondary core.
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@@ -163,7 +163,7 @@ static int __cpuinit omap4_boot_secondar
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* Now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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- spin_unlock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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return 0;
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}
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--- a/arch/arm/mach-spear13xx/platsmp.c
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+++ b/arch/arm/mach-spear13xx/platsmp.c
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@@ -21,7 +21,7 @@
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#include <mach/spear.h>
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#include <mach/generic.h>
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-static DEFINE_SPINLOCK(boot_lock);
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+static DEFINE_RAW_SPINLOCK(boot_lock);
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static void __iomem *scu_base = IOMEM(VA_SCU_BASE);
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@@ -44,8 +44,8 @@ static void __cpuinit spear13xx_secondar
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/*
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* Synchronise with the boot thread.
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*/
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- spin_lock(&boot_lock);
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- spin_unlock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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}
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static int __cpuinit spear13xx_boot_secondary(unsigned int cpu, struct task_struct *idle)
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@@ -56,7 +56,7 @@ static int __cpuinit spear13xx_boot_seco
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* set synchronisation state between this boot processor
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* and the secondary one
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*/
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- spin_lock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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/*
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* The secondary processor is waiting to be released from
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@@ -83,7 +83,7 @@ static int __cpuinit spear13xx_boot_seco
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* now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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- spin_unlock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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return pen_release != -1 ? -ENOSYS : 0;
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}
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--- a/arch/arm/mach-ux500/platsmp.c
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+++ b/arch/arm/mach-ux500/platsmp.c
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@@ -50,7 +50,7 @@ static void __iomem *scu_base_addr(void)
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return NULL;
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}
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-static DEFINE_SPINLOCK(boot_lock);
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+static DEFINE_RAW_SPINLOCK(boot_lock);
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static void __cpuinit ux500_secondary_init(unsigned int cpu)
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{
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@@ -70,8 +70,8 @@ static void __cpuinit ux500_secondary_in
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/*
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* Synchronise with the boot thread.
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*/
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- spin_lock(&boot_lock);
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- spin_unlock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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}
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static int __cpuinit ux500_boot_secondary(unsigned int cpu, struct task_struct *idle)
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@@ -82,7 +82,7 @@ static int __cpuinit ux500_boot_secondar
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* set synchronisation state between this boot processor
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* and the secondary one
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*/
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- spin_lock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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/*
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* The secondary processor is waiting to be released from
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@@ -103,7 +103,7 @@ static int __cpuinit ux500_boot_secondar
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* now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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- spin_unlock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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return pen_release != -1 ? -ENOSYS : 0;
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}
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--- a/arch/arm/plat-versatile/platsmp.c
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+++ b/arch/arm/plat-versatile/platsmp.c
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@@ -32,7 +32,7 @@ static void __cpuinit write_pen_release(
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outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
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}
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-static DEFINE_SPINLOCK(boot_lock);
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+static DEFINE_RAW_SPINLOCK(boot_lock);
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void __cpuinit versatile_secondary_init(unsigned int cpu)
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{
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@@ -52,8 +52,8 @@ void __cpuinit versatile_secondary_init(
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/*
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* Synchronise with the boot thread.
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*/
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- spin_lock(&boot_lock);
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- spin_unlock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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}
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int __cpuinit versatile_boot_secondary(unsigned int cpu, struct task_struct *idle)
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@@ -64,7 +64,7 @@ int __cpuinit versatile_boot_secondary(u
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* Set synchronisation state between this boot processor
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* and the secondary one
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*/
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- spin_lock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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/*
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* This is really belt and braces; we hold unintended secondary
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@@ -94,7 +94,7 @@ int __cpuinit versatile_boot_secondary(u
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* now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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- spin_unlock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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return pen_release != -1 ? -ENOSYS : 0;
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}
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