138 lines
4.0 KiB
Diff
138 lines
4.0 KiB
Diff
From: Roland Vossen <rvossen@broadcom.com>
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Date: Mon, 8 Aug 2011 15:58:49 +0200
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Subject: [PATCH 2/5] staging: brcm80211: simplified register access macro's in
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softmac
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commit b60987a15628046259be17471fd80ba92cf35ed2 upstream.
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Code cleanup. Removed MIPS specific 'sync' instruction since this is not
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required for the chips that this driver supports. MIPS specific macro's
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were now the same as non-MIPS register access macro's and thus have been
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deleted. Also added comment that makes clearer what the benefit of these
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macro's is. Unified big and little end register access macro's.
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Reported-by: Dan Carpenter <error27@gmail.com>
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Reported-by: Julian Calaby <julian.calaby@gmail.com>
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Reviewed-by: Pieter-Paul Giesberts <pieterpg@broadcom.com>
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Signed-off-by: Arend van Spriel <arend@broadcom.com>
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Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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---
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drivers/staging/brcm80211/brcmsmac/types.h | 81 ++++++++++------------------
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1 files changed, 29 insertions(+), 52 deletions(-)
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diff --git a/drivers/staging/brcm80211/brcmsmac/types.h b/drivers/staging/brcm80211/brcmsmac/types.h
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index 360795f..16a1c6a 100644
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--- a/drivers/staging/brcm80211/brcmsmac/types.h
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+++ b/drivers/staging/brcm80211/brcmsmac/types.h
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@@ -320,60 +320,38 @@ do { \
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#define WL_ERROR_ON() (brcm_msg_level & LOG_ERROR_VAL)
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-/* register access macros */
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+/*
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+ * Register access macros.
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+ *
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+ * These macro's take a pointer to the address to read as one of their
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+ * arguments. The macro itself deduces the size of the IO transaction (u8, u16
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+ * or u32). Advantage of this approach in combination with using a struct to
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+ * define the registers in a register block, is that access size and access
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+ * location are defined in only one spot. This reduces the risk of the
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+ * programmer trying to use an unsupported transaction size on a register.
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+ *
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+ * For big endian operation, a byte swap has to be done. Eg, when attempting
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+ * to read byte address 0, byte 3 should be read. This is accomplished
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+ * using an xor ('^') operator.
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+ */
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+
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#ifndef __BIG_ENDIAN
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-#ifndef __mips__
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-#define R_REG(r) \
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- ({\
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- sizeof(*(r)) == sizeof(u8) ? \
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- readb((u8 *)(r)) : \
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- sizeof(*(r)) == sizeof(u16) ? readw((u16 *)(r)) : \
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- readl((u32 *)(r)); \
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- })
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-#else /* __mips__ */
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-#define R_REG(r) \
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- ({ \
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- __typeof(*(r)) __osl_v; \
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- __asm__ __volatile__("sync"); \
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- switch (sizeof(*(r))) { \
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- case sizeof(u8): \
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- __osl_v = readb((u8 *)(r)); \
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- break; \
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- case sizeof(u16): \
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- __osl_v = readw((u16 *)(r)); \
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- break; \
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- case sizeof(u32): \
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- __osl_v = \
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- readl((u32 *)(r)); \
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- break; \
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- } \
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- __asm__ __volatile__("sync"); \
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- __osl_v; \
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- })
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-#endif /* __mips__ */
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+#define SWP2(r) (r)
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+#define SWP3(r) (r)
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+#else
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+#define SWP2(r) ((unsigned long)(r)^2)
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+#define SWP3(r) ((unsigned long)(r)^3)
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+#endif /* __BIG_ENDIAN */
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-#define W_REG(r, v) do { \
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- switch (sizeof(*(r))) { \
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- case sizeof(u8): \
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- writeb((u8)(v), (u8 *)(r)); break; \
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- case sizeof(u16): \
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- writew((u16)(v), (u16 *)(r)); break; \
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- case sizeof(u32): \
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- writel((u32)(v), (u32 *)(r)); break; \
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- }; \
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- } while (0)
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-#else /* __BIG_ENDIAN */
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#define R_REG(r) \
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({ \
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__typeof(*(r)) __osl_v; \
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switch (sizeof(*(r))) { \
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case sizeof(u8): \
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- __osl_v = \
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- readb((u8 *)((unsigned long)(r)^3)); \
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+ __osl_v = readb((u8 *)(SWP3(r))); \
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break; \
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case sizeof(u16): \
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- __osl_v = \
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- readw((u16 *)((unsigned long)(r)^2)); \
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+ __osl_v = readw((u16 *)(SWP2(r))); \
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break; \
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case sizeof(u32): \
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__osl_v = readl((u32 *)(r)); \
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@@ -385,17 +363,16 @@ do { \
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#define W_REG(r, v) do { \
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switch (sizeof(*(r))) { \
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case sizeof(u8): \
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- writeb((u8)(v), \
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- (u8 *)((unsigned long)(r)^3)); break; \
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+ writeb((u8)(v), (u8 *)(SWP3(r))); \
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+ break; \
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case sizeof(u16): \
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- writew((u16)(v), \
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- (u16 *)((unsigned long)(r)^2)); break; \
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+ writew((u16)(v), (u16 *)(SWP2(r))); \
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+ break; \
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case sizeof(u32): \
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- writel((u32)(v), \
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- (u32 *)(r)); break; \
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+ writel((u32)(v), (u32 *)(r)); \
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+ break; \
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} \
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} while (0)
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-#endif /* __BIG_ENDIAN */
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#ifdef __mips__
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/*
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--
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1.7.7.3
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