318 lines
10 KiB
Diff
318 lines
10 KiB
Diff
From: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
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Date: Thu, 12 Feb 2015 16:01:13 +0100
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Subject: gpio: omap: use raw locks for locking
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Origin: https://www.kernel.org/pub/linux/kernel/projects/rt/4.1/patches-4.1.3-rt3.tar.xz
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This patch converts gpio_bank.lock from a spin_lock into a
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raw_spin_lock. The call path is to access this lock is always under a
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raw_spin_lock, for instance
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- __setup_irq() holds &desc->lock with irq off
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+ __irq_set_trigger()
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+ omap_gpio_irq_type()
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- handle_level_irq() (runs with irqs off therefore raw locks)
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+ mask_ack_irq()
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+ omap_gpio_mask_irq()
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This fixes the obvious backtrace on -RT. However the locking vs context
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is not and this is not limited to -RT:
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- omap_gpio_irq_type() is called with IRQ off and has an conditional
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call to pm_runtime_get_sync() which may sleep. Either it may happen or
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it may not happen but pm_runtime_get_sync() should not be called with
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irqs off.
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- omap_gpio_debounce() is holding the lock with IRQs off.
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+ omap2_set_gpio_debounce()
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+ clk_prepare_enable()
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+ clk_prepare() this one might sleep.
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The number of users of gpiod_set_debounce() / gpio_set_debounce()
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looks low but still this is not good.
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Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
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---
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drivers/gpio/gpio-omap.c | 78 +++++++++++++++++++++++------------------------
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1 file changed, 39 insertions(+), 39 deletions(-)
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--- a/drivers/gpio/gpio-omap.c
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+++ b/drivers/gpio/gpio-omap.c
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@@ -57,7 +57,7 @@ struct gpio_bank {
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u32 saved_datain;
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u32 level_mask;
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u32 toggle_mask;
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- spinlock_t lock;
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+ raw_spinlock_t lock;
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struct gpio_chip chip;
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struct clk *dbck;
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u32 mod_usage;
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@@ -498,14 +498,14 @@ static int omap_gpio_irq_type(struct irq
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(type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
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return -EINVAL;
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- spin_lock_irqsave(&bank->lock, flags);
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+ raw_spin_lock_irqsave(&bank->lock, flags);
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retval = omap_set_gpio_triggering(bank, offset, type);
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omap_gpio_init_irq(bank, offset);
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if (!omap_gpio_is_input(bank, offset)) {
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- spin_unlock_irqrestore(&bank->lock, flags);
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+ raw_spin_unlock_irqrestore(&bank->lock, flags);
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return -EINVAL;
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}
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- spin_unlock_irqrestore(&bank->lock, flags);
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+ raw_spin_unlock_irqrestore(&bank->lock, flags);
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if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
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__irq_set_handler_locked(d->irq, handle_level_irq);
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@@ -626,14 +626,14 @@ static int omap_set_gpio_wakeup(struct g
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return -EINVAL;
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}
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- spin_lock_irqsave(&bank->lock, flags);
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+ raw_spin_lock_irqsave(&bank->lock, flags);
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if (enable)
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bank->context.wake_en |= gpio_bit;
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else
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bank->context.wake_en &= ~gpio_bit;
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writel_relaxed(bank->context.wake_en, bank->base + bank->regs->wkup_en);
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- spin_unlock_irqrestore(&bank->lock, flags);
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+ raw_spin_unlock_irqrestore(&bank->lock, flags);
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return 0;
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}
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@@ -668,7 +668,7 @@ static int omap_gpio_request(struct gpio
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if (!BANK_USED(bank))
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pm_runtime_get_sync(bank->dev);
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- spin_lock_irqsave(&bank->lock, flags);
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+ raw_spin_lock_irqsave(&bank->lock, flags);
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/* Set trigger to none. You need to enable the desired trigger with
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* request_irq() or set_irq_type(). Only do this if the IRQ line has
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* not already been requested.
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@@ -678,7 +678,7 @@ static int omap_gpio_request(struct gpio
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omap_enable_gpio_module(bank, offset);
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}
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bank->mod_usage |= BIT(offset);
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- spin_unlock_irqrestore(&bank->lock, flags);
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+ raw_spin_unlock_irqrestore(&bank->lock, flags);
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return 0;
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}
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@@ -688,11 +688,11 @@ static void omap_gpio_free(struct gpio_c
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struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
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unsigned long flags;
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- spin_lock_irqsave(&bank->lock, flags);
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+ raw_spin_lock_irqsave(&bank->lock, flags);
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bank->mod_usage &= ~(BIT(offset));
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omap_disable_gpio_module(bank, offset);
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omap_reset_gpio(bank, offset);
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- spin_unlock_irqrestore(&bank->lock, flags);
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+ raw_spin_unlock_irqrestore(&bank->lock, flags);
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/*
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* If this is the last gpio to be freed in the bank,
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@@ -794,9 +794,9 @@ static unsigned int omap_gpio_irq_startu
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if (!BANK_USED(bank))
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pm_runtime_get_sync(bank->dev);
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- spin_lock_irqsave(&bank->lock, flags);
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+ raw_spin_lock_irqsave(&bank->lock, flags);
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omap_gpio_init_irq(bank, offset);
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- spin_unlock_irqrestore(&bank->lock, flags);
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+ raw_spin_unlock_irqrestore(&bank->lock, flags);
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omap_gpio_unmask_irq(d);
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return 0;
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@@ -808,11 +808,11 @@ static void omap_gpio_irq_shutdown(struc
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unsigned long flags;
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unsigned offset = d->hwirq;
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- spin_lock_irqsave(&bank->lock, flags);
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+ raw_spin_lock_irqsave(&bank->lock, flags);
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bank->irq_usage &= ~(BIT(offset));
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omap_disable_gpio_module(bank, offset);
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omap_reset_gpio(bank, offset);
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- spin_unlock_irqrestore(&bank->lock, flags);
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+ raw_spin_unlock_irqrestore(&bank->lock, flags);
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/*
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* If this is the last IRQ to be freed in the bank,
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@@ -836,10 +836,10 @@ static void omap_gpio_mask_irq(struct ir
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unsigned offset = d->hwirq;
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unsigned long flags;
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- spin_lock_irqsave(&bank->lock, flags);
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+ raw_spin_lock_irqsave(&bank->lock, flags);
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omap_set_gpio_irqenable(bank, offset, 0);
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omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
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- spin_unlock_irqrestore(&bank->lock, flags);
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+ raw_spin_unlock_irqrestore(&bank->lock, flags);
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}
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static void omap_gpio_unmask_irq(struct irq_data *d)
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@@ -849,7 +849,7 @@ static void omap_gpio_unmask_irq(struct
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u32 trigger = irqd_get_trigger_type(d);
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unsigned long flags;
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- spin_lock_irqsave(&bank->lock, flags);
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+ raw_spin_lock_irqsave(&bank->lock, flags);
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if (trigger)
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omap_set_gpio_triggering(bank, offset, trigger);
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@@ -861,7 +861,7 @@ static void omap_gpio_unmask_irq(struct
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}
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omap_set_gpio_irqenable(bank, offset, 1);
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- spin_unlock_irqrestore(&bank->lock, flags);
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+ raw_spin_unlock_irqrestore(&bank->lock, flags);
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}
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/*---------------------------------------------------------------------*/
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@@ -874,9 +874,9 @@ static int omap_mpuio_suspend_noirq(stru
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OMAP_MPUIO_GPIO_MASKIT / bank->stride;
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unsigned long flags;
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- spin_lock_irqsave(&bank->lock, flags);
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+ raw_spin_lock_irqsave(&bank->lock, flags);
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writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg);
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- spin_unlock_irqrestore(&bank->lock, flags);
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+ raw_spin_unlock_irqrestore(&bank->lock, flags);
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return 0;
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}
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@@ -889,9 +889,9 @@ static int omap_mpuio_resume_noirq(struc
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OMAP_MPUIO_GPIO_MASKIT / bank->stride;
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unsigned long flags;
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- spin_lock_irqsave(&bank->lock, flags);
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+ raw_spin_lock_irqsave(&bank->lock, flags);
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writel_relaxed(bank->context.wake_en, mask_reg);
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- spin_unlock_irqrestore(&bank->lock, flags);
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+ raw_spin_unlock_irqrestore(&bank->lock, flags);
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return 0;
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}
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@@ -937,9 +937,9 @@ static int omap_gpio_get_direction(struc
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bank = container_of(chip, struct gpio_bank, chip);
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reg = bank->base + bank->regs->direction;
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- spin_lock_irqsave(&bank->lock, flags);
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+ raw_spin_lock_irqsave(&bank->lock, flags);
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dir = !!(readl_relaxed(reg) & BIT(offset));
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- spin_unlock_irqrestore(&bank->lock, flags);
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+ raw_spin_unlock_irqrestore(&bank->lock, flags);
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return dir;
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}
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@@ -949,9 +949,9 @@ static int omap_gpio_input(struct gpio_c
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unsigned long flags;
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bank = container_of(chip, struct gpio_bank, chip);
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- spin_lock_irqsave(&bank->lock, flags);
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+ raw_spin_lock_irqsave(&bank->lock, flags);
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omap_set_gpio_direction(bank, offset, 1);
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- spin_unlock_irqrestore(&bank->lock, flags);
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+ raw_spin_unlock_irqrestore(&bank->lock, flags);
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return 0;
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}
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@@ -973,10 +973,10 @@ static int omap_gpio_output(struct gpio_
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unsigned long flags;
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bank = container_of(chip, struct gpio_bank, chip);
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- spin_lock_irqsave(&bank->lock, flags);
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+ raw_spin_lock_irqsave(&bank->lock, flags);
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bank->set_dataout(bank, offset, value);
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omap_set_gpio_direction(bank, offset, 0);
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- spin_unlock_irqrestore(&bank->lock, flags);
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+ raw_spin_unlock_irqrestore(&bank->lock, flags);
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return 0;
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}
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@@ -988,9 +988,9 @@ static int omap_gpio_debounce(struct gpi
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bank = container_of(chip, struct gpio_bank, chip);
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- spin_lock_irqsave(&bank->lock, flags);
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+ raw_spin_lock_irqsave(&bank->lock, flags);
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omap2_set_gpio_debounce(bank, offset, debounce);
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- spin_unlock_irqrestore(&bank->lock, flags);
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+ raw_spin_unlock_irqrestore(&bank->lock, flags);
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return 0;
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}
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@@ -1001,9 +1001,9 @@ static void omap_gpio_set(struct gpio_ch
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unsigned long flags;
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bank = container_of(chip, struct gpio_bank, chip);
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- spin_lock_irqsave(&bank->lock, flags);
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+ raw_spin_lock_irqsave(&bank->lock, flags);
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bank->set_dataout(bank, offset, value);
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- spin_unlock_irqrestore(&bank->lock, flags);
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+ raw_spin_unlock_irqrestore(&bank->lock, flags);
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}
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/*---------------------------------------------------------------------*/
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@@ -1199,7 +1199,7 @@ static int omap_gpio_probe(struct platfo
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else
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bank->set_dataout = omap_set_gpio_dataout_mask;
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- spin_lock_init(&bank->lock);
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+ raw_spin_lock_init(&bank->lock);
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/* Static mapping, never released */
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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@@ -1246,7 +1246,7 @@ static int omap_gpio_runtime_suspend(str
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unsigned long flags;
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u32 wake_low, wake_hi;
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- spin_lock_irqsave(&bank->lock, flags);
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+ raw_spin_lock_irqsave(&bank->lock, flags);
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/*
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* Only edges can generate a wakeup event to the PRCM.
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@@ -1299,7 +1299,7 @@ static int omap_gpio_runtime_suspend(str
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bank->get_context_loss_count(bank->dev);
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omap_gpio_dbck_disable(bank);
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- spin_unlock_irqrestore(&bank->lock, flags);
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+ raw_spin_unlock_irqrestore(&bank->lock, flags);
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return 0;
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}
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@@ -1314,7 +1314,7 @@ static int omap_gpio_runtime_resume(stru
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unsigned long flags;
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int c;
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- spin_lock_irqsave(&bank->lock, flags);
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+ raw_spin_lock_irqsave(&bank->lock, flags);
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/*
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* On the first resume during the probe, the context has not
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@@ -1350,14 +1350,14 @@ static int omap_gpio_runtime_resume(stru
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if (c != bank->context_loss_count) {
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omap_gpio_restore_context(bank);
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} else {
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- spin_unlock_irqrestore(&bank->lock, flags);
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+ raw_spin_unlock_irqrestore(&bank->lock, flags);
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return 0;
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}
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}
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}
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if (!bank->workaround_enabled) {
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- spin_unlock_irqrestore(&bank->lock, flags);
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+ raw_spin_unlock_irqrestore(&bank->lock, flags);
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return 0;
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}
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@@ -1412,7 +1412,7 @@ static int omap_gpio_runtime_resume(stru
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}
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bank->workaround_enabled = false;
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- spin_unlock_irqrestore(&bank->lock, flags);
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+ raw_spin_unlock_irqrestore(&bank->lock, flags);
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return 0;
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}
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