66 lines
1.9 KiB
Diff
66 lines
1.9 KiB
Diff
From 9c15795a4f96cb4f82a0e1503b46621251644bc2 Mon Sep 17 00:00:00 2001
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From: Emiliano Ingrassia <ingrassia@epigenesys.com>
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Date: Fri, 19 Jan 2018 02:49:17 +0100
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Subject: [PATCH 5/6] ARM: dts: meson8b-odroidc1: ethernet support
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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The Odroid-C1+ board is equipped with an RTL8211F ethernet PHY
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which supports 10/100/1000 Mbps ethernet.
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The PHY reset and interrupt lines are controlled by the SoC via
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two GPIO lines (GPIOH_4 and GPIOH_3 respectively).
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The PHY energy efficient ethernet (eee) mode is marked as broken
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using "eee-broken-1000t" because, during tests, high packet losses
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were experienced without it.
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Signed-off-by: Emiliano Ingrassia <ingrassia@epigenesys.com>
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Tested-by: Linus Lüssing <linus.luessing@c0d3.blue>
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Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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---
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arch/arm/boot/dts/meson8b-odroidc1.dts | 30 ++++++++++++++++++++++++++++++
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1 file changed, 30 insertions(+)
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diff --git a/arch/arm/boot/dts/meson8b-odroidc1.dts b/arch/arm/boot/dts/meson8b-odroidc1.dts
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index 9ff6ca4e20d0..d5e83051bb54 100644
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--- a/arch/arm/boot/dts/meson8b-odroidc1.dts
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+++ b/arch/arm/boot/dts/meson8b-odroidc1.dts
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@@ -99,3 +99,33 @@
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&usb1 {
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status = "okay";
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};
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+
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+ðmac {
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+ status = "okay";
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+
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+ snps,reset-gpio = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH>;
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+ snps,reset-active-low;
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+ snps,reset-delays-us = <0 10000 30000>;
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+
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+ pinctrl-0 = <ð_rgmii_pins>;
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+ pinctrl-names = "default";
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+
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+ phy-mode = "rgmii";
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+ phy-handle = <ð_phy>;
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+ amlogic,tx-delay-ns = <4>;
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+
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+ mdio {
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+ compatible = "snps,dwmac-mdio";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ /* Realtek RTL8211F (0x001cc916) */
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+ eth_phy: ethernet-phy@0 {
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+ reg = <0>;
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+ eee-broken-1000t;
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+ interrupt-parent = <&gpio_intc>;
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+ /* GPIOH_3 */
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+ interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
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+ };
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+ };
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+};
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--
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2.11.0
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