84 lines
2.3 KiB
Diff
84 lines
2.3 KiB
Diff
From b96446541d8390ec22e6dc579282770453ec98a4 Mon Sep 17 00:00:00 2001
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From: Emiliano Ingrassia <ingrassia@epigenesys.com>
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Date: Fri, 19 Jan 2018 02:48:00 +0100
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Subject: [PATCH 4/6] ARM: dts: meson8b: extend ethernet controller description
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Enable S805 (aka Meson8b) ethernet pin multiplexing and
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extend the controller description.
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The programmable ethernet (PRG_ETHERNET) register address
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value (0xc1108108), contained in meson.dtsi, is overridden
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according to the value found in S805 SoC manual.
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This also required to switch to "amlogic,meson8b-dwmac" compatible
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to correctly configure that register.
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The two clock sources "clkin0" and "clkin1" are both equals
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to MPLL2 because, as reported in bit 9-7 register description,
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that is the only Meson8b ethernet clock source.
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Signed-off-by: Emiliano Ingrassia <ingrassia@epigenesys.com>
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Tested-by: Linus Lüssing <linus.luessing@c0d3.blue>
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Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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---
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arch/arm/boot/dts/meson8b.dtsi | 35 +++++++++++++++++++++++++++++++++--
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1 file changed, 33 insertions(+), 2 deletions(-)
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diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
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index 4c1ac3a44357..1a7c16640ea5 100644
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--- a/arch/arm/boot/dts/meson8b.dtsi
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+++ b/arch/arm/boot/dts/meson8b.dtsi
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@@ -185,6 +185,27 @@
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl_cbus 0 0 130>;
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};
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+
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+ eth_rgmii_pins: eth-rgmii {
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+ mux {
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+ groups = "eth_tx_clk",
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+ "eth_tx_en",
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+ "eth_txd1_0",
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+ "eth_txd1_1",
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+ "eth_txd0_0",
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+ "eth_txd0_1",
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+ "eth_rx_clk",
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+ "eth_rx_dv",
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+ "eth_rxd1",
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+ "eth_rxd0",
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+ "eth_mdio_en",
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+ "eth_mdc",
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+ "eth_ref_clk",
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+ "eth_txd2",
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+ "eth_txd3";
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+ function = "ethernet";
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+ };
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+ };
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};
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};
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@@ -203,8 +224,18 @@
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};
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ðmac {
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- clocks = <&clkc CLKID_ETH>;
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- clock-names = "stmmaceth";
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+ compatible = "amlogic,meson8b-dwmac", "snps,dwmac-3.70a", "snps,dwmac";
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+
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+ reg = <0xc9410000 0x10000
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+ 0xc1108140 0x4>;
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+
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+ clocks = <&clkc CLKID_ETH>,
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+ <&clkc CLKID_MPLL2>,
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+ <&clkc CLKID_MPLL2>;
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+ clock-names = "stmmaceth", "clkin0", "clkin1";
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+
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+ resets = <&reset RESET_ETHERNET>;
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+ reset-names = "stmmaceth";
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};
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&gpio_intc {
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--
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2.11.0
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