90 lines
3.0 KiB
Diff
90 lines
3.0 KiB
Diff
From 9c6692963c4b96a40852c7ac28e8bd7d2a421821 Mon Sep 17 00:00:00 2001
|
|
From: Allen Pais <allen.pais@oracle.com>
|
|
Date: Fri, 13 Dec 2013 09:44:43 +0530
|
|
Subject: [PATCH 3/3] sparc64: convert ctx_alloc_lock raw_spinlock_t
|
|
Origin: https://www.kernel.org/pub/linux/kernel/projects/rt/3.12/patches-3.12.6-rt9.tar.xz
|
|
|
|
Signed-off-by: Allen Pais <allen.pais@oracle.com>
|
|
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
|
|
---
|
|
arch/sparc/include/asm/mmu_context_64.h | 2 +-
|
|
arch/sparc/mm/init_64.c | 10 +++++-----
|
|
arch/sparc/mm/tsb.c | 4 ++--
|
|
3 files changed, 8 insertions(+), 8 deletions(-)
|
|
|
|
--- a/arch/sparc/include/asm/mmu_context_64.h
|
|
+++ b/arch/sparc/include/asm/mmu_context_64.h
|
|
@@ -13,7 +13,7 @@ static inline void enter_lazy_tlb(struct
|
|
{
|
|
}
|
|
|
|
-extern spinlock_t ctx_alloc_lock;
|
|
+extern raw_spinlock_t ctx_alloc_lock;
|
|
extern unsigned long tlb_context_cache;
|
|
extern unsigned long mmu_context_bmap[];
|
|
|
|
--- a/arch/sparc/mm/init_64.c
|
|
+++ b/arch/sparc/mm/init_64.c
|
|
@@ -661,7 +661,7 @@ void __flush_dcache_range(unsigned long
|
|
EXPORT_SYMBOL(__flush_dcache_range);
|
|
|
|
/* get_new_mmu_context() uses "cache + 1". */
|
|
-DEFINE_SPINLOCK(ctx_alloc_lock);
|
|
+DEFINE_RAW_SPINLOCK(ctx_alloc_lock);
|
|
unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
|
|
#define MAX_CTX_NR (1UL << CTX_NR_BITS)
|
|
#define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR)
|
|
@@ -683,7 +683,7 @@ void get_new_mmu_context(struct mm_struc
|
|
unsigned long orig_pgsz_bits;
|
|
int new_version;
|
|
|
|
- spin_lock(&ctx_alloc_lock);
|
|
+ raw_spin_lock(&ctx_alloc_lock);
|
|
orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
|
|
ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
|
|
new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
|
|
@@ -719,7 +719,7 @@ void get_new_mmu_context(struct mm_struc
|
|
out:
|
|
tlb_context_cache = new_ctx;
|
|
mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
|
|
- spin_unlock(&ctx_alloc_lock);
|
|
+ raw_spin_unlock(&ctx_alloc_lock);
|
|
|
|
if (unlikely(new_version))
|
|
smp_new_mmu_context_version();
|
|
@@ -2721,7 +2721,7 @@ void hugetlb_setup(struct pt_regs *regs)
|
|
if (tlb_type == cheetah_plus) {
|
|
unsigned long ctx;
|
|
|
|
- spin_lock(&ctx_alloc_lock);
|
|
+ raw_spin_lock(&ctx_alloc_lock);
|
|
ctx = mm->context.sparc64_ctx_val;
|
|
ctx &= ~CTX_PGSZ_MASK;
|
|
ctx |= CTX_PGSZ_BASE << CTX_PGSZ0_SHIFT;
|
|
@@ -2742,7 +2742,7 @@ void hugetlb_setup(struct pt_regs *regs)
|
|
mm->context.sparc64_ctx_val = ctx;
|
|
on_each_cpu(context_reload, mm, 0);
|
|
}
|
|
- spin_unlock(&ctx_alloc_lock);
|
|
+ raw_spin_unlock(&ctx_alloc_lock);
|
|
}
|
|
}
|
|
#endif
|
|
--- a/arch/sparc/mm/tsb.c
|
|
+++ b/arch/sparc/mm/tsb.c
|
|
@@ -523,12 +523,12 @@ void destroy_context(struct mm_struct *m
|
|
free_hot_cold_page(page, 0);
|
|
}
|
|
|
|
- spin_lock_irqsave(&ctx_alloc_lock, flags);
|
|
+ raw_spin_lock_irqsave(&ctx_alloc_lock, flags);
|
|
|
|
if (CTX_VALID(mm->context)) {
|
|
unsigned long nr = CTX_NRBITS(mm->context);
|
|
mmu_context_bmap[nr>>6] &= ~(1UL << (nr & 63));
|
|
}
|
|
|
|
- spin_unlock_irqrestore(&ctx_alloc_lock, flags);
|
|
+ raw_spin_unlock_irqrestore(&ctx_alloc_lock, flags);
|
|
}
|