114 lines
4.0 KiB
Diff
114 lines
4.0 KiB
Diff
From: Eric Anholt <eric@anholt.net>
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Date: Fri, 11 Sep 2009 00:48:48 +0000 (-0700)
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Subject: agp/intel: Fix the pre-9xx chipset flush.
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X-Git-Url: http://git.kernel.org/?p=linux%2Fkernel%2Fgit%2Fanholt%2Fdrm-intel.git;a=commitdiff_plain;h=e517a5e97080bbe52857bd0d7df9b66602d53c4d;hp=8082400327d8d2ca54254b593644942bed0edd25
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agp/intel: Fix the pre-9xx chipset flush.
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Ever since we enabled GEM, the pre-9xx chipsets (particularly 865) have had
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serious stability issues. Back in May a wbinvd was added to the DRM to
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work around much of the problem. Some failure remained -- easily visible
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by dragging a window around on an X -retro desktop, or by looking at bugzilla.
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The chipset flush was on the right track -- hitting the right amount of
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memory, and it appears to be the only way to flush on these chipsets, but the
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flush page was mapped uncached. As a result, the writes trying to clear the
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writeback cache ended up bypassing the cache, and not flushing anything! The
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wbinvd would flush out other writeback data and often cause the data we wanted
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to get flushed, but not always. By removing the setting of the page to UC
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and instead just clflushing the data we write to try to flush it, we get the
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desired behavior with no wbinvd.
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This exports clflush_cache_range(), which was laying around and happened to
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basically match the code I was otherwise going to copy from the DRM.
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Signed-off-by: Eric Anholt <eric@anholt.net>
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Signed-off-by: Brice Goglin <Brice.Goglin@ens-lyon.org>
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Cc: stable@kernel.org
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---
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diff --git a/arch/x86/mm/pageattr.c b/arch/x86/mm/pageattr.c
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index 7e600c1..5866b28 100644
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--- a/arch/x86/mm/pageattr.c
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+++ b/arch/x86/mm/pageattr.c
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@@ -143,6 +143,7 @@ void clflush_cache_range(void *vaddr, unsigned int size)
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mb();
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}
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+EXPORT_SYMBOL_GPL(clflush_cache_range);
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static void __cpa_flush_all(void *arg)
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{
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diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c
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index c172917..e8dc75f 100644
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--- a/drivers/char/agp/intel-agp.c
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+++ b/drivers/char/agp/intel-agp.c
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@@ -682,23 +682,39 @@ static void intel_i830_setup_flush(void)
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if (!intel_private.i8xx_page)
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return;
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- /* make page uncached */
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- map_page_into_agp(intel_private.i8xx_page);
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-
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intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page);
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if (!intel_private.i8xx_flush_page)
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intel_i830_fini_flush();
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}
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+static void
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+do_wbinvd(void *null)
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+{
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+ wbinvd();
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+}
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+
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+/* The chipset_flush interface needs to get data that has already been
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+ * flushed out of the CPU all the way out to main memory, because the GPU
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+ * doesn't snoop those buffers.
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+ *
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+ * The 8xx series doesn't have the same lovely interface for flushing the
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+ * chipset write buffers that the later chips do. According to the 865
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+ * specs, it's 64 octwords, or 1KB. So, to get those previous things in
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+ * that buffer out, we just fill 1KB and clflush it out, on the assumption
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+ * that it'll push whatever was in there out. It appears to work.
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+ */
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static void intel_i830_chipset_flush(struct agp_bridge_data *bridge)
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{
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unsigned int *pg = intel_private.i8xx_flush_page;
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- int i;
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- for (i = 0; i < 256; i += 2)
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- *(pg + i) = i;
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+ memset(pg, 0, 1024);
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- wmb();
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+ if (cpu_has_clflush) {
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+ clflush_cache_range(pg, 1024);
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+ } else {
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+ if (on_each_cpu(do_wbinvd, NULL, 1) != 0)
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+ printk(KERN_ERR "Timed out waiting for cache flush.\n");
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+ }
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}
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/* The intel i830 automatically initializes the agp aperture during POST.
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diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
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index f3758f9..30ea4b6 100644
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--- a/drivers/gpu/drm/i915/i915_gem.c
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+++ b/drivers/gpu/drm/i915/i915_gem.c
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@@ -2511,16 +2511,6 @@ i915_gem_clflush_object(struct drm_gem_object *obj)
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if (obj_priv->pages == NULL)
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return;
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- /* XXX: The 865 in particular appears to be weird in how it handles
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- * cache flushing. We haven't figured it out, but the
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- * clflush+agp_chipset_flush doesn't appear to successfully get the
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- * data visible to the PGU, while wbinvd + agp_chipset_flush does.
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- */
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- if (IS_I865G(obj->dev)) {
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- wbinvd();
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- return;
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- }
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-
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drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
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}
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