292 lines
9.3 KiB
Diff
292 lines
9.3 KiB
Diff
From ff5b41cc7672f63ddee1bffe606f0a3b660c53fd Mon Sep 17 00:00:00 2001
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From: Frank Rowand <frank.rowand@am.sony.com>
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Date: Mon, 19 Sep 2011 14:51:14 -0700
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Subject: [PATCH 030/298] preempt-rt: Convert arm boot_lock to raw
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The arm boot_lock is used by the secondary processor startup code. The locking
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task is the idle thread, which has idle->sched_class == &idle_sched_class.
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idle_sched_class->enqueue_task == NULL, so if the idle task blocks on the
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lock, the attempt to wake it when the lock becomes available will fail:
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try_to_wake_up()
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...
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activate_task()
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enqueue_task()
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p->sched_class->enqueue_task(rq, p, flags)
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Fix by converting boot_lock to a raw spin lock.
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Signed-off-by: Frank Rowand <frank.rowand@am.sony.com>
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Link: http://lkml.kernel.org/r/4E77B952.3010606@am.sony.com
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Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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---
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arch/arm/mach-exynos/platsmp.c | 12 ++++++------
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arch/arm/mach-msm/platsmp.c | 10 +++++-----
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arch/arm/mach-omap2/omap-smp.c | 10 +++++-----
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arch/arm/mach-tegra/platsmp.c | 10 +++++-----
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arch/arm/mach-ux500/platsmp.c | 10 +++++-----
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arch/arm/plat-versatile/platsmp.c | 10 +++++-----
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6 files changed, 31 insertions(+), 31 deletions(-)
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diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
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index 69ffb2f..fe321b0 100644
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--- a/arch/arm/mach-exynos/platsmp.c
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+++ b/arch/arm/mach-exynos/platsmp.c
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@@ -63,7 +63,7 @@ static void __iomem *scu_base_addr(void)
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return (void __iomem *)(S5P_VA_SCU);
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}
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-static DEFINE_SPINLOCK(boot_lock);
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+static DEFINE_RAW_SPINLOCK(boot_lock);
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static void __cpuinit exynos4_gic_secondary_init(void)
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{
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@@ -108,8 +108,8 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
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/*
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* Synchronise with the boot thread.
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*/
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- spin_lock(&boot_lock);
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- spin_unlock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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}
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int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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@@ -120,7 +120,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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* Set synchronisation state between this boot processor
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* and the secondary one
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*/
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- spin_lock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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/*
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* The secondary processor is waiting to be released from
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@@ -149,7 +149,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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if (timeout == 0) {
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printk(KERN_ERR "cpu1 power enable failed");
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- spin_unlock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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return -ETIMEDOUT;
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}
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}
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@@ -177,7 +177,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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* now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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- spin_unlock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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return pen_release != -1 ? -ENOSYS : 0;
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}
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diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c
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index fdec58a..cad6b81 100644
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--- a/arch/arm/mach-msm/platsmp.c
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+++ b/arch/arm/mach-msm/platsmp.c
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@@ -39,7 +39,7 @@ extern void msm_secondary_startup(void);
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*/
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volatile int pen_release = -1;
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-static DEFINE_SPINLOCK(boot_lock);
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+static DEFINE_RAW_SPINLOCK(boot_lock);
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static inline int get_core_count(void)
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{
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@@ -69,8 +69,8 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
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/*
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* Synchronise with the boot thread.
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*/
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- spin_lock(&boot_lock);
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- spin_unlock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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}
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static __cpuinit void prepare_cold_cpu(unsigned int cpu)
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@@ -107,7 +107,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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* set synchronisation state between this boot processor
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* and the secondary one
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*/
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- spin_lock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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/*
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* The secondary processor is waiting to be released from
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@@ -141,7 +141,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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* now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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- spin_unlock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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return pen_release != -1 ? -ENOSYS : 0;
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}
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diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
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index 4412ddb..490de9c 100644
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--- a/arch/arm/mach-omap2/omap-smp.c
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+++ b/arch/arm/mach-omap2/omap-smp.c
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@@ -29,7 +29,7 @@
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/* SCU base address */
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static void __iomem *scu_base;
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-static DEFINE_SPINLOCK(boot_lock);
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+static DEFINE_RAW_SPINLOCK(boot_lock);
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void __cpuinit platform_secondary_init(unsigned int cpu)
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{
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@@ -43,8 +43,8 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
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/*
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* Synchronise with the boot thread.
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*/
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- spin_lock(&boot_lock);
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- spin_unlock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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}
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int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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@@ -53,7 +53,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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* Set synchronisation state between this boot processor
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* and the secondary one
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*/
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- spin_lock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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/*
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* Update the AuxCoreBoot0 with boot state for secondary core.
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@@ -70,7 +70,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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* Now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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- spin_unlock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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return 0;
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}
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diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
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index 7d2b5d0..571f61a 100644
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--- a/arch/arm/mach-tegra/platsmp.c
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+++ b/arch/arm/mach-tegra/platsmp.c
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@@ -28,7 +28,7 @@
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extern void tegra_secondary_startup(void);
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-static DEFINE_SPINLOCK(boot_lock);
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+static DEFINE_RAW_SPINLOCK(boot_lock);
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static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE);
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#define EVP_CPU_RESET_VECTOR \
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@@ -50,8 +50,8 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
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/*
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* Synchronise with the boot thread.
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*/
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- spin_lock(&boot_lock);
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- spin_unlock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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}
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int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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@@ -65,7 +65,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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* set synchronisation state between this boot processor
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* and the secondary one
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*/
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- spin_lock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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/* set the reset vector to point to the secondary_startup routine */
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@@ -101,7 +101,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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* now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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- spin_unlock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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return 0;
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}
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diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c
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index a19e398..9e92c6c 100644
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--- a/arch/arm/mach-ux500/platsmp.c
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+++ b/arch/arm/mach-ux500/platsmp.c
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@@ -57,7 +57,7 @@ static void __iomem *scu_base_addr(void)
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return NULL;
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}
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-static DEFINE_SPINLOCK(boot_lock);
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+static DEFINE_RAW_SPINLOCK(boot_lock);
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void __cpuinit platform_secondary_init(unsigned int cpu)
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{
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@@ -77,8 +77,8 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
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/*
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* Synchronise with the boot thread.
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*/
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- spin_lock(&boot_lock);
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- spin_unlock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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}
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int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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@@ -89,7 +89,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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* set synchronisation state between this boot processor
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* and the secondary one
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*/
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- spin_lock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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/*
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* The secondary processor is waiting to be released from
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@@ -110,7 +110,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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* now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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- spin_unlock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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return pen_release != -1 ? -ENOSYS : 0;
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}
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diff --git a/arch/arm/plat-versatile/platsmp.c b/arch/arm/plat-versatile/platsmp.c
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index 92f18d3..287bbb5 100644
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--- a/arch/arm/plat-versatile/platsmp.c
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+++ b/arch/arm/plat-versatile/platsmp.c
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@@ -37,7 +37,7 @@ static void __cpuinit write_pen_release(int val)
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outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
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}
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-static DEFINE_SPINLOCK(boot_lock);
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+static DEFINE_RAW_SPINLOCK(boot_lock);
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void __cpuinit platform_secondary_init(unsigned int cpu)
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{
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@@ -57,8 +57,8 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
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/*
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* Synchronise with the boot thread.
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*/
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- spin_lock(&boot_lock);
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- spin_unlock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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}
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int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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@@ -69,7 +69,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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* Set synchronisation state between this boot processor
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* and the secondary one
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*/
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- spin_lock(&boot_lock);
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+ raw_spin_lock(&boot_lock);
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/*
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* This is really belt and braces; we hold unintended secondary
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@@ -99,7 +99,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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* now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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- spin_unlock(&boot_lock);
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+ raw_spin_unlock(&boot_lock);
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return pen_release != -1 ? -ENOSYS : 0;
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}
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