327 lines
10 KiB
Diff
327 lines
10 KiB
Diff
Subject: preempt-rt: Convert arm boot_lock to raw
|
|
From: Frank Rowand <frank.rowand@am.sony.com>
|
|
Date: Mon, 19 Sep 2011 14:51:14 -0700
|
|
Origin: https://www.kernel.org/pub/linux/kernel/projects/rt/3.10/patches-3.10.4-rt1.tar.xz
|
|
|
|
|
|
The arm boot_lock is used by the secondary processor startup code. The locking
|
|
task is the idle thread, which has idle->sched_class == &idle_sched_class.
|
|
idle_sched_class->enqueue_task == NULL, so if the idle task blocks on the
|
|
lock, the attempt to wake it when the lock becomes available will fail:
|
|
|
|
try_to_wake_up()
|
|
...
|
|
activate_task()
|
|
enqueue_task()
|
|
p->sched_class->enqueue_task(rq, p, flags)
|
|
|
|
Fix by converting boot_lock to a raw spin lock.
|
|
|
|
Signed-off-by: Frank Rowand <frank.rowand@am.sony.com>
|
|
Link: http://lkml.kernel.org/r/4E77B952.3010606@am.sony.com
|
|
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
|
|
---
|
|
arch/arm/mach-exynos/platsmp.c | 12 ++++++------
|
|
arch/arm/mach-msm/platsmp.c | 10 +++++-----
|
|
arch/arm/mach-omap2/omap-smp.c | 10 +++++-----
|
|
arch/arm/mach-prima2/platsmp.c | 10 +++++-----
|
|
arch/arm/mach-spear/platsmp.c | 8 ++++----
|
|
arch/arm/mach-ux500/platsmp.c | 10 +++++-----
|
|
arch/arm/plat-versatile/platsmp.c | 10 +++++-----
|
|
7 files changed, 35 insertions(+), 35 deletions(-)
|
|
|
|
Index: linux-stable/arch/arm/mach-exynos/platsmp.c
|
|
===================================================================
|
|
--- linux-stable.orig/arch/arm/mach-exynos/platsmp.c
|
|
+++ linux-stable/arch/arm/mach-exynos/platsmp.c
|
|
@@ -71,7 +71,7 @@ static void __iomem *scu_base_addr(void)
|
|
return (void __iomem *)(S5P_VA_SCU);
|
|
}
|
|
|
|
-static DEFINE_SPINLOCK(boot_lock);
|
|
+static DEFINE_RAW_SPINLOCK(boot_lock);
|
|
|
|
static void __cpuinit exynos_secondary_init(unsigned int cpu)
|
|
{
|
|
@@ -84,8 +84,8 @@ static void __cpuinit exynos_secondary_i
|
|
/*
|
|
* Synchronise with the boot thread.
|
|
*/
|
|
- spin_lock(&boot_lock);
|
|
- spin_unlock(&boot_lock);
|
|
+ raw_spin_lock(&boot_lock);
|
|
+ raw_spin_unlock(&boot_lock);
|
|
}
|
|
|
|
static int __cpuinit exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
|
|
@@ -97,7 +97,7 @@ static int __cpuinit exynos_boot_seconda
|
|
* Set synchronisation state between this boot processor
|
|
* and the secondary one
|
|
*/
|
|
- spin_lock(&boot_lock);
|
|
+ raw_spin_lock(&boot_lock);
|
|
|
|
/*
|
|
* The secondary processor is waiting to be released from
|
|
@@ -126,7 +126,7 @@ static int __cpuinit exynos_boot_seconda
|
|
|
|
if (timeout == 0) {
|
|
printk(KERN_ERR "cpu1 power enable failed");
|
|
- spin_unlock(&boot_lock);
|
|
+ raw_spin_unlock(&boot_lock);
|
|
return -ETIMEDOUT;
|
|
}
|
|
}
|
|
@@ -165,7 +165,7 @@ static int __cpuinit exynos_boot_seconda
|
|
* now the secondary core is starting up let it run its
|
|
* calibrations, then wait for it to finish
|
|
*/
|
|
- spin_unlock(&boot_lock);
|
|
+ raw_spin_unlock(&boot_lock);
|
|
|
|
return pen_release != -1 ? -ENOSYS : 0;
|
|
}
|
|
Index: linux-stable/arch/arm/mach-msm/platsmp.c
|
|
===================================================================
|
|
--- linux-stable.orig/arch/arm/mach-msm/platsmp.c
|
|
+++ linux-stable/arch/arm/mach-msm/platsmp.c
|
|
@@ -30,7 +30,7 @@
|
|
|
|
extern void msm_secondary_startup(void);
|
|
|
|
-static DEFINE_SPINLOCK(boot_lock);
|
|
+static DEFINE_RAW_SPINLOCK(boot_lock);
|
|
|
|
static inline int get_core_count(void)
|
|
{
|
|
@@ -50,8 +50,8 @@ static void __cpuinit msm_secondary_init
|
|
/*
|
|
* Synchronise with the boot thread.
|
|
*/
|
|
- spin_lock(&boot_lock);
|
|
- spin_unlock(&boot_lock);
|
|
+ raw_spin_lock(&boot_lock);
|
|
+ raw_spin_unlock(&boot_lock);
|
|
}
|
|
|
|
static __cpuinit void prepare_cold_cpu(unsigned int cpu)
|
|
@@ -88,7 +88,7 @@ static int __cpuinit msm_boot_secondary(
|
|
* set synchronisation state between this boot processor
|
|
* and the secondary one
|
|
*/
|
|
- spin_lock(&boot_lock);
|
|
+ raw_spin_lock(&boot_lock);
|
|
|
|
/*
|
|
* The secondary processor is waiting to be released from
|
|
@@ -122,7 +122,7 @@ static int __cpuinit msm_boot_secondary(
|
|
* now the secondary core is starting up let it run its
|
|
* calibrations, then wait for it to finish
|
|
*/
|
|
- spin_unlock(&boot_lock);
|
|
+ raw_spin_unlock(&boot_lock);
|
|
|
|
return pen_release != -1 ? -ENOSYS : 0;
|
|
}
|
|
Index: linux-stable/arch/arm/mach-omap2/omap-smp.c
|
|
===================================================================
|
|
--- linux-stable.orig/arch/arm/mach-omap2/omap-smp.c
|
|
+++ linux-stable/arch/arm/mach-omap2/omap-smp.c
|
|
@@ -44,7 +44,7 @@ u16 pm44xx_errata;
|
|
/* SCU base address */
|
|
static void __iomem *scu_base;
|
|
|
|
-static DEFINE_SPINLOCK(boot_lock);
|
|
+static DEFINE_RAW_SPINLOCK(boot_lock);
|
|
|
|
void __iomem *omap4_get_scu_base(void)
|
|
{
|
|
@@ -68,8 +68,8 @@ static void __cpuinit omap4_secondary_in
|
|
/*
|
|
* Synchronise with the boot thread.
|
|
*/
|
|
- spin_lock(&boot_lock);
|
|
- spin_unlock(&boot_lock);
|
|
+ raw_spin_lock(&boot_lock);
|
|
+ raw_spin_unlock(&boot_lock);
|
|
}
|
|
|
|
static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *idle)
|
|
@@ -83,7 +83,7 @@ static int __cpuinit omap4_boot_secondar
|
|
* Set synchronisation state between this boot processor
|
|
* and the secondary one
|
|
*/
|
|
- spin_lock(&boot_lock);
|
|
+ raw_spin_lock(&boot_lock);
|
|
|
|
/*
|
|
* Update the AuxCoreBoot0 with boot state for secondary core.
|
|
@@ -160,7 +160,7 @@ static int __cpuinit omap4_boot_secondar
|
|
* Now the secondary core is starting up let it run its
|
|
* calibrations, then wait for it to finish
|
|
*/
|
|
- spin_unlock(&boot_lock);
|
|
+ raw_spin_unlock(&boot_lock);
|
|
|
|
return 0;
|
|
}
|
|
Index: linux-stable/arch/arm/mach-prima2/platsmp.c
|
|
===================================================================
|
|
--- linux-stable.orig/arch/arm/mach-prima2/platsmp.c
|
|
+++ linux-stable/arch/arm/mach-prima2/platsmp.c
|
|
@@ -23,7 +23,7 @@
|
|
static void __iomem *scu_base;
|
|
static void __iomem *rsc_base;
|
|
|
|
-static DEFINE_SPINLOCK(boot_lock);
|
|
+static DEFINE_RAW_SPINLOCK(boot_lock);
|
|
|
|
static struct map_desc scu_io_desc __initdata = {
|
|
.length = SZ_4K,
|
|
@@ -56,8 +56,8 @@ static void __cpuinit sirfsoc_secondary_
|
|
/*
|
|
* Synchronise with the boot thread.
|
|
*/
|
|
- spin_lock(&boot_lock);
|
|
- spin_unlock(&boot_lock);
|
|
+ raw_spin_lock(&boot_lock);
|
|
+ raw_spin_unlock(&boot_lock);
|
|
}
|
|
|
|
static struct of_device_id rsc_ids[] = {
|
|
@@ -95,7 +95,7 @@ static int __cpuinit sirfsoc_boot_second
|
|
/* make sure write buffer is drained */
|
|
mb();
|
|
|
|
- spin_lock(&boot_lock);
|
|
+ raw_spin_lock(&boot_lock);
|
|
|
|
/*
|
|
* The secondary processor is waiting to be released from
|
|
@@ -128,7 +128,7 @@ static int __cpuinit sirfsoc_boot_second
|
|
* now the secondary core is starting up let it run its
|
|
* calibrations, then wait for it to finish
|
|
*/
|
|
- spin_unlock(&boot_lock);
|
|
+ raw_spin_unlock(&boot_lock);
|
|
|
|
return pen_release != -1 ? -ENOSYS : 0;
|
|
}
|
|
Index: linux-stable/arch/arm/mach-spear/platsmp.c
|
|
===================================================================
|
|
--- linux-stable.orig/arch/arm/mach-spear/platsmp.c
|
|
+++ linux-stable/arch/arm/mach-spear/platsmp.c
|
|
@@ -36,8 +36,8 @@ static void __cpuinit spear13xx_secondar
|
|
/*
|
|
* Synchronise with the boot thread.
|
|
*/
|
|
- spin_lock(&boot_lock);
|
|
- spin_unlock(&boot_lock);
|
|
+ raw_spin_lock(&boot_lock);
|
|
+ raw_spin_unlock(&boot_lock);
|
|
}
|
|
|
|
static int __cpuinit spear13xx_boot_secondary(unsigned int cpu, struct task_struct *idle)
|
|
@@ -48,7 +48,7 @@ static int __cpuinit spear13xx_boot_seco
|
|
* set synchronisation state between this boot processor
|
|
* and the secondary one
|
|
*/
|
|
- spin_lock(&boot_lock);
|
|
+ raw_spin_lock(&boot_lock);
|
|
|
|
/*
|
|
* The secondary processor is waiting to be released from
|
|
@@ -75,7 +75,7 @@ static int __cpuinit spear13xx_boot_seco
|
|
* now the secondary core is starting up let it run its
|
|
* calibrations, then wait for it to finish
|
|
*/
|
|
- spin_unlock(&boot_lock);
|
|
+ raw_spin_unlock(&boot_lock);
|
|
|
|
return pen_release != -1 ? -ENOSYS : 0;
|
|
}
|
|
Index: linux-stable/arch/arm/mach-ux500/platsmp.c
|
|
===================================================================
|
|
--- linux-stable.orig/arch/arm/mach-ux500/platsmp.c
|
|
+++ linux-stable/arch/arm/mach-ux500/platsmp.c
|
|
@@ -52,7 +52,7 @@ static void __iomem *scu_base_addr(void)
|
|
return NULL;
|
|
}
|
|
|
|
-static DEFINE_SPINLOCK(boot_lock);
|
|
+static DEFINE_RAW_SPINLOCK(boot_lock);
|
|
|
|
static void __cpuinit ux500_secondary_init(unsigned int cpu)
|
|
{
|
|
@@ -65,8 +65,8 @@ static void __cpuinit ux500_secondary_in
|
|
/*
|
|
* Synchronise with the boot thread.
|
|
*/
|
|
- spin_lock(&boot_lock);
|
|
- spin_unlock(&boot_lock);
|
|
+ raw_spin_lock(&boot_lock);
|
|
+ raw_spin_unlock(&boot_lock);
|
|
}
|
|
|
|
static int __cpuinit ux500_boot_secondary(unsigned int cpu, struct task_struct *idle)
|
|
@@ -77,7 +77,7 @@ static int __cpuinit ux500_boot_secondar
|
|
* set synchronisation state between this boot processor
|
|
* and the secondary one
|
|
*/
|
|
- spin_lock(&boot_lock);
|
|
+ raw_spin_lock(&boot_lock);
|
|
|
|
/*
|
|
* The secondary processor is waiting to be released from
|
|
@@ -98,7 +98,7 @@ static int __cpuinit ux500_boot_secondar
|
|
* now the secondary core is starting up let it run its
|
|
* calibrations, then wait for it to finish
|
|
*/
|
|
- spin_unlock(&boot_lock);
|
|
+ raw_spin_unlock(&boot_lock);
|
|
|
|
return pen_release != -1 ? -ENOSYS : 0;
|
|
}
|
|
Index: linux-stable/arch/arm/plat-versatile/platsmp.c
|
|
===================================================================
|
|
--- linux-stable.orig/arch/arm/plat-versatile/platsmp.c
|
|
+++ linux-stable/arch/arm/plat-versatile/platsmp.c
|
|
@@ -31,7 +31,7 @@ static void __cpuinit write_pen_release(
|
|
outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
|
|
}
|
|
|
|
-static DEFINE_SPINLOCK(boot_lock);
|
|
+static DEFINE_RAW_SPINLOCK(boot_lock);
|
|
|
|
void __cpuinit versatile_secondary_init(unsigned int cpu)
|
|
{
|
|
@@ -44,8 +44,8 @@ void __cpuinit versatile_secondary_init(
|
|
/*
|
|
* Synchronise with the boot thread.
|
|
*/
|
|
- spin_lock(&boot_lock);
|
|
- spin_unlock(&boot_lock);
|
|
+ raw_spin_lock(&boot_lock);
|
|
+ raw_spin_unlock(&boot_lock);
|
|
}
|
|
|
|
int __cpuinit versatile_boot_secondary(unsigned int cpu, struct task_struct *idle)
|
|
@@ -56,7 +56,7 @@ int __cpuinit versatile_boot_secondary(u
|
|
* Set synchronisation state between this boot processor
|
|
* and the secondary one
|
|
*/
|
|
- spin_lock(&boot_lock);
|
|
+ raw_spin_lock(&boot_lock);
|
|
|
|
/*
|
|
* This is really belt and braces; we hold unintended secondary
|
|
@@ -86,7 +86,7 @@ int __cpuinit versatile_boot_secondary(u
|
|
* now the secondary core is starting up let it run its
|
|
* calibrations, then wait for it to finish
|
|
*/
|
|
- spin_unlock(&boot_lock);
|
|
+ raw_spin_unlock(&boot_lock);
|
|
|
|
return pen_release != -1 ? -ENOSYS : 0;
|
|
}
|