81 lines
3.1 KiB
Diff
81 lines
3.1 KiB
Diff
From: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
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Date: Wed, 23 Oct 2019 10:45:50 +0200
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Subject: x86/msr: Add the IA32_TSX_CTRL MSR
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commit c2955f270a84762343000f103e0640d29c7a96f3 upstream.
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Transactional Synchronization Extensions (TSX) may be used on certain
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processors as part of a speculative side channel attack. A microcode
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update for existing processors that are vulnerable to this attack will
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add a new MSR - IA32_TSX_CTRL to allow the system administrator the
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option to disable TSX as one of the possible mitigations.
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The CPUs which get this new MSR after a microcode upgrade are the ones
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which do not set MSR_IA32_ARCH_CAPABILITIES.MDS_NO (bit 5) because those
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CPUs have CPUID.MD_CLEAR, i.e., the VERW implementation which clears all
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CPU buffers takes care of the TAA case as well.
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[ Note that future processors that are not vulnerable will also
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support the IA32_TSX_CTRL MSR. ]
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Add defines for the new IA32_TSX_CTRL MSR and its bits.
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TSX has two sub-features:
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1. Restricted Transactional Memory (RTM) is an explicitly-used feature
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where new instructions begin and end TSX transactions.
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2. Hardware Lock Elision (HLE) is implicitly used when certain kinds of
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"old" style locks are used by software.
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Bit 7 of the IA32_ARCH_CAPABILITIES indicates the presence of the
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IA32_TSX_CTRL MSR.
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There are two control bits in IA32_TSX_CTRL MSR:
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Bit 0: When set, it disables the Restricted Transactional Memory (RTM)
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sub-feature of TSX (will force all transactions to abort on the
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XBEGIN instruction).
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Bit 1: When set, it disables the enumeration of the RTM and HLE feature
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(i.e. it will make CPUID(EAX=7).EBX{bit4} and
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CPUID(EAX=7).EBX{bit11} read as 0).
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The other TSX sub-feature, Hardware Lock Elision (HLE), is
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unconditionally disabled by the new microcode but still enumerated
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as present by CPUID(EAX=7).EBX{bit4}, unless disabled by
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IA32_TSX_CTRL_MSR[1] - TSX_CTRL_CPUID_CLEAR.
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Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
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Signed-off-by: Borislav Petkov <bp@suse.de>
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Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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Tested-by: Neelima Krishnan <neelima.krishnan@intel.com>
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Reviewed-by: Mark Gross <mgross@linux.intel.com>
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Reviewed-by: Tony Luck <tony.luck@intel.com>
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Reviewed-by: Josh Poimboeuf <jpoimboe@redhat.com>
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Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
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---
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arch/x86/include/asm/msr-index.h | 5 +++++
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1 file changed, 5 insertions(+)
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--- a/arch/x86/include/asm/msr-index.h
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+++ b/arch/x86/include/asm/msr-index.h
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@@ -84,6 +84,7 @@
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* Microarchitectural Data
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* Sampling (MDS) vulnerabilities.
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*/
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+#define ARCH_CAP_TSX_CTRL_MSR BIT(7) /* MSR for TSX control is available. */
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#define MSR_IA32_FLUSH_CMD 0x0000010b
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#define L1D_FLUSH BIT(0) /*
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@@ -94,6 +95,10 @@
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#define MSR_IA32_BBL_CR_CTL 0x00000119
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#define MSR_IA32_BBL_CR_CTL3 0x0000011e
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+#define MSR_IA32_TSX_CTRL 0x00000122
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+#define TSX_CTRL_RTM_DISABLE BIT(0) /* Disable RTM feature */
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+#define TSX_CTRL_CPUID_CLEAR BIT(1) /* Disable TSX enumeration */
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+
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#define MSR_IA32_SYSENTER_CS 0x00000174
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#define MSR_IA32_SYSENTER_ESP 0x00000175
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#define MSR_IA32_SYSENTER_EIP 0x00000176
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