793 lines
30 KiB
Diff
793 lines
30 KiB
Diff
From: Ben Hutchings <ben@decadent.org.uk>
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Date: Wed, 14 Mar 2018 00:48:34 +0000
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Subject: Revert "x86/cpu: Rename cpu_data.x86_mask to cpu_data.x86_stepping"
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Forwarded: not-needed
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This reverts commit 7d6446416778e695ddba589a25aa2dabcaba5d2d, which
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was commit b399151cb48db30ad1e0e93dd40d68c6d007b637 upstream. This
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is an unnecessary ABI change.
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---
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arch/x86/events/intel/core.c | 2 +-
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arch/x86/events/intel/lbr.c | 2 +-
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arch/x86/events/intel/p6.c | 2 +-
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arch/x86/include/asm/acpi.h | 2 +-
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arch/x86/include/asm/processor.h | 2 +-
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arch/x86/kernel/amd_nb.c | 2 +-
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arch/x86/kernel/apic/apic.c | 6 +++---
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arch/x86/kernel/asm-offsets_32.c | 2 +-
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arch/x86/kernel/cpu/amd.c | 28 ++++++++++++++--------------
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arch/x86/kernel/cpu/centaur.c | 4 ++--
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arch/x86/kernel/cpu/common.c | 8 ++++----
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arch/x86/kernel/cpu/cyrix.c | 2 +-
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arch/x86/kernel/cpu/intel.c | 18 +++++++++---------
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arch/x86/kernel/cpu/intel_rdt.c | 2 +-
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arch/x86/kernel/cpu/microcode/intel.c | 4 ++--
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arch/x86/kernel/cpu/mtrr/generic.c | 2 +-
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arch/x86/kernel/cpu/mtrr/main.c | 4 ++--
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arch/x86/kernel/cpu/proc.c | 4 ++--
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arch/x86/kernel/head_32.S | 4 ++--
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arch/x86/kernel/mpparse.c | 2 +-
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arch/x86/lib/cpu.c | 2 +-
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drivers/char/hw_random/via-rng.c | 2 +-
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drivers/cpufreq/acpi-cpufreq.c | 2 +-
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drivers/cpufreq/longhaul.c | 6 +++---
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drivers/cpufreq/p4-clockmod.c | 2 +-
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drivers/cpufreq/powernow-k7.c | 2 +-
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drivers/cpufreq/speedstep-centrino.c | 4 ++--
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drivers/cpufreq/speedstep-lib.c | 6 +++---
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drivers/crypto/padlock-aes.c | 2 +-
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drivers/edac/amd64_edac.c | 2 +-
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drivers/hwmon/coretemp.c | 6 +++---
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drivers/hwmon/hwmon-vid.c | 2 +-
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drivers/hwmon/k10temp.c | 2 +-
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drivers/hwmon/k8temp.c | 2 +-
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drivers/video/fbdev/geode/video_gx.c | 2 +-
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35 files changed, 73 insertions(+), 73 deletions(-)
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diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
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index 56457cb73448..731153a4681e 100644
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--- a/arch/x86/events/intel/core.c
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+++ b/arch/x86/events/intel/core.c
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@@ -3559,7 +3559,7 @@ static int intel_snb_pebs_broken(int cpu)
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break;
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case INTEL_FAM6_SANDYBRIDGE_X:
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- switch (cpu_data(cpu).x86_stepping) {
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+ switch (cpu_data(cpu).x86_mask) {
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case 6: rev = 0x618; break;
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case 7: rev = 0x70c; break;
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}
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diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c
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index cf372b90557e..ae64d0b69729 100644
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--- a/arch/x86/events/intel/lbr.c
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+++ b/arch/x86/events/intel/lbr.c
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@@ -1186,7 +1186,7 @@ void __init intel_pmu_lbr_init_atom(void)
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* on PMU interrupt
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*/
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if (boot_cpu_data.x86_model == 28
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- && boot_cpu_data.x86_stepping < 10) {
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+ && boot_cpu_data.x86_mask < 10) {
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pr_cont("LBR disabled due to erratum");
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return;
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}
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diff --git a/arch/x86/events/intel/p6.c b/arch/x86/events/intel/p6.c
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index 408879b0c0d4..a5604c352930 100644
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--- a/arch/x86/events/intel/p6.c
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+++ b/arch/x86/events/intel/p6.c
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@@ -234,7 +234,7 @@ static __initconst const struct x86_pmu p6_pmu = {
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static __init void p6_pmu_rdpmc_quirk(void)
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{
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- if (boot_cpu_data.x86_stepping < 9) {
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+ if (boot_cpu_data.x86_mask < 9) {
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/*
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* PPro erratum 26; fixed in stepping 9 and above.
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*/
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diff --git a/arch/x86/include/asm/acpi.h b/arch/x86/include/asm/acpi.h
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index f077401869ee..8d0ec9df1cbe 100644
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--- a/arch/x86/include/asm/acpi.h
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+++ b/arch/x86/include/asm/acpi.h
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@@ -94,7 +94,7 @@ static inline unsigned int acpi_processor_cstate_check(unsigned int max_cstate)
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if (boot_cpu_data.x86 == 0x0F &&
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boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
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boot_cpu_data.x86_model <= 0x05 &&
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- boot_cpu_data.x86_stepping < 0x0A)
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+ boot_cpu_data.x86_mask < 0x0A)
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return 1;
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else if (boot_cpu_has(X86_BUG_AMD_APIC_C1E))
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return 1;
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diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
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index 44c2c4ec6d60..bf787ee25466 100644
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--- a/arch/x86/include/asm/processor.h
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+++ b/arch/x86/include/asm/processor.h
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@@ -91,7 +91,7 @@ struct cpuinfo_x86 {
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__u8 x86; /* CPU family */
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__u8 x86_vendor; /* CPU vendor */
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__u8 x86_model;
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- __u8 x86_stepping;
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+ __u8 x86_mask;
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#ifdef CONFIG_X86_64
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/* Number of 4K pages in DTLB/ITLB combined(in pages): */
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int x86_tlbsize;
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diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
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index c88e0b127810..6db28f17ff28 100644
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--- a/arch/x86/kernel/amd_nb.c
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+++ b/arch/x86/kernel/amd_nb.c
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@@ -235,7 +235,7 @@ int amd_cache_northbridges(void)
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if (boot_cpu_data.x86 == 0x10 &&
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boot_cpu_data.x86_model >= 0x8 &&
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(boot_cpu_data.x86_model > 0x9 ||
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- boot_cpu_data.x86_stepping >= 0x1))
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+ boot_cpu_data.x86_mask >= 0x1))
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amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE;
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if (boot_cpu_data.x86 == 0x15)
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diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
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index b203af0855b5..25ddf02598d2 100644
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--- a/arch/x86/kernel/apic/apic.c
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+++ b/arch/x86/kernel/apic/apic.c
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@@ -546,7 +546,7 @@ static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
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static u32 hsx_deadline_rev(void)
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{
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- switch (boot_cpu_data.x86_stepping) {
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+ switch (boot_cpu_data.x86_mask) {
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case 0x02: return 0x3a; /* EP */
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case 0x04: return 0x0f; /* EX */
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}
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@@ -556,7 +556,7 @@ static u32 hsx_deadline_rev(void)
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static u32 bdx_deadline_rev(void)
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{
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- switch (boot_cpu_data.x86_stepping) {
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+ switch (boot_cpu_data.x86_mask) {
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case 0x02: return 0x00000011;
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case 0x03: return 0x0700000e;
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case 0x04: return 0x0f00000c;
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@@ -568,7 +568,7 @@ static u32 bdx_deadline_rev(void)
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static u32 skx_deadline_rev(void)
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{
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- switch (boot_cpu_data.x86_stepping) {
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+ switch (boot_cpu_data.x86_mask) {
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case 0x03: return 0x01000136;
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case 0x04: return 0x02000014;
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}
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diff --git a/arch/x86/kernel/asm-offsets_32.c b/arch/x86/kernel/asm-offsets_32.c
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index f91ba53e06c8..fa1261eefa16 100644
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--- a/arch/x86/kernel/asm-offsets_32.c
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+++ b/arch/x86/kernel/asm-offsets_32.c
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@@ -18,7 +18,7 @@ void foo(void)
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OFFSET(CPUINFO_x86, cpuinfo_x86, x86);
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OFFSET(CPUINFO_x86_vendor, cpuinfo_x86, x86_vendor);
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OFFSET(CPUINFO_x86_model, cpuinfo_x86, x86_model);
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- OFFSET(CPUINFO_x86_stepping, cpuinfo_x86, x86_stepping);
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+ OFFSET(CPUINFO_x86_mask, cpuinfo_x86, x86_mask);
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OFFSET(CPUINFO_cpuid_level, cpuinfo_x86, cpuid_level);
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OFFSET(CPUINFO_x86_capability, cpuinfo_x86, x86_capability);
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OFFSET(CPUINFO_x86_vendor_id, cpuinfo_x86, x86_vendor_id);
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diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
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index e7d5a7883632..ea831c858195 100644
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--- a/arch/x86/kernel/cpu/amd.c
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+++ b/arch/x86/kernel/cpu/amd.c
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@@ -119,7 +119,7 @@ static void init_amd_k6(struct cpuinfo_x86 *c)
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return;
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}
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- if (c->x86_model == 6 && c->x86_stepping == 1) {
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+ if (c->x86_model == 6 && c->x86_mask == 1) {
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const int K6_BUG_LOOP = 1000000;
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int n;
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void (*f_vide)(void);
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@@ -149,7 +149,7 @@ static void init_amd_k6(struct cpuinfo_x86 *c)
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/* K6 with old style WHCR */
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if (c->x86_model < 8 ||
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- (c->x86_model == 8 && c->x86_stepping < 8)) {
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+ (c->x86_model == 8 && c->x86_mask < 8)) {
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/* We can only write allocate on the low 508Mb */
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if (mbytes > 508)
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mbytes = 508;
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@@ -168,7 +168,7 @@ static void init_amd_k6(struct cpuinfo_x86 *c)
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return;
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}
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- if ((c->x86_model == 8 && c->x86_stepping > 7) ||
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+ if ((c->x86_model == 8 && c->x86_mask > 7) ||
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c->x86_model == 9 || c->x86_model == 13) {
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/* The more serious chips .. */
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@@ -221,7 +221,7 @@ static void init_amd_k7(struct cpuinfo_x86 *c)
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* are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
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* As per AMD technical note 27212 0.2
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*/
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- if ((c->x86_model == 8 && c->x86_stepping >= 1) || (c->x86_model > 8)) {
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+ if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) {
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rdmsr(MSR_K7_CLK_CTL, l, h);
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if ((l & 0xfff00000) != 0x20000000) {
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pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n",
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@@ -241,12 +241,12 @@ static void init_amd_k7(struct cpuinfo_x86 *c)
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* but they are not certified as MP capable.
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*/
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/* Athlon 660/661 is valid. */
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- if ((c->x86_model == 6) && ((c->x86_stepping == 0) ||
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- (c->x86_stepping == 1)))
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+ if ((c->x86_model == 6) && ((c->x86_mask == 0) ||
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+ (c->x86_mask == 1)))
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return;
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/* Duron 670 is valid */
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- if ((c->x86_model == 7) && (c->x86_stepping == 0))
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+ if ((c->x86_model == 7) && (c->x86_mask == 0))
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return;
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/*
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@@ -256,8 +256,8 @@ static void init_amd_k7(struct cpuinfo_x86 *c)
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* See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
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* more.
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*/
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- if (((c->x86_model == 6) && (c->x86_stepping >= 2)) ||
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- ((c->x86_model == 7) && (c->x86_stepping >= 1)) ||
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+ if (((c->x86_model == 6) && (c->x86_mask >= 2)) ||
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+ ((c->x86_model == 7) && (c->x86_mask >= 1)) ||
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(c->x86_model > 7))
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if (cpu_has(c, X86_FEATURE_MP))
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return;
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@@ -583,7 +583,7 @@ static void early_init_amd(struct cpuinfo_x86 *c)
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/* Set MTRR capability flag if appropriate */
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if (c->x86 == 5)
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if (c->x86_model == 13 || c->x86_model == 9 ||
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- (c->x86_model == 8 && c->x86_stepping >= 8))
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+ (c->x86_model == 8 && c->x86_mask >= 8))
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set_cpu_cap(c, X86_FEATURE_K6_MTRR);
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#endif
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#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI)
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@@ -769,7 +769,7 @@ static void init_amd_zn(struct cpuinfo_x86 *c)
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* Fix erratum 1076: CPB feature bit not being set in CPUID. It affects
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* all up to and including B1.
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*/
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- if (c->x86_model <= 1 && c->x86_stepping <= 1)
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+ if (c->x86_model <= 1 && c->x86_mask <= 1)
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set_cpu_cap(c, X86_FEATURE_CPB);
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}
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@@ -880,11 +880,11 @@ static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
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/* AMD errata T13 (order #21922) */
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if ((c->x86 == 6)) {
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/* Duron Rev A0 */
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- if (c->x86_model == 3 && c->x86_stepping == 0)
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+ if (c->x86_model == 3 && c->x86_mask == 0)
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size = 64;
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/* Tbird rev A1/A2 */
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if (c->x86_model == 4 &&
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- (c->x86_stepping == 0 || c->x86_stepping == 1))
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+ (c->x86_mask == 0 || c->x86_mask == 1))
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size = 256;
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}
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return size;
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@@ -1021,7 +1021,7 @@ static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
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}
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/* OSVW unavailable or ID unknown, match family-model-stepping range */
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- ms = (cpu->x86_model << 4) | cpu->x86_stepping;
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+ ms = (cpu->x86_model << 4) | cpu->x86_mask;
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while ((range = *erratum++))
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if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
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(ms >= AMD_MODEL_RANGE_START(range)) &&
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diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c
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index 595be776727d..68bc6d9b3132 100644
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--- a/arch/x86/kernel/cpu/centaur.c
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+++ b/arch/x86/kernel/cpu/centaur.c
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@@ -136,7 +136,7 @@ static void init_centaur(struct cpuinfo_x86 *c)
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clear_cpu_cap(c, X86_FEATURE_TSC);
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break;
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case 8:
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- switch (c->x86_stepping) {
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+ switch (c->x86_mask) {
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default:
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name = "2";
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break;
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@@ -211,7 +211,7 @@ centaur_size_cache(struct cpuinfo_x86 *c, unsigned int size)
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* - Note, it seems this may only be in engineering samples.
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*/
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if ((c->x86 == 6) && (c->x86_model == 9) &&
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- (c->x86_stepping == 1) && (size == 65))
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+ (c->x86_mask == 1) && (size == 65))
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size -= 1;
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return size;
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}
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diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
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index 824aee0117bb..a37fd008d24b 100644
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--- a/arch/x86/kernel/cpu/common.c
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+++ b/arch/x86/kernel/cpu/common.c
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@@ -731,7 +731,7 @@ void cpu_detect(struct cpuinfo_x86 *c)
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cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
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c->x86 = x86_family(tfms);
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c->x86_model = x86_model(tfms);
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- c->x86_stepping = x86_stepping(tfms);
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+ c->x86_mask = x86_stepping(tfms);
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if (cap0 & (1<<19)) {
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c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
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@@ -1186,7 +1186,7 @@ static void identify_cpu(struct cpuinfo_x86 *c)
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c->loops_per_jiffy = loops_per_jiffy;
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c->x86_cache_size = 0;
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c->x86_vendor = X86_VENDOR_UNKNOWN;
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- c->x86_model = c->x86_stepping = 0; /* So far unknown... */
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+ c->x86_model = c->x86_mask = 0; /* So far unknown... */
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c->x86_vendor_id[0] = '\0'; /* Unset */
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c->x86_model_id[0] = '\0'; /* Unset */
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c->x86_max_cores = 1;
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@@ -1378,8 +1378,8 @@ void print_cpu_info(struct cpuinfo_x86 *c)
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pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model);
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- if (c->x86_stepping || c->cpuid_level >= 0)
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- pr_cont(", stepping: 0x%x)\n", c->x86_stepping);
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+ if (c->x86_mask || c->cpuid_level >= 0)
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+ pr_cont(", stepping: 0x%x)\n", c->x86_mask);
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else
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pr_cont(")\n");
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}
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diff --git a/arch/x86/kernel/cpu/cyrix.c b/arch/x86/kernel/cpu/cyrix.c
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index 8949b7ae6d92..6b4bb335641f 100644
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--- a/arch/x86/kernel/cpu/cyrix.c
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+++ b/arch/x86/kernel/cpu/cyrix.c
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@@ -215,7 +215,7 @@ static void init_cyrix(struct cpuinfo_x86 *c)
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/* common case step number/rev -- exceptions handled below */
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c->x86_model = (dir1 >> 4) + 1;
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- c->x86_stepping = dir1 & 0xf;
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+ c->x86_mask = dir1 & 0xf;
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/* Now cook; the original recipe is by Channing Corn, from Cyrix.
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* We do the same thing for each generation: we work out
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diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
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index d19e903214b4..ef796f14f7ae 100644
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--- a/arch/x86/kernel/cpu/intel.c
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+++ b/arch/x86/kernel/cpu/intel.c
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@@ -146,7 +146,7 @@ static bool bad_spectre_microcode(struct cpuinfo_x86 *c)
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for (i = 0; i < ARRAY_SIZE(spectre_bad_microcodes); i++) {
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if (c->x86_model == spectre_bad_microcodes[i].model &&
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- c->x86_stepping == spectre_bad_microcodes[i].stepping)
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+ c->x86_mask == spectre_bad_microcodes[i].stepping)
|
|
return (c->microcode <= spectre_bad_microcodes[i].microcode);
|
|
}
|
|
return false;
|
|
@@ -193,7 +193,7 @@ static void early_init_intel(struct cpuinfo_x86 *c)
|
|
* need the microcode to have already been loaded... so if it is
|
|
* not, recommend a BIOS update and disable large pages.
|
|
*/
|
|
- if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_stepping <= 2 &&
|
|
+ if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2 &&
|
|
c->microcode < 0x20e) {
|
|
pr_warn("Atom PSE erratum detected, BIOS microcode update recommended\n");
|
|
clear_cpu_cap(c, X86_FEATURE_PSE);
|
|
@@ -209,7 +209,7 @@ static void early_init_intel(struct cpuinfo_x86 *c)
|
|
|
|
/* CPUID workaround for 0F33/0F34 CPU */
|
|
if (c->x86 == 0xF && c->x86_model == 0x3
|
|
- && (c->x86_stepping == 0x3 || c->x86_stepping == 0x4))
|
|
+ && (c->x86_mask == 0x3 || c->x86_mask == 0x4))
|
|
c->x86_phys_bits = 36;
|
|
|
|
/*
|
|
@@ -307,7 +307,7 @@ int ppro_with_ram_bug(void)
|
|
if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
|
|
boot_cpu_data.x86 == 6 &&
|
|
boot_cpu_data.x86_model == 1 &&
|
|
- boot_cpu_data.x86_stepping < 8) {
|
|
+ boot_cpu_data.x86_mask < 8) {
|
|
pr_info("Pentium Pro with Errata#50 detected. Taking evasive action.\n");
|
|
return 1;
|
|
}
|
|
@@ -324,7 +324,7 @@ static void intel_smp_check(struct cpuinfo_x86 *c)
|
|
* Mask B, Pentium, but not Pentium MMX
|
|
*/
|
|
if (c->x86 == 5 &&
|
|
- c->x86_stepping >= 1 && c->x86_stepping <= 4 &&
|
|
+ c->x86_mask >= 1 && c->x86_mask <= 4 &&
|
|
c->x86_model <= 3) {
|
|
/*
|
|
* Remember we have B step Pentia with bugs
|
|
@@ -367,7 +367,7 @@ static void intel_workarounds(struct cpuinfo_x86 *c)
|
|
* SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
|
|
* model 3 mask 3
|
|
*/
|
|
- if ((c->x86<<8 | c->x86_model<<4 | c->x86_stepping) < 0x633)
|
|
+ if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
|
|
clear_cpu_cap(c, X86_FEATURE_SEP);
|
|
|
|
/*
|
|
@@ -385,7 +385,7 @@ static void intel_workarounds(struct cpuinfo_x86 *c)
|
|
* P4 Xeon erratum 037 workaround.
|
|
* Hardware prefetcher may cause stale data to be loaded into the cache.
|
|
*/
|
|
- if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_stepping == 1)) {
|
|
+ if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
|
|
if (msr_set_bit(MSR_IA32_MISC_ENABLE,
|
|
MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) {
|
|
pr_info("CPU: C0 stepping P4 Xeon detected.\n");
|
|
@@ -400,7 +400,7 @@ static void intel_workarounds(struct cpuinfo_x86 *c)
|
|
* Specification Update").
|
|
*/
|
|
if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
|
|
- (c->x86_stepping < 0x6 || c->x86_stepping == 0xb))
|
|
+ (c->x86_mask < 0x6 || c->x86_mask == 0xb))
|
|
set_cpu_bug(c, X86_BUG_11AP);
|
|
|
|
|
|
@@ -647,7 +647,7 @@ static void init_intel(struct cpuinfo_x86 *c)
|
|
case 6:
|
|
if (l2 == 128)
|
|
p = "Celeron (Mendocino)";
|
|
- else if (c->x86_stepping == 0 || c->x86_stepping == 5)
|
|
+ else if (c->x86_mask == 0 || c->x86_mask == 5)
|
|
p = "Celeron-A";
|
|
break;
|
|
|
|
diff --git a/arch/x86/kernel/cpu/intel_rdt.c b/arch/x86/kernel/cpu/intel_rdt.c
|
|
index 18dd8f22e353..99442370de40 100644
|
|
--- a/arch/x86/kernel/cpu/intel_rdt.c
|
|
+++ b/arch/x86/kernel/cpu/intel_rdt.c
|
|
@@ -771,7 +771,7 @@ static __init void rdt_quirks(void)
|
|
cache_alloc_hsw_probe();
|
|
break;
|
|
case INTEL_FAM6_SKYLAKE_X:
|
|
- if (boot_cpu_data.x86_stepping <= 4)
|
|
+ if (boot_cpu_data.x86_mask <= 4)
|
|
set_rdt_options("!cmt,!mbmtotal,!mbmlocal,!l3cat");
|
|
}
|
|
}
|
|
diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c
|
|
index a15db2b4e0d6..e5edb92c9172 100644
|
|
--- a/arch/x86/kernel/cpu/microcode/intel.c
|
|
+++ b/arch/x86/kernel/cpu/microcode/intel.c
|
|
@@ -921,7 +921,7 @@ static bool is_blacklisted(unsigned int cpu)
|
|
*/
|
|
if (c->x86 == 6 &&
|
|
c->x86_model == INTEL_FAM6_BROADWELL_X &&
|
|
- c->x86_stepping == 0x01 &&
|
|
+ c->x86_mask == 0x01 &&
|
|
llc_size_per_core > 2621440 &&
|
|
c->microcode < 0x0b000021) {
|
|
pr_err_once("Erratum BDF90: late loading with revision < 0x0b000021 (0x%x) disabled.\n", c->microcode);
|
|
@@ -944,7 +944,7 @@ static enum ucode_state request_microcode_fw(int cpu, struct device *device,
|
|
return UCODE_NFOUND;
|
|
|
|
sprintf(name, "intel-ucode/%02x-%02x-%02x",
|
|
- c->x86, c->x86_model, c->x86_stepping);
|
|
+ c->x86, c->x86_model, c->x86_mask);
|
|
|
|
if (request_firmware_direct(&firmware, name, device)) {
|
|
pr_debug("data file %s load failed\n", name);
|
|
diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/generic.c
|
|
index e12ee86906c6..fdc55215d44d 100644
|
|
--- a/arch/x86/kernel/cpu/mtrr/generic.c
|
|
+++ b/arch/x86/kernel/cpu/mtrr/generic.c
|
|
@@ -859,7 +859,7 @@ int generic_validate_add_page(unsigned long base, unsigned long size,
|
|
*/
|
|
if (is_cpu(INTEL) && boot_cpu_data.x86 == 6 &&
|
|
boot_cpu_data.x86_model == 1 &&
|
|
- boot_cpu_data.x86_stepping <= 7) {
|
|
+ boot_cpu_data.x86_mask <= 7) {
|
|
if (base & ((1 << (22 - PAGE_SHIFT)) - 1)) {
|
|
pr_warn("mtrr: base(0x%lx000) is not 4 MiB aligned\n", base);
|
|
return -EINVAL;
|
|
diff --git a/arch/x86/kernel/cpu/mtrr/main.c b/arch/x86/kernel/cpu/mtrr/main.c
|
|
index 7468de429087..40d5a8a75212 100644
|
|
--- a/arch/x86/kernel/cpu/mtrr/main.c
|
|
+++ b/arch/x86/kernel/cpu/mtrr/main.c
|
|
@@ -711,8 +711,8 @@ void __init mtrr_bp_init(void)
|
|
if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
|
|
boot_cpu_data.x86 == 0xF &&
|
|
boot_cpu_data.x86_model == 0x3 &&
|
|
- (boot_cpu_data.x86_stepping == 0x3 ||
|
|
- boot_cpu_data.x86_stepping == 0x4))
|
|
+ (boot_cpu_data.x86_mask == 0x3 ||
|
|
+ boot_cpu_data.x86_mask == 0x4))
|
|
phys_addr = 36;
|
|
|
|
size_or_mask = SIZE_OR_MASK_BITS(phys_addr);
|
|
diff --git a/arch/x86/kernel/cpu/proc.c b/arch/x86/kernel/cpu/proc.c
|
|
index 2c8522a39ed5..f3da3bb1e29e 100644
|
|
--- a/arch/x86/kernel/cpu/proc.c
|
|
+++ b/arch/x86/kernel/cpu/proc.c
|
|
@@ -72,8 +72,8 @@ static int show_cpuinfo(struct seq_file *m, void *v)
|
|
c->x86_model,
|
|
c->x86_model_id[0] ? c->x86_model_id : "unknown");
|
|
|
|
- if (c->x86_stepping || c->cpuid_level >= 0)
|
|
- seq_printf(m, "stepping\t: %d\n", c->x86_stepping);
|
|
+ if (c->x86_mask || c->cpuid_level >= 0)
|
|
+ seq_printf(m, "stepping\t: %d\n", c->x86_mask);
|
|
else
|
|
seq_puts(m, "stepping\t: unknown\n");
|
|
if (c->microcode)
|
|
diff --git a/arch/x86/kernel/head_32.S b/arch/x86/kernel/head_32.S
|
|
index b59e4fb40fd9..c29020907886 100644
|
|
--- a/arch/x86/kernel/head_32.S
|
|
+++ b/arch/x86/kernel/head_32.S
|
|
@@ -37,7 +37,7 @@
|
|
#define X86 new_cpu_data+CPUINFO_x86
|
|
#define X86_VENDOR new_cpu_data+CPUINFO_x86_vendor
|
|
#define X86_MODEL new_cpu_data+CPUINFO_x86_model
|
|
-#define X86_STEPPING new_cpu_data+CPUINFO_x86_stepping
|
|
+#define X86_MASK new_cpu_data+CPUINFO_x86_mask
|
|
#define X86_HARD_MATH new_cpu_data+CPUINFO_hard_math
|
|
#define X86_CPUID new_cpu_data+CPUINFO_cpuid_level
|
|
#define X86_CAPABILITY new_cpu_data+CPUINFO_x86_capability
|
|
@@ -332,7 +332,7 @@ ENTRY(startup_32_smp)
|
|
shrb $4,%al
|
|
movb %al,X86_MODEL
|
|
andb $0x0f,%cl # mask mask revision
|
|
- movb %cl,X86_STEPPING
|
|
+ movb %cl,X86_MASK
|
|
movl %edx,X86_CAPABILITY
|
|
|
|
.Lis486:
|
|
diff --git a/arch/x86/kernel/mpparse.c b/arch/x86/kernel/mpparse.c
|
|
index bc6bc6689e68..3a4b12809ab5 100644
|
|
--- a/arch/x86/kernel/mpparse.c
|
|
+++ b/arch/x86/kernel/mpparse.c
|
|
@@ -407,7 +407,7 @@ static inline void __init construct_default_ISA_mptable(int mpc_default_type)
|
|
processor.apicver = mpc_default_type > 4 ? 0x10 : 0x01;
|
|
processor.cpuflag = CPU_ENABLED;
|
|
processor.cpufeature = (boot_cpu_data.x86 << 8) |
|
|
- (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_stepping;
|
|
+ (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
|
|
processor.featureflag = boot_cpu_data.x86_capability[CPUID_1_EDX];
|
|
processor.reserved[0] = 0;
|
|
processor.reserved[1] = 0;
|
|
diff --git a/arch/x86/lib/cpu.c b/arch/x86/lib/cpu.c
|
|
index 2dd1fe13a37b..d6f848d1211d 100644
|
|
--- a/arch/x86/lib/cpu.c
|
|
+++ b/arch/x86/lib/cpu.c
|
|
@@ -18,7 +18,7 @@ unsigned int x86_model(unsigned int sig)
|
|
{
|
|
unsigned int fam, model;
|
|
|
|
- fam = x86_family(sig);
|
|
+ fam = x86_family(sig);
|
|
|
|
model = (sig >> 4) & 0xf;
|
|
|
|
diff --git a/drivers/char/hw_random/via-rng.c b/drivers/char/hw_random/via-rng.c
|
|
index 6e9df558325b..d1f5bb534e0e 100644
|
|
--- a/drivers/char/hw_random/via-rng.c
|
|
+++ b/drivers/char/hw_random/via-rng.c
|
|
@@ -162,7 +162,7 @@ static int via_rng_init(struct hwrng *rng)
|
|
/* Enable secondary noise source on CPUs where it is present. */
|
|
|
|
/* Nehemiah stepping 8 and higher */
|
|
- if ((c->x86_model == 9) && (c->x86_stepping > 7))
|
|
+ if ((c->x86_model == 9) && (c->x86_mask > 7))
|
|
lo |= VIA_NOISESRC2;
|
|
|
|
/* Esther */
|
|
diff --git a/drivers/cpufreq/acpi-cpufreq.c b/drivers/cpufreq/acpi-cpufreq.c
|
|
index d0c34df0529c..3a2ca0f79daf 100644
|
|
--- a/drivers/cpufreq/acpi-cpufreq.c
|
|
+++ b/drivers/cpufreq/acpi-cpufreq.c
|
|
@@ -629,7 +629,7 @@ static int acpi_cpufreq_blacklist(struct cpuinfo_x86 *c)
|
|
if (c->x86_vendor == X86_VENDOR_INTEL) {
|
|
if ((c->x86 == 15) &&
|
|
(c->x86_model == 6) &&
|
|
- (c->x86_stepping == 8)) {
|
|
+ (c->x86_mask == 8)) {
|
|
pr_info("Intel(R) Xeon(R) 7100 Errata AL30, processors may lock up on frequency changes: disabling acpi-cpufreq\n");
|
|
return -ENODEV;
|
|
}
|
|
diff --git a/drivers/cpufreq/longhaul.c b/drivers/cpufreq/longhaul.c
|
|
index d5e27bc7585a..c46a12df40dd 100644
|
|
--- a/drivers/cpufreq/longhaul.c
|
|
+++ b/drivers/cpufreq/longhaul.c
|
|
@@ -775,7 +775,7 @@ static int longhaul_cpu_init(struct cpufreq_policy *policy)
|
|
break;
|
|
|
|
case 7:
|
|
- switch (c->x86_stepping) {
|
|
+ switch (c->x86_mask) {
|
|
case 0:
|
|
longhaul_version = TYPE_LONGHAUL_V1;
|
|
cpu_model = CPU_SAMUEL2;
|
|
@@ -787,7 +787,7 @@ static int longhaul_cpu_init(struct cpufreq_policy *policy)
|
|
break;
|
|
case 1 ... 15:
|
|
longhaul_version = TYPE_LONGHAUL_V2;
|
|
- if (c->x86_stepping < 8) {
|
|
+ if (c->x86_mask < 8) {
|
|
cpu_model = CPU_SAMUEL2;
|
|
cpuname = "C3 'Samuel 2' [C5B]";
|
|
} else {
|
|
@@ -814,7 +814,7 @@ static int longhaul_cpu_init(struct cpufreq_policy *policy)
|
|
numscales = 32;
|
|
memcpy(mults, nehemiah_mults, sizeof(nehemiah_mults));
|
|
memcpy(eblcr, nehemiah_eblcr, sizeof(nehemiah_eblcr));
|
|
- switch (c->x86_stepping) {
|
|
+ switch (c->x86_mask) {
|
|
case 0 ... 1:
|
|
cpu_model = CPU_NEHEMIAH;
|
|
cpuname = "C3 'Nehemiah A' [C5XLOE]";
|
|
diff --git a/drivers/cpufreq/p4-clockmod.c b/drivers/cpufreq/p4-clockmod.c
|
|
index a25741b1281b..fd77812313f3 100644
|
|
--- a/drivers/cpufreq/p4-clockmod.c
|
|
+++ b/drivers/cpufreq/p4-clockmod.c
|
|
@@ -168,7 +168,7 @@ static int cpufreq_p4_cpu_init(struct cpufreq_policy *policy)
|
|
#endif
|
|
|
|
/* Errata workaround */
|
|
- cpuid = (c->x86 << 8) | (c->x86_model << 4) | c->x86_stepping;
|
|
+ cpuid = (c->x86 << 8) | (c->x86_model << 4) | c->x86_mask;
|
|
switch (cpuid) {
|
|
case 0x0f07:
|
|
case 0x0f0a:
|
|
diff --git a/drivers/cpufreq/powernow-k7.c b/drivers/cpufreq/powernow-k7.c
|
|
index 302e9ce793a0..80ac313e6c59 100644
|
|
--- a/drivers/cpufreq/powernow-k7.c
|
|
+++ b/drivers/cpufreq/powernow-k7.c
|
|
@@ -131,7 +131,7 @@ static int check_powernow(void)
|
|
return 0;
|
|
}
|
|
|
|
- if ((c->x86_model == 6) && (c->x86_stepping == 0)) {
|
|
+ if ((c->x86_model == 6) && (c->x86_mask == 0)) {
|
|
pr_info("K7 660[A0] core detected, enabling errata workarounds\n");
|
|
have_a0 = 1;
|
|
}
|
|
diff --git a/drivers/cpufreq/speedstep-centrino.c b/drivers/cpufreq/speedstep-centrino.c
|
|
index 4fa5adf16c70..41bc5397f4bb 100644
|
|
--- a/drivers/cpufreq/speedstep-centrino.c
|
|
+++ b/drivers/cpufreq/speedstep-centrino.c
|
|
@@ -37,7 +37,7 @@ struct cpu_id
|
|
{
|
|
__u8 x86; /* CPU family */
|
|
__u8 x86_model; /* model */
|
|
- __u8 x86_stepping; /* stepping */
|
|
+ __u8 x86_mask; /* stepping */
|
|
};
|
|
|
|
enum {
|
|
@@ -277,7 +277,7 @@ static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c,
|
|
{
|
|
if ((c->x86 == x->x86) &&
|
|
(c->x86_model == x->x86_model) &&
|
|
- (c->x86_stepping == x->x86_stepping))
|
|
+ (c->x86_mask == x->x86_mask))
|
|
return 1;
|
|
return 0;
|
|
}
|
|
diff --git a/drivers/cpufreq/speedstep-lib.c b/drivers/cpufreq/speedstep-lib.c
|
|
index e3a9962ee410..8085ec9000d1 100644
|
|
--- a/drivers/cpufreq/speedstep-lib.c
|
|
+++ b/drivers/cpufreq/speedstep-lib.c
|
|
@@ -272,9 +272,9 @@ unsigned int speedstep_detect_processor(void)
|
|
ebx = cpuid_ebx(0x00000001);
|
|
ebx &= 0x000000FF;
|
|
|
|
- pr_debug("ebx value is %x, x86_stepping is %x\n", ebx, c->x86_stepping);
|
|
+ pr_debug("ebx value is %x, x86_mask is %x\n", ebx, c->x86_mask);
|
|
|
|
- switch (c->x86_stepping) {
|
|
+ switch (c->x86_mask) {
|
|
case 4:
|
|
/*
|
|
* B-stepping [M-P4-M]
|
|
@@ -361,7 +361,7 @@ unsigned int speedstep_detect_processor(void)
|
|
msr_lo, msr_hi);
|
|
if ((msr_hi & (1<<18)) &&
|
|
(relaxed_check ? 1 : (msr_hi & (3<<24)))) {
|
|
- if (c->x86_stepping == 0x01) {
|
|
+ if (c->x86_mask == 0x01) {
|
|
pr_debug("early PIII version\n");
|
|
return SPEEDSTEP_CPU_PIII_C_EARLY;
|
|
} else
|
|
diff --git a/drivers/crypto/padlock-aes.c b/drivers/crypto/padlock-aes.c
|
|
index 1c6cbda56afe..4b6642a25df5 100644
|
|
--- a/drivers/crypto/padlock-aes.c
|
|
+++ b/drivers/crypto/padlock-aes.c
|
|
@@ -512,7 +512,7 @@ static int __init padlock_init(void)
|
|
|
|
printk(KERN_NOTICE PFX "Using VIA PadLock ACE for AES algorithm.\n");
|
|
|
|
- if (c->x86 == 6 && c->x86_model == 15 && c->x86_stepping == 2) {
|
|
+ if (c->x86 == 6 && c->x86_model == 15 && c->x86_mask == 2) {
|
|
ecb_fetch_blocks = MAX_ECB_FETCH_BLOCKS;
|
|
cbc_fetch_blocks = MAX_CBC_FETCH_BLOCKS;
|
|
printk(KERN_NOTICE PFX "VIA Nano stepping 2 detected: enabling workaround.\n");
|
|
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
|
|
index 329cb96f886f..8b16ec595fa7 100644
|
|
--- a/drivers/edac/amd64_edac.c
|
|
+++ b/drivers/edac/amd64_edac.c
|
|
@@ -3147,7 +3147,7 @@ static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt)
|
|
struct amd64_family_type *fam_type = NULL;
|
|
|
|
pvt->ext_model = boot_cpu_data.x86_model >> 4;
|
|
- pvt->stepping = boot_cpu_data.x86_stepping;
|
|
+ pvt->stepping = boot_cpu_data.x86_mask;
|
|
pvt->model = boot_cpu_data.x86_model;
|
|
pvt->fam = boot_cpu_data.x86;
|
|
|
|
diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c
|
|
index a42744c7665b..c13a4fd86b3c 100644
|
|
--- a/drivers/hwmon/coretemp.c
|
|
+++ b/drivers/hwmon/coretemp.c
|
|
@@ -268,13 +268,13 @@ static int adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev)
|
|
for (i = 0; i < ARRAY_SIZE(tjmax_model_table); i++) {
|
|
const struct tjmax_model *tm = &tjmax_model_table[i];
|
|
if (c->x86_model == tm->model &&
|
|
- (tm->mask == ANY || c->x86_stepping == tm->mask))
|
|
+ (tm->mask == ANY || c->x86_mask == tm->mask))
|
|
return tm->tjmax;
|
|
}
|
|
|
|
/* Early chips have no MSR for TjMax */
|
|
|
|
- if (c->x86_model == 0xf && c->x86_stepping < 4)
|
|
+ if (c->x86_model == 0xf && c->x86_mask < 4)
|
|
usemsr_ee = 0;
|
|
|
|
if (c->x86_model > 0xe && usemsr_ee) {
|
|
@@ -425,7 +425,7 @@ static int chk_ucode_version(unsigned int cpu)
|
|
* Readings might stop update when processor visited too deep sleep,
|
|
* fixed for stepping D0 (6EC).
|
|
*/
|
|
- if (c->x86_model == 0xe && c->x86_stepping < 0xc && c->microcode < 0x39) {
|
|
+ if (c->x86_model == 0xe && c->x86_mask < 0xc && c->microcode < 0x39) {
|
|
pr_err("Errata AE18 not fixed, update BIOS or microcode of the CPU!\n");
|
|
return -ENODEV;
|
|
}
|
|
diff --git a/drivers/hwmon/hwmon-vid.c b/drivers/hwmon/hwmon-vid.c
|
|
index 84e91286fc4f..ef91b8a67549 100644
|
|
--- a/drivers/hwmon/hwmon-vid.c
|
|
+++ b/drivers/hwmon/hwmon-vid.c
|
|
@@ -293,7 +293,7 @@ u8 vid_which_vrm(void)
|
|
if (c->x86 < 6) /* Any CPU with family lower than 6 */
|
|
return 0; /* doesn't have VID */
|
|
|
|
- vrm_ret = find_vrm(c->x86, c->x86_model, c->x86_stepping, c->x86_vendor);
|
|
+ vrm_ret = find_vrm(c->x86, c->x86_model, c->x86_mask, c->x86_vendor);
|
|
if (vrm_ret == 134)
|
|
vrm_ret = get_via_model_d_vrm();
|
|
if (vrm_ret == 0)
|
|
diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c
|
|
index b960015cb073..0721e175664a 100644
|
|
--- a/drivers/hwmon/k10temp.c
|
|
+++ b/drivers/hwmon/k10temp.c
|
|
@@ -226,7 +226,7 @@ static bool has_erratum_319(struct pci_dev *pdev)
|
|
* and AM3 formats, but that's the best we can do.
|
|
*/
|
|
return boot_cpu_data.x86_model < 4 ||
|
|
- (boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_stepping <= 2);
|
|
+ (boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_mask <= 2);
|
|
}
|
|
|
|
static int k10temp_probe(struct pci_dev *pdev,
|
|
diff --git a/drivers/hwmon/k8temp.c b/drivers/hwmon/k8temp.c
|
|
index e59f9113fb93..5a632bcf869b 100644
|
|
--- a/drivers/hwmon/k8temp.c
|
|
+++ b/drivers/hwmon/k8temp.c
|
|
@@ -187,7 +187,7 @@ static int k8temp_probe(struct pci_dev *pdev,
|
|
return -ENOMEM;
|
|
|
|
model = boot_cpu_data.x86_model;
|
|
- stepping = boot_cpu_data.x86_stepping;
|
|
+ stepping = boot_cpu_data.x86_mask;
|
|
|
|
/* feature available since SH-C0, exclude older revisions */
|
|
if ((model == 4 && stepping == 0) ||
|
|
diff --git a/drivers/video/fbdev/geode/video_gx.c b/drivers/video/fbdev/geode/video_gx.c
|
|
index 67773e8bbb95..6082f653c68a 100644
|
|
--- a/drivers/video/fbdev/geode/video_gx.c
|
|
+++ b/drivers/video/fbdev/geode/video_gx.c
|
|
@@ -127,7 +127,7 @@ void gx_set_dclk_frequency(struct fb_info *info)
|
|
int timeout = 1000;
|
|
|
|
/* Rev. 1 Geode GXs use a 14 MHz reference clock instead of 48 MHz. */
|
|
- if (cpu_data(0).x86_stepping == 1) {
|
|
+ if (cpu_data(0).x86_mask == 1) {
|
|
pll_table = gx_pll_table_14MHz;
|
|
pll_table_len = ARRAY_SIZE(gx_pll_table_14MHz);
|
|
} else {
|