100 lines
2.8 KiB
Diff
100 lines
2.8 KiB
Diff
From b5df280bb16345875c0c1baf1db5607fde005395 Mon Sep 17 00:00:00 2001
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From: Andre Przywara <andre.przywara@arm.com>
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Date: Tue, 5 Jun 2018 22:17:01 -0700
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Subject: [PATCH 3/5] arm64: dts: allwinner: a64: Add PWM controllers
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The Allwinner A64 SoC features two PWM controllers, which are fully
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compatible to the one used in the A13 and H3 chips.
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Add the nodes for the devices (one for the "normal" PWM, the other for
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the one in the CPUS domain) and the pins their outputs are connected to.
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On the A64 the "normal" PWM is muxed together with one of the MDIO pins
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used to communicate with the Ethernet PHY, so it won't be usable on many
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boards. But the Pinebook laptop uses this pin for controlling the LCD
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backlight.
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On Pine64 the CPUS PWM pin however is routed to the "RPi2" header,
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at the same location as the PWM pin on the RaspberryPi.
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Tested on Pinebook and Teres-I
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[vasily: fixed comment message as requested by Stefan Bruens, added default
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muxing options to pwm and r_pwm nodes]
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Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
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Tested-by: Harald Geyer <harald@ccbib.org>
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Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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---
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arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 32 +++++++++++++++++++++++++++
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1 file changed, 32 insertions(+)
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diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
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index 1b31a3aaed5a..2777b2d02d77 100644
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--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
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@@ -365,6 +365,11 @@
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bias-pull-up;
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};
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+ pwm_pin: pwm_pin {
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+ pins = "PD22";
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+ function = "pwm";
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+ };
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+
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rmii_pins: rmii_pins {
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pins = "PD10", "PD11", "PD13", "PD14", "PD17",
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"PD18", "PD19", "PD20", "PD22", "PD23";
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@@ -630,6 +635,17 @@
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#interrupt-cells = <3>;
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};
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+ pwm: pwm@1c21400 {
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+ compatible = "allwinner,sun50i-a64-pwm",
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+ "allwinner,sun5i-a13-pwm";
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+ reg = <0x01c21400 0x400>;
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+ clocks = <&osc24M>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pwm_pin>;
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+ #pwm-cells = <3>;
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+ status = "disabled";
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+ };
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+
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rtc: rtc@1f00000 {
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compatible = "allwinner,sun6i-a31-rtc";
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reg = <0x01f00000 0x54>;
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@@ -671,6 +687,17 @@
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#size-cells = <0>;
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};
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+ r_pwm: pwm@1f03800 {
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+ compatible = "allwinner,sun50i-a64-pwm",
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+ "allwinner,sun5i-a13-pwm";
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+ reg = <0x01f03800 0x400>;
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+ clocks = <&osc24M>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&r_pwm_pin>;
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+ #pwm-cells = <3>;
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+ status = "disabled";
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+ };
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+
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r_pio: pinctrl@1f02c00 {
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compatible = "allwinner,sun50i-a64-r-pinctrl";
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reg = <0x01f02c00 0x400>;
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@@ -687,6 +714,11 @@
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function = "s_i2c";
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};
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+ r_pwm_pin: pwm {
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+ pins = "PL10";
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+ function = "s_pwm";
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+ };
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+
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r_rsb_pins: rsb {
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pins = "PL0", "PL1";
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function = "s_rsb";
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--
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2.11.0
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