65 lines
1.9 KiB
Diff
65 lines
1.9 KiB
Diff
From 871b5352125c49a2d5f31db69baede43e003a532 Mon Sep 17 00:00:00 2001
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From: Icenowy Zheng <icenowy@aosc.io>
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Date: Tue, 5 Jun 2018 22:17:00 -0700
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Subject: [PATCH 2/5] arm64: dts: allwinner: a64: add R_I2C controller
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Allwinner A64 has a I2C controller, which is in the R_ MMIO zone and has
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two groups of pinmuxes on PL bank, so it's called R_I2C.
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Add support for this I2C controller and the pinmux which doesn't conflict
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with RSB.
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Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
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Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
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Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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---
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arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 18 ++++++++++++++++++
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1 file changed, 18 insertions(+)
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diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
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index 82516aec4153..1b31a3aaed5a 100644
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--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
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@@ -46,6 +46,7 @@
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#include <dt-bindings/clock/sun8i-r-ccu.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/reset/sun50i-a64-ccu.h>
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+#include <dt-bindings/reset/sun8i-r-ccu.h>
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/ {
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interrupt-parent = <&gic>;
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@@ -658,6 +659,18 @@
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#reset-cells = <1>;
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};
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+ r_i2c: i2c@1f02400 {
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+ compatible = "allwinner,sun50i-a64-i2c",
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+ "allwinner,sun6i-a31-i2c";
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+ reg = <0x01f02400 0x400>;
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+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&r_ccu CLK_APB0_I2C>;
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+ resets = <&r_ccu RST_APB0_I2C>;
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+ status = "disabled";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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r_pio: pinctrl@1f02c00 {
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compatible = "allwinner,sun50i-a64-r-pinctrl";
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reg = <0x01f02c00 0x400>;
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@@ -669,6 +682,11 @@
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interrupt-controller;
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#interrupt-cells = <3>;
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+ r_i2c_pins_a: i2c-a {
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+ pins = "PL8", "PL9";
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+ function = "s_i2c";
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+ };
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+
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r_rsb_pins: rsb {
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pins = "PL0", "PL1";
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function = "s_rsb";
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--
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2.11.0
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