39 lines
1.5 KiB
Diff
39 lines
1.5 KiB
Diff
From: Chris Wilson <chris@chris-wilson.co.uk>
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Date: Sun, 20 Jan 2013 16:33:32 +0000
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Subject: drm/i915: GFX_MODE Flush TLB Invalidate Mode must be '1' for
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scanline waits
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commit f05bb0c7b624252a5e768287e340e8e45df96e42 upstream.
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On SNB, if bit 13 of GFX_MODE, Flush TLB Invalidate Mode, is not set to 1,
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the hardware can not program the scanline values. Those scanline values
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then control when the signal is sent from the display engine to the render
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ring for MI_WAIT_FOR_EVENTs. Note setting this bit means that TLB
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invalidations must be performed explicitly through the appropriate bits
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being set in PIPE_CONTROL.
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References: https://bugzilla.kernel.org/show_bug.cgi?id=52311
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Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
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Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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[bwh: Backported to 3.2: s/_MASKED_BIT/GFX_MODE/]
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Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
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---
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drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +++++
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1 file changed, 5 insertions(+)
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--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
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+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
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@@ -407,6 +407,11 @@ static int init_render_ring(struct intel
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if (INTEL_INFO(dev)->gen >= 6)
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I915_WRITE(MI_MODE, GFX_MODE_ENABLE(ASYNC_FLIP_PERF_DISABLE));
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+ /* Required for the hardware to program scanline values for waiting */
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+ if (INTEL_INFO(dev)->gen == 6)
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+ I915_WRITE(GFX_MODE,
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+ GFX_MODE_ENABLE(GFX_TLB_INVALIDATE_ALWAYS));
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+
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if (IS_GEN7(dev))
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I915_WRITE(GFX_MODE_GEN7,
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GFX_MODE_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
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