120 lines
4.7 KiB
Diff
120 lines
4.7 KiB
Diff
From de787f2bb763b7b5516f5c43df2e9c63be6ef279 Mon Sep 17 00:00:00 2001
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From: Thomas Gleixner <tglx@linutronix.de>
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Date: Thu, 21 Feb 2019 12:36:50 +0100
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Subject: [PATCH 04/30] x86/msr-index: Cleanup bit defines
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commit d8eabc37310a92df40d07c5a8afc53cebf996716 upstream
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Greg pointed out that speculation related bit defines are using (1 << N)
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format instead of BIT(N). Aside of that (1 << N) is wrong as it should use
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1UL at least.
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Clean it up.
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[ Josh Poimboeuf: Fix tools build ]
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Reported-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Reviewed-by: Borislav Petkov <bp@suse.de>
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Reviewed-by: Frederic Weisbecker <frederic@kernel.org>
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Reviewed-by: Jon Masters <jcm@redhat.com>
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Tested-by: Jon Masters <jcm@redhat.com>
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---
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arch/x86/include/asm/msr-index.h | 34 ++++++++++---------
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tools/power/x86/turbostat/Makefile | 2 +-
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.../power/x86/x86_energy_perf_policy/Makefile | 2 +-
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3 files changed, 20 insertions(+), 18 deletions(-)
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diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
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index f14ca0be1e3f..308b7c94df00 100644
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--- a/arch/x86/include/asm/msr-index.h
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+++ b/arch/x86/include/asm/msr-index.h
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@@ -2,6 +2,8 @@
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#ifndef _ASM_X86_MSR_INDEX_H
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#define _ASM_X86_MSR_INDEX_H
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+#include <linux/bits.h>
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+
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/*
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* CPU model specific register (MSR) numbers.
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*
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@@ -40,14 +42,14 @@
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/* Intel MSRs. Some also available on other CPUs */
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#define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */
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-#define SPEC_CTRL_IBRS (1 << 0) /* Indirect Branch Restricted Speculation */
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+#define SPEC_CTRL_IBRS BIT(0) /* Indirect Branch Restricted Speculation */
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#define SPEC_CTRL_STIBP_SHIFT 1 /* Single Thread Indirect Branch Predictor (STIBP) bit */
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-#define SPEC_CTRL_STIBP (1 << SPEC_CTRL_STIBP_SHIFT) /* STIBP mask */
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+#define SPEC_CTRL_STIBP BIT(SPEC_CTRL_STIBP_SHIFT) /* STIBP mask */
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#define SPEC_CTRL_SSBD_SHIFT 2 /* Speculative Store Bypass Disable bit */
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-#define SPEC_CTRL_SSBD (1 << SPEC_CTRL_SSBD_SHIFT) /* Speculative Store Bypass Disable */
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+#define SPEC_CTRL_SSBD BIT(SPEC_CTRL_SSBD_SHIFT) /* Speculative Store Bypass Disable */
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#define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */
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-#define PRED_CMD_IBPB (1 << 0) /* Indirect Branch Prediction Barrier */
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+#define PRED_CMD_IBPB BIT(0) /* Indirect Branch Prediction Barrier */
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#define MSR_PPIN_CTL 0x0000004e
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#define MSR_PPIN 0x0000004f
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@@ -69,20 +71,20 @@
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#define MSR_MTRRcap 0x000000fe
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#define MSR_IA32_ARCH_CAPABILITIES 0x0000010a
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-#define ARCH_CAP_RDCL_NO (1 << 0) /* Not susceptible to Meltdown */
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-#define ARCH_CAP_IBRS_ALL (1 << 1) /* Enhanced IBRS support */
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-#define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH (1 << 3) /* Skip L1D flush on vmentry */
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-#define ARCH_CAP_SSB_NO (1 << 4) /*
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- * Not susceptible to Speculative Store Bypass
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- * attack, so no Speculative Store Bypass
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- * control required.
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- */
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+#define ARCH_CAP_RDCL_NO BIT(0) /* Not susceptible to Meltdown */
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+#define ARCH_CAP_IBRS_ALL BIT(1) /* Enhanced IBRS support */
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+#define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH BIT(3) /* Skip L1D flush on vmentry */
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+#define ARCH_CAP_SSB_NO BIT(4) /*
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+ * Not susceptible to Speculative Store Bypass
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+ * attack, so no Speculative Store Bypass
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+ * control required.
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+ */
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#define MSR_IA32_FLUSH_CMD 0x0000010b
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-#define L1D_FLUSH (1 << 0) /*
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- * Writeback and invalidate the
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- * L1 data cache.
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- */
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+#define L1D_FLUSH BIT(0) /*
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+ * Writeback and invalidate the
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+ * L1 data cache.
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+ */
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#define MSR_IA32_BBL_CR_CTL 0x00000119
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#define MSR_IA32_BBL_CR_CTL3 0x0000011e
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diff --git a/tools/power/x86/turbostat/Makefile b/tools/power/x86/turbostat/Makefile
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index 2ab25aa38263..ff058bfbca3e 100644
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--- a/tools/power/x86/turbostat/Makefile
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+++ b/tools/power/x86/turbostat/Makefile
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@@ -9,7 +9,7 @@ ifeq ("$(origin O)", "command line")
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endif
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turbostat : turbostat.c
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-CFLAGS += -Wall
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+CFLAGS += -Wall -I../../../include
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CFLAGS += -DMSRHEADER='"../../../../arch/x86/include/asm/msr-index.h"'
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CFLAGS += -DINTEL_FAMILY_HEADER='"../../../../arch/x86/include/asm/intel-family.h"'
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diff --git a/tools/power/x86/x86_energy_perf_policy/Makefile b/tools/power/x86/x86_energy_perf_policy/Makefile
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index f4534fb8b951..da781b430937 100644
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--- a/tools/power/x86/x86_energy_perf_policy/Makefile
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+++ b/tools/power/x86/x86_energy_perf_policy/Makefile
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@@ -9,7 +9,7 @@ ifeq ("$(origin O)", "command line")
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endif
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x86_energy_perf_policy : x86_energy_perf_policy.c
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-CFLAGS += -Wall
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+CFLAGS += -Wall -I../../../include
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CFLAGS += -DMSRHEADER='"../../../../arch/x86/include/asm/msr-index.h"'
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%: %.c
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