86 lines
3.0 KiB
Diff
86 lines
3.0 KiB
Diff
From 75841ebf0d47558653b21d6cc88942c397d40a98 Mon Sep 17 00:00:00 2001
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From: Ben Hutchings <ben@decadent.org.uk>
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Date: Sun, 13 Jun 2010 21:23:29 +0100
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Subject: [PATCH] mips: Set io_map_base for several PCI bridges lacking it
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Several MIPS platforms don't set pci_controller::io_map_base for their
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PCI bridges. This results in a panic in pci_iomap(). (The panic is
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conditional on CONFIG_PCI_DOMAINS, but that is now enabled for all PCI
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MIPS systems.)
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I have tested the change to Malta in qemu; the other platforms not at
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all.
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---
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arch/mips/mti-malta/malta-pci.c | 2 ++
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arch/mips/nxp/pnx8550/common/pci.c | 1 +
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arch/mips/nxp/pnx8550/common/setup.c | 2 +-
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arch/mips/pci/ops-pmcmsp.c | 1 +
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arch/mips/pci/pci-yosemite.c | 1 +
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5 files changed, 6 insertions(+), 1 deletions(-)
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diff --git a/arch/mips/mti-malta/malta-pci.c b/arch/mips/mti-malta/malta-pci.c
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index 2fbfa1a..bf80921 100644
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--- a/arch/mips/mti-malta/malta-pci.c
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+++ b/arch/mips/mti-malta/malta-pci.c
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@@ -247,6 +247,8 @@ void __init mips_pcibios_init(void)
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iomem_resource.end &= 0xfffffffffULL; /* 64 GB */
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ioport_resource.end = controller->io_resource->end;
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+ controller->io_map_base = mips_io_port_base;
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+
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register_pci_controller(controller);
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}
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diff --git a/arch/mips/nxp/pnx8550/common/pci.c b/arch/mips/nxp/pnx8550/common/pci.c
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index eee4f3d..98e86dd 100644
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--- a/arch/mips/nxp/pnx8550/common/pci.c
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+++ b/arch/mips/nxp/pnx8550/common/pci.c
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@@ -44,6 +44,7 @@ extern struct pci_ops pnx8550_pci_ops;
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static struct pci_controller pnx8550_controller = {
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.pci_ops = &pnx8550_pci_ops,
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+ .io_map_base = PNX8550_PORT_BASE,
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.io_resource = &pci_io_resource,
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.mem_resource = &pci_mem_resource,
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};
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diff --git a/arch/mips/nxp/pnx8550/common/setup.c b/arch/mips/nxp/pnx8550/common/setup.c
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index 2aed50f..64246c9 100644
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--- a/arch/mips/nxp/pnx8550/common/setup.c
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+++ b/arch/mips/nxp/pnx8550/common/setup.c
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@@ -113,7 +113,7 @@ void __init plat_mem_setup(void)
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PNX8550_GLB2_ENAB_INTA_O = 0;
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/* IO/MEM resources. */
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- set_io_port_base(KSEG1);
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+ set_io_port_base(PNX8550_PORT_BASE);
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ioport_resource.start = 0;
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ioport_resource.end = ~0;
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iomem_resource.start = 0;
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diff --git a/arch/mips/pci/ops-pmcmsp.c b/arch/mips/pci/ops-pmcmsp.c
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index 04b3147..b7c03d8 100644
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--- a/arch/mips/pci/ops-pmcmsp.c
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+++ b/arch/mips/pci/ops-pmcmsp.c
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@@ -944,6 +944,7 @@ static struct pci_controller msp_pci_controller = {
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.pci_ops = &msp_pci_ops,
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.mem_resource = &pci_mem_resource,
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.mem_offset = 0,
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+ .io_map_base = MSP_PCI_IOSPACE_BASE,
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.io_resource = &pci_io_resource,
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.io_offset = 0
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};
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diff --git a/arch/mips/pci/pci-yosemite.c b/arch/mips/pci/pci-yosemite.c
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index 0357946..cf5e1a2 100644
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--- a/arch/mips/pci/pci-yosemite.c
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+++ b/arch/mips/pci/pci-yosemite.c
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@@ -54,6 +54,7 @@ static int __init pmc_yosemite_setup(void)
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panic(ioremap_failed);
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set_io_port_base(io_v_base);
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+ py_controller.io_map_base = io_v_base;
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TITAN_WRITE(RM9000x2_OCD_LKM7, TITAN_READ(RM9000x2_OCD_LKM7) | 1);
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ioport_resource.end = TITAN_IO_SIZE - 1;
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--
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1.7.1
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