88 lines
3.2 KiB
Diff
88 lines
3.2 KiB
Diff
From 0249842554e776541173cf005b179a2c38955b19 Mon Sep 17 00:00:00 2001
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Message-Id: <0249842554e776541173cf005b179a2c38955b19.1601675152.git.zanussi@kernel.org>
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In-Reply-To: <5b5a156f9808b1acf1205606e03da117214549ea.1601675151.git.zanussi@kernel.org>
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References: <5b5a156f9808b1acf1205606e03da117214549ea.1601675151.git.zanussi@kernel.org>
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From: Haris Okanovic <haris.okanovic@ni.com>
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Date: Tue, 15 Aug 2017 15:13:08 -0500
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Subject: [PATCH 249/333] tpm_tis: fix stall after iowrite*()s
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Origin: https://www.kernel.org/pub/linux/kernel/projects/rt/4.19/older/patches-4.19.148-rt64.tar.xz
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ioread8() operations to TPM MMIO addresses can stall the cpu when
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immediately following a sequence of iowrite*()'s to the same region.
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For example, cyclitest measures ~400us latency spikes when a non-RT
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usermode application communicates with an SPI-based TPM chip (Intel Atom
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E3940 system, PREEMPT_RT_FULL kernel). The spikes are caused by a
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stalling ioread8() operation following a sequence of 30+ iowrite8()s to
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the same address. I believe this happens because the write sequence is
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buffered (in cpu or somewhere along the bus), and gets flushed on the
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first LOAD instruction (ioread*()) that follows.
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The enclosed change appears to fix this issue: read the TPM chip's
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access register (status code) after every iowrite*() operation to
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amortize the cost of flushing data to chip across multiple instructions.
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Signed-off-by: Haris Okanovic <haris.okanovic@ni.com>
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Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
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---
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drivers/char/tpm/tpm_tis.c | 29 +++++++++++++++++++++++++++--
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1 file changed, 27 insertions(+), 2 deletions(-)
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diff --git a/drivers/char/tpm/tpm_tis.c b/drivers/char/tpm/tpm_tis.c
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index f08949a5f678..9fefcfcae593 100644
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--- a/drivers/char/tpm/tpm_tis.c
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+++ b/drivers/char/tpm/tpm_tis.c
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@@ -53,6 +53,31 @@ static inline struct tpm_tis_tcg_phy *to_tpm_tis_tcg_phy(struct tpm_tis_data *da
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return container_of(data, struct tpm_tis_tcg_phy, priv);
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}
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+#ifdef CONFIG_PREEMPT_RT_FULL
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+/*
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+ * Flushes previous write operations to chip so that a subsequent
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+ * ioread*()s won't stall a cpu.
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+ */
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+static inline void tpm_tis_flush(void __iomem *iobase)
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+{
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+ ioread8(iobase + TPM_ACCESS(0));
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+}
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+#else
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+#define tpm_tis_flush(iobase) do { } while (0)
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+#endif
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+
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+static inline void tpm_tis_iowrite8(u8 b, void __iomem *iobase, u32 addr)
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+{
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+ iowrite8(b, iobase + addr);
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+ tpm_tis_flush(iobase);
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+}
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+
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+static inline void tpm_tis_iowrite32(u32 b, void __iomem *iobase, u32 addr)
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+{
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+ iowrite32(b, iobase + addr);
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+ tpm_tis_flush(iobase);
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+}
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+
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static bool interrupts = true;
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module_param(interrupts, bool, 0444);
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MODULE_PARM_DESC(interrupts, "Enable interrupts");
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@@ -150,7 +175,7 @@ static int tpm_tcg_write_bytes(struct tpm_tis_data *data, u32 addr, u16 len,
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struct tpm_tis_tcg_phy *phy = to_tpm_tis_tcg_phy(data);
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while (len--)
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- iowrite8(*value++, phy->iobase + addr);
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+ tpm_tis_iowrite8(*value++, phy->iobase, addr);
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return 0;
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}
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@@ -177,7 +202,7 @@ static int tpm_tcg_write32(struct tpm_tis_data *data, u32 addr, u32 value)
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{
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struct tpm_tis_tcg_phy *phy = to_tpm_tis_tcg_phy(data);
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- iowrite32(value, phy->iobase + addr);
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+ tpm_tis_iowrite32(value, phy->iobase, addr);
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return 0;
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}
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--
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2.17.1
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