* backport MIPS FPU emulator: allow Cause bits of FCSR to be writeable
by ctc1. (closes: #580602). svn path=/dists/sid/linux-2.6/; revision=15659
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Aurelien Jarno
parent
49ede2ac48
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ff12f60bcc
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@ -27,6 +27,8 @@ linux-2.6 (2.6.32-13) UNRELEASED; urgency=low
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* mips/swarm: fix boot from IDE based media (Sebastian Andrzej Siewior)
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(closes: #466977).
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* backport mips/swarm: fix M3 TLB exception handler.
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* backport MIPS FPU emulator: allow Cause bits of FCSR to be writeable
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by ctc1. (closes: #580602).
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-- Frederik Schüler <fs@debian.org> Wed, 05 May 2010 17:54:01 +0200
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@ -0,0 +1,99 @@
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From: Shane McDonald <mcdonald.shane@gmail.com>
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Date: Fri, 7 May 2010 05:26:57 +0000 (-0600)
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Subject: MIPS FPU emulator: allow Cause bits of FCSR to be writeable by ctc1
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X-Git-Url: http://www.linux-mips.org/git?p=linux.git;a=commitdiff_plain;h=2c8fb481214e608f6b9a71aa85651d9ddf7fd6e4
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MIPS FPU emulator: allow Cause bits of FCSR to be writeable by ctc1
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In the FPU emulator code of the MIPS, the Cause bits of the FCSR register
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are not currently writeable by the ctc1 instruction. In odd corner cases,
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this can cause problems. For example, a case existed where a divide-by-zero
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exception was generated by the FPU, and the signal handler attempted to
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restore the FPU registers to their state before the exception occurred. In
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this particular setup, writing the old value to the FCSR register would
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cause another divide-by-zero exception to occur immediately. The solution
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is to change the ctc1 instruction emulator code to allow the Cause bits of
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the FCSR register to be writeable. This is the behaviour of the hardware
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that the code is emulating.
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This problem was found by Shane McDonald, but the credit for the fix goes
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to Kevin Kissell. In Kevin's words:
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I submit that the bug is indeed in that ctc_op: case of the emulator. The
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Cause bits (17:12) are supposed to be writable by that instruction, but the
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CTC1 emulation won't let them be updated by the instruction. I think that
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actually if you just completely removed lines 387-388 [...] things would
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work a good deal better. At least, it would be a more accurate emulation of
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the architecturally defined FPU. If I wanted to be really, really pedantic
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(which I sometimes do), I'd also protect the reserved bits that aren't
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necessarily writable.
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Signed-off-by: Shane McDonald <mcdonald.shane@gmail.com>
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To: anemo@mba.ocn.ne.jp
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To: kevink@paralogos.com
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To: sshtylyov@mvista.com
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Patchwork: http://patchwork.linux-mips.org/patch/1205/
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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(cherry picked from commit 635be78c7c80d4c61f0f16b6132a730d7668cb43)
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---
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diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
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index a581d60..608dc97 100644
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--- a/arch/mips/include/asm/mipsregs.h
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+++ b/arch/mips/include/asm/mipsregs.h
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@@ -135,6 +135,12 @@
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#define FPU_CSR_COND7 0x80000000 /* $fcc7 */
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/*
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+ * Bits 18 - 20 of the FPU Status Register will be read as 0,
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+ * and should be written as zero.
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+ */
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+#define FPU_CSR_RSVD 0x001c0000
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+
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+/*
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* X the exception cause indicator
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* E the exception enable
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* S the sticky/flag bit
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@@ -161,7 +167,8 @@
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#define FPU_CSR_UDF_S 0x00000008
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#define FPU_CSR_INE_S 0x00000004
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-/* rounding mode */
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+/* Bits 0 and 1 of FPU Status Register specify the rounding mode */
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+#define FPU_CSR_RM 0x00000003
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#define FPU_CSR_RN 0x0 /* nearest */
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#define FPU_CSR_RZ 0x1 /* towards zero */
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#define FPU_CSR_RU 0x2 /* towards +Infinity */
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diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
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index 454b539..c15d94b 100644
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--- a/arch/mips/math-emu/cp1emu.c
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+++ b/arch/mips/math-emu/cp1emu.c
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@@ -75,6 +75,9 @@ struct mips_fpu_emulator_stats fpuemustats;
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#define FPCREG_RID 0 /* $0 = revision id */
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#define FPCREG_CSR 31 /* $31 = csr */
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+/* Determine rounding mode from the RM bits of the FCSR */
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+#define modeindex(v) ((v) & FPU_CSR_RM)
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+
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/* Convert Mips rounding mode (0..3) to IEEE library modes. */
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static const unsigned char ieee_rm[4] = {
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[FPU_CSR_RN] = IEEE754_RN,
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@@ -381,10 +384,14 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
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(void *) (xcp->cp0_epc),
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MIPSInst_RT(ir), value);
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#endif
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- value &= (FPU_CSR_FLUSH | FPU_CSR_ALL_E | FPU_CSR_ALL_S | 0x03);
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- ctx->fcr31 &= ~(FPU_CSR_FLUSH | FPU_CSR_ALL_E | FPU_CSR_ALL_S | 0x03);
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- /* convert to ieee library modes */
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- ctx->fcr31 |= (value & ~0x3) | ieee_rm[value & 0x3];
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+
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+ /*
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+ * Don't write reserved bits,
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+ * and convert to ieee library modes
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+ */
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+ ctx->fcr31 = (value &
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+ ~(FPU_CSR_RSVD | FPU_CSR_RM)) |
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+ ieee_rm[modeindex(value)];
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}
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if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
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return SIGFPE;
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@ -10,3 +10,4 @@
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+ features/all/rtl8192su-Add-Sitecom-WL-349.patch
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+ bugfix/mips/mips-ide-flush-dcache.patch
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+ bugfix/mips/sibyte-m3-tlb-exception.patch
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+ bugfix/mips/fpu-emulator.patch
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