[mips*] Emulate unaligned LDXC1 and SDXC1 instructions.

debian/changelog

@@ -7,6 +7,9 @@ linux (4.5.1-2) UNRELEASED; urgency=medium
   [ Ben Hutchings ]
   * fs: Consolidate softdep declarations in each module
 
+  [ Aurelien Jarno ]
+  * [mips*] Emulate unaligned LDXC1 and SDXC1 instructions.
+
  -- Salvatore Bonaccorso <carnil@debian.org>  Thu, 14 Apr 2016 20:52:28 +0200
 
 linux (4.5.1-1) unstable; urgency=medium

debian/patches/bugfix/mips/MIPS-Allow-emulation-for-unaligned-LSDXC1-instructions.patch

@@ -0,0 +1,33 @@
+From: Paul Burton <paul.burton@imgtec.com>
+Date: Thu, 21 Apr 2016 12:25:38 +0100
+Subject: MIPS: Allow emulation for unaligned [LS]DXC1 instructions
+Origin: https://patchwork.linux-mips.org/patch/13143/
+
+If an address error exception occurs for a LDXC1 or SDXC1 instruction,
+within the cop1x opcode space, allow it to be passed through to the FPU
+emulator rather than resulting in a SIGILL. This causes LDXC1 & SDXC1 to
+be handled in a manner consistent with the more common LDC1 & SDC1
+instructions.
+
+Signed-off-by: Paul Burton <paul.burton@imgtec.com>
+Cc: Aurelien Jarno <aurelien@aurel32.net>
+---
+ arch/mips/kernel/unaligned.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c
+index 5c62065..28b3af7 100644
+--- a/arch/mips/kernel/unaligned.c
++++ b/arch/mips/kernel/unaligned.c
+@@ -1191,6 +1191,7 @@ static void emulate_load_store_insn(struct pt_regs *regs,
+ 	case ldc1_op:
+ 	case swc1_op:
+ 	case sdc1_op:
++	case cop1x_op:
+ 		die_if_kernel("Unaligned FP access in kernel code", regs);
+ 		BUG_ON(!used_math());
+ 
+-- 
+2.8.0
+
+

debian/patches/series

@@ -45,6 +45,7 @@ debian/snd-pcsp-disable-autoload.patch
 bugfix/x86/viafb-autoload-on-olpc-xo1.5-only.patch
 
 # Arch bug fixes
+bugfix/mips/MIPS-Allow-emulation-for-unaligned-LSDXC1-instructions.patch
 bugfix/x86/vmxnet3-fix-lock-imbalance-in-vmxnet3_tq_xmit.patch
 bugfix/x86/acpi-processor-request-native-thermal-interrupt-hand.patch