[mips] SB1: Fix interrupt disable hazard (Ralf Baechle).
svn path=/dists/trunk/linux-2.6/; revision=6182
This commit is contained in:
Martin Michlmayr
parent
972d653e1f
commit
a8ba20e2a2
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@ -9,6 +9,7 @@ linux-2.6 (2.6.15+2.6.16-rc6-0experimental.1) UNRELEASED; urgency=low
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[ Martin Michlmayr ]
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* [arm, armeb] Enable the netconsole module.
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* [mipsel/cobalt] Enable the netconsole module.
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* [mips] SB1: Fix interrupt disable hazard (Ralf Baechle).
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[ dann frazier ]
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* [ia64] use yaird on ia64 until #341181 is fixed
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@ -0,0 +1,273 @@
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From: linux-mips@linux-mips.org
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Date: Mon, 13 Mar 2006 16:07:47 +0000
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To: git-commits@linux-mips.org
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Subject: [MIPS] SB1: Fix interrupt disable hazard.
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Author: Ralf Baechle <ralf@linux-mips.org> Mon Mar 13 16:16:29 2006 +0000
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Commit: fa9e2c8227a0a770fbc748d35d0ec1d906c34614
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Gitweb: http://www.linux-mips.org/g/linux/fa9e2c82
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Branch: master
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The SB1 core has a three cycle interrupt disable hazard but we were
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wrongly treating it as fully interlocked.
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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---
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include/asm-mips/hazards.h | 180 +++++++++++++++++++++++++-------------------
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1 files changed, 103 insertions(+), 77 deletions(-)
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diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h
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index 6111a0c..feb29a7 100644
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--- a/include/asm-mips/hazards.h
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+++ b/include/asm-mips/hazards.h
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@@ -3,7 +3,9 @@
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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- * Copyright (C) 2003, 2004 Ralf Baechle
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+ * Copyright (C) 2003, 2004 Ralf Baechle <ralf@linux-mips.org>
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+ * Copyright (C) MIPS Technologies, Inc.
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+ * written by Ralf Baechle <ralf@linux-mips.org>
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*/
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#ifndef _ASM_HAZARDS_H
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#define _ASM_HAZARDS_H
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@@ -74,8 +76,7 @@
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#define irq_disable_hazard
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_ehb
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-#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) || \
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- defined(CONFIG_CPU_SB1)
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+#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000)
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/*
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* R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
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@@ -99,13 +100,13 @@
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#else /* __ASSEMBLY__ */
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__asm__(
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- " .macro _ssnop \n\t"
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- " sll $0, $0, 1 \n\t"
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- " .endm \n\t"
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- " \n\t"
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- " .macro _ehb \n\t"
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- " sll $0, $0, 3 \n\t"
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- " .endm \n\t");
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+ " .macro _ssnop \n"
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+ " sll $0, $0, 1 \n"
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+ " .endm \n"
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+ " \n"
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+ " .macro _ehb \n"
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+ " sll $0, $0, 3 \n"
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+ " .endm \n");
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#ifdef CONFIG_CPU_RM9000
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@@ -117,17 +118,21 @@ __asm__(
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#define mtc0_tlbw_hazard() \
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__asm__ __volatile__( \
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- ".set\tmips32\n\t" \
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- "_ssnop; _ssnop; _ssnop; _ssnop\n\t" \
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- ".set\tmips0")
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+ " .set mips32 \n" \
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+ " _ssnop \n" \
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+ " _ssnop \n" \
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+ " _ssnop \n" \
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+ " _ssnop \n" \
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+ " .set mips0 \n")
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#define tlbw_use_hazard() \
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__asm__ __volatile__( \
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- ".set\tmips32\n\t" \
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- "_ssnop; _ssnop; _ssnop; _ssnop\n\t" \
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- ".set\tmips0")
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-
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-#define back_to_back_c0_hazard() do { } while (0)
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+ " .set mips32 \n" \
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+ " _ssnop \n" \
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+ " _ssnop \n" \
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+ " _ssnop \n" \
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+ " _ssnop \n" \
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+ " .set mips0 \n")
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#else
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@@ -136,15 +141,25 @@ __asm__(
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*/
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#define mtc0_tlbw_hazard() \
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__asm__ __volatile__( \
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- ".set noreorder\n\t" \
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- "nop; nop; nop; nop; nop; nop;\n\t" \
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- ".set reorder\n\t")
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+ " .set noreorder \n" \
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+ " nop \n" \
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+ " nop \n" \
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+ " nop \n" \
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+ " nop \n" \
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+ " nop \n" \
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+ " nop \n" \
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+ " .set reorder \n")
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#define tlbw_use_hazard() \
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__asm__ __volatile__( \
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- ".set noreorder\n\t" \
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- "nop; nop; nop; nop; nop; nop;\n\t" \
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- ".set reorder\n\t")
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+ " .set noreorder \n" \
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+ " nop \n" \
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+ " nop \n" \
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+ " nop \n" \
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+ " nop \n" \
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+ " nop \n" \
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+ " nop \n" \
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+ " .set reorder \n")
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#endif
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@@ -156,49 +171,26 @@ __asm__(
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#ifdef CONFIG_CPU_MIPSR2
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-__asm__(
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- " .macro\tirq_enable_hazard \n\t"
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- " _ehb \n\t"
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- " .endm \n\t"
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- " \n\t"
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- " .macro\tirq_disable_hazard \n\t"
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- " _ehb \n\t"
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- " .endm \n\t"
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- " \n\t"
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- " .macro\tback_to_back_c0_hazard \n\t"
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- " _ehb \n\t"
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- " .endm");
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-
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-#define irq_enable_hazard() \
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- __asm__ __volatile__( \
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- "irq_enable_hazard")
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+__asm__(" .macro irq_enable_hazard \n"
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+ " _ehb \n"
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+ " .endm \n"
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+ " \n"
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+ " .macro irq_disable_hazard \n"
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+ " _ehb \n"
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+ " .endm \n");
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-#define irq_disable_hazard() \
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- __asm__ __volatile__( \
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- "irq_disable_hazard")
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-
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-#define back_to_back_c0_hazard() \
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- __asm__ __volatile__( \
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- "back_to_back_c0_hazard")
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-
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-#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) || \
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- defined(CONFIG_CPU_SB1)
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+#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000)
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/*
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* R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
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*/
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__asm__(
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- " .macro\tirq_enable_hazard \n\t"
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- " .endm \n\t"
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- " \n\t"
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- " .macro\tirq_disable_hazard \n\t"
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- " .endm");
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-
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-#define irq_enable_hazard() do { } while (0)
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-#define irq_disable_hazard() do { } while (0)
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-
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-#define back_to_back_c0_hazard() do { } while (0)
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+ " .macro irq_enable_hazard \n"
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+ " .endm \n"
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+ " \n"
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+ " .macro irq_disable_hazard \n"
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+ " .endm \n");
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#else
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@@ -209,29 +201,63 @@ __asm__(
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*/
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__asm__(
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- " # \n\t"
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- " # There is a hazard but we do not care \n\t"
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- " # \n\t"
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- " .macro\tirq_enable_hazard \n\t"
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- " .endm \n\t"
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- " \n\t"
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- " .macro\tirq_disable_hazard \n\t"
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- " _ssnop; _ssnop; _ssnop \n\t"
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- " .endm");
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+ " # \n"
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+ " # There is a hazard but we do not care \n"
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+ " # \n"
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+ " .macro\tirq_enable_hazard \n"
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+ " .endm \n"
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+ " \n"
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+ " .macro\tirq_disable_hazard \n"
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+ " _ssnop \n"
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+ " _ssnop \n"
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+ " _ssnop \n"
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+ " .endm \n");
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-#define irq_enable_hazard() do { } while (0)
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+#endif
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+
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+#define irq_enable_hazard() \
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+ __asm__ __volatile__("irq_enable_hazard")
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#define irq_disable_hazard() \
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- __asm__ __volatile__( \
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- "irq_disable_hazard")
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+ __asm__ __volatile__("irq_disable_hazard")
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-#define back_to_back_c0_hazard() \
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- __asm__ __volatile__( \
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- " .set noreorder \n" \
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- " nop; nop; nop \n" \
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- " .set reorder \n")
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+
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+/*
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+ * Back-to-back hazards -
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+ *
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+ * What is needed to separate a move to cp0 from a subsequent read from the
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+ * same cp0 register?
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+ */
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+#ifdef CONFIG_CPU_MIPSR2
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+
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+__asm__(" .macro back_to_back_c0_hazard \n"
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+ " _ehb \n"
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+ " .endm \n");
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+
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+#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) || \
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+ defined(CONFIG_CPU_SB1)
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+
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+__asm__(" .macro back_to_back_c0_hazard \n"
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+ " .endm \n");
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+
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+#else
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+
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+__asm__(" .macro back_to_back_c0_hazard \n"
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+ " .set noreorder \n"
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+ " _ssnop \n"
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+ " _ssnop \n"
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+ " _ssnop \n"
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+ " .set reorder \n"
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+ " .endm");
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#endif
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+#define back_to_back_c0_hazard() \
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+ __asm__ __volatile__("back_to_back_c0_hazard")
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+
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+
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+/*
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+ * Instruction execution hazard
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+ */
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#ifdef CONFIG_CPU_MIPSR2
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/*
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* gcc has a tradition of misscompiling the previous construct using the
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@ -19,5 +19,6 @@
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+ mips-gettimeofday.patch
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+ mips-ide-scan.patch
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+ mips-sb1-probe-ide.patch
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+ mips-sb1-irq-hazard.patch
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+ s390-drivers-ccw-uevent-modalias.patch
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+ s390-drivers-ccw-uevent-cleanup.patch
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