From a2a6a1fe3e0268d936d28309b2191b5e51376ff7 Mon Sep 17 00:00:00 2001 From: Ben Hutchings Date: Sun, 27 Apr 2014 13:46:49 +0000 Subject: [PATCH] [armhf] Enable more Allwinner/sunxi drivers (Closes: #745972) - spi: sunxi: Add Allwinner A31 SPI controller driver - ARM: dt: sun4i: Add A10 SPI controller nodes - PHY: sunxi: Add driver for sunxi usb phy - ARM: sun4i: dt: Add USB host bindings - Enable PHY_SUN4I_USB, RTC_DRV_SUNXI, SPI_SUN6I, USB_EHCI_HCD_PLATFORM, USB_OHCI_HCD_PLATFORM and CONFIG_SUNXI_WATCHDOG as modules svn path=/dists/trunk/linux/; revision=21273 --- debian/changelog | 9 +- debian/config/armhf/config.armmp | 6 + ...-Allwinner-A31-SPI-controller-driver.patch | 570 ++++++++++++++++++ ...Fix-define-for-SUN6I_TFR_CTL_CS_MASK.patch | 30 + ...ts_per_word_mask-to-only-support-8-b.patch | 29 + ...t-sun4i-Add-A10-SPI-controller-nodes.patch | 72 +++ .../ARM-sun4i-dt-Add-USB-host-bindings.patch | 82 +++ ...Y-sunxi-Add-driver-for-sunxi-usb-phy.patch | 412 +++++++++++++ debian/patches/series | 6 + 9 files changed, 1214 insertions(+), 2 deletions(-) create mode 100644 debian/patches/features/arm/0001-spi-sunxi-Add-Allwinner-A31-SPI-controller-driver.patch create mode 100644 debian/patches/features/arm/0002-spi-sun6i-Fix-define-for-SUN6I_TFR_CTL_CS_MASK.patch create mode 100644 debian/patches/features/arm/0003-spi-sun6i-Set-bits_per_word_mask-to-only-support-8-b.patch create mode 100644 debian/patches/features/arm/ARM-dt-sun4i-Add-A10-SPI-controller-nodes.patch create mode 100644 debian/patches/features/arm/ARM-sun4i-dt-Add-USB-host-bindings.patch create mode 100644 debian/patches/features/arm/PHY-sunxi-Add-driver-for-sunxi-usb-phy.patch diff --git a/debian/changelog b/debian/changelog index fce8aed35..456405e0e 100644 --- a/debian/changelog +++ b/debian/changelog @@ -11,8 +11,13 @@ linux (3.14.2-1~exp1) UNRELEASED; urgency=medium * [x86] Enable X86_INTEL_LPSS (Closes: #745331) * [x86] thinkpad_acpi: Add support for X1 Carbon 2nd generation's adaptive keyboard (Closes: #745252) - * [armhf] Enable RTC_DRV_SUNXI, USB_EHCI_HCD_PLATFORM, USB_OHCI_HCD_PLATFORM - and CONFIG_SUNXI_WATCHDOG as modules + * [armhf] Enable more Allwinner/sunxi drivers (Closes: #745972): + - spi: sunxi: Add Allwinner A31 SPI controller driver + - ARM: dt: sun4i: Add A10 SPI controller nodes + - PHY: sunxi: Add driver for sunxi usb phy + - ARM: sun4i: dt: Add USB host bindings + - Enable PHY_SUN4I_USB, RTC_DRV_SUNXI, SPI_SUN6I, USB_EHCI_HCD_PLATFORM, + USB_OHCI_HCD_PLATFORM and CONFIG_SUNXI_WATCHDOG as modules -- Ben Hutchings Sun, 20 Apr 2014 21:54:54 +0100 diff --git a/debian/config/armhf/config.armmp b/debian/config/armhf/config.armmp index 712197fef..c43f74e6a 100644 --- a/debian/config/armhf/config.armmp +++ b/debian/config/armhf/config.armmp @@ -485,6 +485,11 @@ CONFIG_WL18XX=m CONFIG_WLCORE_SPI=m CONFIG_WLCORE_SDIO=m +## +## file: drivers/phy/Kconfig +## +CONFIG_PHY_SUN4I_USB=m + ## ## file: drivers/pinctrl/vt8500/Kconfig ## @@ -553,6 +558,7 @@ CONFIG_SPI_GPIO=y CONFIG_SPI_OMAP24XX=m CONFIG_SPI_ORION=m CONFIG_SPI_PL022=m +CONFIG_SPI_SUN6I=m CONFIG_SPI_SPIDEV=y ## diff --git a/debian/patches/features/arm/0001-spi-sunxi-Add-Allwinner-A31-SPI-controller-driver.patch b/debian/patches/features/arm/0001-spi-sunxi-Add-Allwinner-A31-SPI-controller-driver.patch new file mode 100644 index 000000000..61c229c9f --- /dev/null +++ b/debian/patches/features/arm/0001-spi-sunxi-Add-Allwinner-A31-SPI-controller-driver.patch @@ -0,0 +1,570 @@ +From: Maxime Ripard +Date: Wed, 5 Feb 2014 14:05:05 +0100 +Subject: [1/3] spi: sunxi: Add Allwinner A31 SPI controller driver +Origin: https://git.kernel.org/linus/3558fe900e8af6c3bfadeff24a12ffb19ac9b108 + +The Allwinner A31 has a new SPI controller IP compared to the older Allwinner +SoCs. + +It supports DMA, but the driver only does PIO for now, and DMA will be +supported eventually. + +Signed-off-by: Maxime Ripard +Signed-off-by: Mark Brown +--- + .../devicetree/bindings/spi/spi-sun6i.txt | 24 + + drivers/spi/Kconfig | 6 + + drivers/spi/Makefile | 1 + + drivers/spi/spi-sun6i.c | 483 +++++++++++++++++++++ + 4 files changed, 514 insertions(+) + create mode 100644 Documentation/devicetree/bindings/spi/spi-sun6i.txt + create mode 100644 drivers/spi/spi-sun6i.c + +diff --git a/Documentation/devicetree/bindings/spi/spi-sun6i.txt b/Documentation/devicetree/bindings/spi/spi-sun6i.txt +new file mode 100644 +index 0000000..21de73d +--- /dev/null ++++ b/Documentation/devicetree/bindings/spi/spi-sun6i.txt +@@ -0,0 +1,24 @@ ++Allwinner A31 SPI controller ++ ++Required properties: ++- compatible: Should be "allwinner,sun6i-a31-spi". ++- reg: Should contain register location and length. ++- interrupts: Should contain interrupt. ++- clocks: phandle to the clocks feeding the SPI controller. Two are ++ needed: ++ - "ahb": the gated AHB parent clock ++ - "mod": the parent module clock ++- clock-names: Must contain the clock names described just above ++- resets: phandle to the reset controller asserting this device in ++ reset ++ ++Example: ++ ++spi1: spi@01c69000 { ++ compatible = "allwinner,sun6i-a31-spi"; ++ reg = <0x01c69000 0x1000>; ++ interrupts = <0 66 4>; ++ clocks = <&ahb1_gates 21>, <&spi1_clk>; ++ clock-names = "ahb", "mod"; ++ resets = <&ahb1_rst 21>; ++}; +diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig +index ba9310b..7cfe0ee 100644 +--- a/drivers/spi/Kconfig ++++ b/drivers/spi/Kconfig +@@ -446,6 +446,12 @@ config SPI_SIRF + help + SPI driver for CSR SiRFprimaII SoCs + ++config SPI_SUN6I ++ tristate "Allwinner A31 SPI controller" ++ depends on ARCH_SUNXI || COMPILE_TEST ++ help ++ This enables using the SPI controller on the Allwinner A31 SoCs. ++ + config SPI_MXS + tristate "Freescale MXS SPI controller" + depends on ARCH_MXS +diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile +index 95af48d..13b6ccf 100644 +--- a/drivers/spi/Makefile ++++ b/drivers/spi/Makefile +@@ -70,6 +70,7 @@ obj-$(CONFIG_SPI_SH_HSPI) += spi-sh-hspi.o + obj-$(CONFIG_SPI_SH_MSIOF) += spi-sh-msiof.o + obj-$(CONFIG_SPI_SH_SCI) += spi-sh-sci.o + obj-$(CONFIG_SPI_SIRF) += spi-sirf.o ++obj-$(CONFIG_SPI_SUN6I) += spi-sun6i.o + obj-$(CONFIG_SPI_TEGRA114) += spi-tegra114.o + obj-$(CONFIG_SPI_TEGRA20_SFLASH) += spi-tegra20-sflash.o + obj-$(CONFIG_SPI_TEGRA20_SLINK) += spi-tegra20-slink.o +diff --git a/drivers/spi/spi-sun6i.c b/drivers/spi/spi-sun6i.c +new file mode 100644 +index 0000000..94d38d0 +--- /dev/null ++++ b/drivers/spi/spi-sun6i.c +@@ -0,0 +1,483 @@ ++/* ++ * Copyright (C) 2012 - 2014 Allwinner Tech ++ * Pan Nan ++ * ++ * Copyright (C) 2014 Maxime Ripard ++ * Maxime Ripard ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#define SUN6I_FIFO_DEPTH 128 ++ ++#define SUN6I_GBL_CTL_REG 0x04 ++#define SUN6I_GBL_CTL_BUS_ENABLE BIT(0) ++#define SUN6I_GBL_CTL_MASTER BIT(1) ++#define SUN6I_GBL_CTL_TP BIT(7) ++#define SUN6I_GBL_CTL_RST BIT(31) ++ ++#define SUN6I_TFR_CTL_REG 0x08 ++#define SUN6I_TFR_CTL_CPHA BIT(0) ++#define SUN6I_TFR_CTL_CPOL BIT(1) ++#define SUN6I_TFR_CTL_SPOL BIT(2) ++#define SUN6I_TFR_CTL_CS_MASK 0x3 ++#define SUN6I_TFR_CTL_CS(cs) (((cs) & SUN6I_TFR_CTL_CS_MASK) << 4) ++#define SUN6I_TFR_CTL_CS_MANUAL BIT(6) ++#define SUN6I_TFR_CTL_CS_LEVEL BIT(7) ++#define SUN6I_TFR_CTL_DHB BIT(8) ++#define SUN6I_TFR_CTL_FBS BIT(12) ++#define SUN6I_TFR_CTL_XCH BIT(31) ++ ++#define SUN6I_INT_CTL_REG 0x10 ++#define SUN6I_INT_CTL_RF_OVF BIT(8) ++#define SUN6I_INT_CTL_TC BIT(12) ++ ++#define SUN6I_INT_STA_REG 0x14 ++ ++#define SUN6I_FIFO_CTL_REG 0x18 ++#define SUN6I_FIFO_CTL_RF_RST BIT(15) ++#define SUN6I_FIFO_CTL_TF_RST BIT(31) ++ ++#define SUN6I_FIFO_STA_REG 0x1c ++#define SUN6I_FIFO_STA_RF_CNT_MASK 0x7f ++#define SUN6I_FIFO_STA_RF_CNT_BITS 0 ++#define SUN6I_FIFO_STA_TF_CNT_MASK 0x7f ++#define SUN6I_FIFO_STA_TF_CNT_BITS 16 ++ ++#define SUN6I_CLK_CTL_REG 0x24 ++#define SUN6I_CLK_CTL_CDR2_MASK 0xff ++#define SUN6I_CLK_CTL_CDR2(div) (((div) & SUN6I_CLK_CTL_CDR2_MASK) << 0) ++#define SUN6I_CLK_CTL_CDR1_MASK 0xf ++#define SUN6I_CLK_CTL_CDR1(div) (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8) ++#define SUN6I_CLK_CTL_DRS BIT(12) ++ ++#define SUN6I_BURST_CNT_REG 0x30 ++#define SUN6I_BURST_CNT(cnt) ((cnt) & 0xffffff) ++ ++#define SUN6I_XMIT_CNT_REG 0x34 ++#define SUN6I_XMIT_CNT(cnt) ((cnt) & 0xffffff) ++ ++#define SUN6I_BURST_CTL_CNT_REG 0x38 ++#define SUN6I_BURST_CTL_CNT_STC(cnt) ((cnt) & 0xffffff) ++ ++#define SUN6I_TXDATA_REG 0x200 ++#define SUN6I_RXDATA_REG 0x300 ++ ++struct sun6i_spi { ++ struct spi_master *master; ++ void __iomem *base_addr; ++ struct clk *hclk; ++ struct clk *mclk; ++ struct reset_control *rstc; ++ ++ struct completion done; ++ ++ const u8 *tx_buf; ++ u8 *rx_buf; ++ int len; ++}; ++ ++static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg) ++{ ++ return readl(sspi->base_addr + reg); ++} ++ ++static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value) ++{ ++ writel(value, sspi->base_addr + reg); ++} ++ ++static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len) ++{ ++ u32 reg, cnt; ++ u8 byte; ++ ++ /* See how much data is available */ ++ reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG); ++ reg &= SUN6I_FIFO_STA_RF_CNT_MASK; ++ cnt = reg >> SUN6I_FIFO_STA_RF_CNT_BITS; ++ ++ if (len > cnt) ++ len = cnt; ++ ++ while (len--) { ++ byte = readb(sspi->base_addr + SUN6I_RXDATA_REG); ++ if (sspi->rx_buf) ++ *sspi->rx_buf++ = byte; ++ } ++} ++ ++static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi, int len) ++{ ++ u8 byte; ++ ++ if (len > sspi->len) ++ len = sspi->len; ++ ++ while (len--) { ++ byte = sspi->tx_buf ? *sspi->tx_buf++ : 0; ++ writeb(byte, sspi->base_addr + SUN6I_TXDATA_REG); ++ sspi->len--; ++ } ++} ++ ++static void sun6i_spi_set_cs(struct spi_device *spi, bool enable) ++{ ++ struct sun6i_spi *sspi = spi_master_get_devdata(spi->master); ++ u32 reg; ++ ++ reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); ++ reg &= ~SUN6I_TFR_CTL_CS_MASK; ++ reg |= SUN6I_TFR_CTL_CS(spi->chip_select); ++ ++ if (enable) ++ reg |= SUN6I_TFR_CTL_CS_LEVEL; ++ else ++ reg &= ~SUN6I_TFR_CTL_CS_LEVEL; ++ ++ sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg); ++} ++ ++ ++static int sun6i_spi_transfer_one(struct spi_master *master, ++ struct spi_device *spi, ++ struct spi_transfer *tfr) ++{ ++ struct sun6i_spi *sspi = spi_master_get_devdata(master); ++ unsigned int mclk_rate, div, timeout; ++ unsigned int tx_len = 0; ++ int ret = 0; ++ u32 reg; ++ ++ /* We don't support transfer larger than the FIFO */ ++ if (tfr->len > SUN6I_FIFO_DEPTH) ++ return -EINVAL; ++ ++ reinit_completion(&sspi->done); ++ sspi->tx_buf = tfr->tx_buf; ++ sspi->rx_buf = tfr->rx_buf; ++ sspi->len = tfr->len; ++ ++ /* Clear pending interrupts */ ++ sun6i_spi_write(sspi, SUN6I_INT_STA_REG, ~0); ++ ++ /* Reset FIFO */ ++ sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG, ++ SUN6I_FIFO_CTL_RF_RST | SUN6I_FIFO_CTL_TF_RST); ++ ++ /* ++ * Setup the transfer control register: Chip Select, ++ * polarities, etc. ++ */ ++ reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); ++ ++ if (spi->mode & SPI_CPOL) ++ reg |= SUN6I_TFR_CTL_CPOL; ++ else ++ reg &= ~SUN6I_TFR_CTL_CPOL; ++ ++ if (spi->mode & SPI_CPHA) ++ reg |= SUN6I_TFR_CTL_CPHA; ++ else ++ reg &= ~SUN6I_TFR_CTL_CPHA; ++ ++ if (spi->mode & SPI_LSB_FIRST) ++ reg |= SUN6I_TFR_CTL_FBS; ++ else ++ reg &= ~SUN6I_TFR_CTL_FBS; ++ ++ /* ++ * If it's a TX only transfer, we don't want to fill the RX ++ * FIFO with bogus data ++ */ ++ if (sspi->rx_buf) ++ reg &= ~SUN6I_TFR_CTL_DHB; ++ else ++ reg |= SUN6I_TFR_CTL_DHB; ++ ++ /* We want to control the chip select manually */ ++ reg |= SUN6I_TFR_CTL_CS_MANUAL; ++ ++ sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg); ++ ++ /* Ensure that we have a parent clock fast enough */ ++ mclk_rate = clk_get_rate(sspi->mclk); ++ if (mclk_rate < (2 * spi->max_speed_hz)) { ++ clk_set_rate(sspi->mclk, 2 * spi->max_speed_hz); ++ mclk_rate = clk_get_rate(sspi->mclk); ++ } ++ ++ /* ++ * Setup clock divider. ++ * ++ * We have two choices there. Either we can use the clock ++ * divide rate 1, which is calculated thanks to this formula: ++ * SPI_CLK = MOD_CLK / (2 ^ cdr) ++ * Or we can use CDR2, which is calculated with the formula: ++ * SPI_CLK = MOD_CLK / (2 * (cdr + 1)) ++ * Wether we use the former or the latter is set through the ++ * DRS bit. ++ * ++ * First try CDR2, and if we can't reach the expected ++ * frequency, fall back to CDR1. ++ */ ++ div = mclk_rate / (2 * spi->max_speed_hz); ++ if (div <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) { ++ if (div > 0) ++ div--; ++ ++ reg = SUN6I_CLK_CTL_CDR2(div) | SUN6I_CLK_CTL_DRS; ++ } else { ++ div = ilog2(mclk_rate) - ilog2(spi->max_speed_hz); ++ reg = SUN6I_CLK_CTL_CDR1(div); ++ } ++ ++ sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg); ++ ++ /* Setup the transfer now... */ ++ if (sspi->tx_buf) ++ tx_len = tfr->len; ++ ++ /* Setup the counters */ ++ sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, SUN6I_BURST_CNT(tfr->len)); ++ sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, SUN6I_XMIT_CNT(tx_len)); ++ sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG, ++ SUN6I_BURST_CTL_CNT_STC(tx_len)); ++ ++ /* Fill the TX FIFO */ ++ sun6i_spi_fill_fifo(sspi, SUN6I_FIFO_DEPTH); ++ ++ /* Enable the interrupts */ ++ sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, SUN6I_INT_CTL_TC); ++ ++ /* Start the transfer */ ++ reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); ++ sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg | SUN6I_TFR_CTL_XCH); ++ ++ timeout = wait_for_completion_timeout(&sspi->done, ++ msecs_to_jiffies(1000)); ++ if (!timeout) { ++ ret = -ETIMEDOUT; ++ goto out; ++ } ++ ++ sun6i_spi_drain_fifo(sspi, SUN6I_FIFO_DEPTH); ++ ++out: ++ sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0); ++ ++ return ret; ++} ++ ++static irqreturn_t sun6i_spi_handler(int irq, void *dev_id) ++{ ++ struct sun6i_spi *sspi = dev_id; ++ u32 status = sun6i_spi_read(sspi, SUN6I_INT_STA_REG); ++ ++ /* Transfer complete */ ++ if (status & SUN6I_INT_CTL_TC) { ++ sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC); ++ complete(&sspi->done); ++ return IRQ_HANDLED; ++ } ++ ++ return IRQ_NONE; ++} ++ ++static int sun6i_spi_runtime_resume(struct device *dev) ++{ ++ struct spi_master *master = dev_get_drvdata(dev); ++ struct sun6i_spi *sspi = spi_master_get_devdata(master); ++ int ret; ++ ++ ret = clk_prepare_enable(sspi->hclk); ++ if (ret) { ++ dev_err(dev, "Couldn't enable AHB clock\n"); ++ goto out; ++ } ++ ++ ret = clk_prepare_enable(sspi->mclk); ++ if (ret) { ++ dev_err(dev, "Couldn't enable module clock\n"); ++ goto err; ++ } ++ ++ ret = reset_control_deassert(sspi->rstc); ++ if (ret) { ++ dev_err(dev, "Couldn't deassert the device from reset\n"); ++ goto err2; ++ } ++ ++ sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG, ++ SUN6I_GBL_CTL_BUS_ENABLE | SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP); ++ ++ return 0; ++ ++err2: ++ clk_disable_unprepare(sspi->mclk); ++err: ++ clk_disable_unprepare(sspi->hclk); ++out: ++ return ret; ++} ++ ++static int sun6i_spi_runtime_suspend(struct device *dev) ++{ ++ struct spi_master *master = dev_get_drvdata(dev); ++ struct sun6i_spi *sspi = spi_master_get_devdata(master); ++ ++ reset_control_assert(sspi->rstc); ++ clk_disable_unprepare(sspi->mclk); ++ clk_disable_unprepare(sspi->hclk); ++ ++ return 0; ++} ++ ++static int sun6i_spi_probe(struct platform_device *pdev) ++{ ++ struct spi_master *master; ++ struct sun6i_spi *sspi; ++ struct resource *res; ++ int ret = 0, irq; ++ ++ master = spi_alloc_master(&pdev->dev, sizeof(struct sun6i_spi)); ++ if (!master) { ++ dev_err(&pdev->dev, "Unable to allocate SPI Master\n"); ++ return -ENOMEM; ++ } ++ ++ platform_set_drvdata(pdev, master); ++ sspi = spi_master_get_devdata(master); ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ sspi->base_addr = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(sspi->base_addr)) { ++ ret = PTR_ERR(sspi->base_addr); ++ goto err_free_master; ++ } ++ ++ irq = platform_get_irq(pdev, 0); ++ if (irq < 0) { ++ dev_err(&pdev->dev, "No spi IRQ specified\n"); ++ ret = -ENXIO; ++ goto err_free_master; ++ } ++ ++ ret = devm_request_irq(&pdev->dev, irq, sun6i_spi_handler, ++ 0, "sun6i-spi", sspi); ++ if (ret) { ++ dev_err(&pdev->dev, "Cannot request IRQ\n"); ++ goto err_free_master; ++ } ++ ++ sspi->master = master; ++ master->set_cs = sun6i_spi_set_cs; ++ master->transfer_one = sun6i_spi_transfer_one; ++ master->num_chipselect = 4; ++ master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST; ++ master->dev.of_node = pdev->dev.of_node; ++ master->auto_runtime_pm = true; ++ ++ sspi->hclk = devm_clk_get(&pdev->dev, "ahb"); ++ if (IS_ERR(sspi->hclk)) { ++ dev_err(&pdev->dev, "Unable to acquire AHB clock\n"); ++ ret = PTR_ERR(sspi->hclk); ++ goto err_free_master; ++ } ++ ++ sspi->mclk = devm_clk_get(&pdev->dev, "mod"); ++ if (IS_ERR(sspi->mclk)) { ++ dev_err(&pdev->dev, "Unable to acquire module clock\n"); ++ ret = PTR_ERR(sspi->mclk); ++ goto err_free_master; ++ } ++ ++ init_completion(&sspi->done); ++ ++ sspi->rstc = devm_reset_control_get(&pdev->dev, NULL); ++ if (IS_ERR(sspi->rstc)) { ++ dev_err(&pdev->dev, "Couldn't get reset controller\n"); ++ ret = PTR_ERR(sspi->rstc); ++ goto err_free_master; ++ } ++ ++ /* ++ * This wake-up/shutdown pattern is to be able to have the ++ * device woken up, even if runtime_pm is disabled ++ */ ++ ret = sun6i_spi_runtime_resume(&pdev->dev); ++ if (ret) { ++ dev_err(&pdev->dev, "Couldn't resume the device\n"); ++ goto err_free_master; ++ } ++ ++ pm_runtime_set_active(&pdev->dev); ++ pm_runtime_enable(&pdev->dev); ++ pm_runtime_idle(&pdev->dev); ++ ++ ret = devm_spi_register_master(&pdev->dev, master); ++ if (ret) { ++ dev_err(&pdev->dev, "cannot register SPI master\n"); ++ goto err_pm_disable; ++ } ++ ++ return 0; ++ ++err_pm_disable: ++ pm_runtime_disable(&pdev->dev); ++ sun6i_spi_runtime_suspend(&pdev->dev); ++err_free_master: ++ spi_master_put(master); ++ return ret; ++} ++ ++static int sun6i_spi_remove(struct platform_device *pdev) ++{ ++ pm_runtime_disable(&pdev->dev); ++ ++ return 0; ++} ++ ++static const struct of_device_id sun6i_spi_match[] = { ++ { .compatible = "allwinner,sun6i-a31-spi", }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, sun6i_spi_match); ++ ++static const struct dev_pm_ops sun6i_spi_pm_ops = { ++ .runtime_resume = sun6i_spi_runtime_resume, ++ .runtime_suspend = sun6i_spi_runtime_suspend, ++}; ++ ++static struct platform_driver sun6i_spi_driver = { ++ .probe = sun6i_spi_probe, ++ .remove = sun6i_spi_remove, ++ .driver = { ++ .name = "sun6i-spi", ++ .owner = THIS_MODULE, ++ .of_match_table = sun6i_spi_match, ++ .pm = &sun6i_spi_pm_ops, ++ }, ++}; ++module_platform_driver(sun6i_spi_driver); ++ ++MODULE_AUTHOR("Pan Nan "); ++MODULE_AUTHOR("Maxime Ripard "); ++MODULE_DESCRIPTION("Allwinner A31 SPI controller driver"); ++MODULE_LICENSE("GPL"); diff --git a/debian/patches/features/arm/0002-spi-sun6i-Fix-define-for-SUN6I_TFR_CTL_CS_MASK.patch b/debian/patches/features/arm/0002-spi-sun6i-Fix-define-for-SUN6I_TFR_CTL_CS_MASK.patch new file mode 100644 index 000000000..77cbfa9a4 --- /dev/null +++ b/debian/patches/features/arm/0002-spi-sun6i-Fix-define-for-SUN6I_TFR_CTL_CS_MASK.patch @@ -0,0 +1,30 @@ +From: Axel Lin +Date: Thu, 13 Feb 2014 10:18:15 +0800 +Subject: [2/3] spi: sun6i: Fix define for SUN6I_TFR_CTL_CS_MASK +Origin: https://git.kernel.org/linus/d31ad46f58e89fdb9f5b902aa7cc29689e123dde + +Current code in sun6i_spi_set_cs() actually clears CPHA and CPOL bits which is +obvious wrong. The define for SUN6I_TFR_CTL_CS_MASK is wrong. Fix it. + +Signed-off-by: Axel Lin +Acked-by: Maxime Ripard +Signed-off-by: Mark Brown +--- + drivers/spi/spi-sun6i.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/spi/spi-sun6i.c b/drivers/spi/spi-sun6i.c +index 94d38d0..4b9ec08 100644 +--- a/drivers/spi/spi-sun6i.c ++++ b/drivers/spi/spi-sun6i.c +@@ -36,8 +36,8 @@ + #define SUN6I_TFR_CTL_CPHA BIT(0) + #define SUN6I_TFR_CTL_CPOL BIT(1) + #define SUN6I_TFR_CTL_SPOL BIT(2) +-#define SUN6I_TFR_CTL_CS_MASK 0x3 +-#define SUN6I_TFR_CTL_CS(cs) (((cs) & SUN6I_TFR_CTL_CS_MASK) << 4) ++#define SUN6I_TFR_CTL_CS_MASK 0x30 ++#define SUN6I_TFR_CTL_CS(cs) (((cs) << 4) & SUN6I_TFR_CTL_CS_MASK) + #define SUN6I_TFR_CTL_CS_MANUAL BIT(6) + #define SUN6I_TFR_CTL_CS_LEVEL BIT(7) + #define SUN6I_TFR_CTL_DHB BIT(8) diff --git a/debian/patches/features/arm/0003-spi-sun6i-Set-bits_per_word_mask-to-only-support-8-b.patch b/debian/patches/features/arm/0003-spi-sun6i-Set-bits_per_word_mask-to-only-support-8-b.patch new file mode 100644 index 000000000..8117b041f --- /dev/null +++ b/debian/patches/features/arm/0003-spi-sun6i-Set-bits_per_word_mask-to-only-support-8-b.patch @@ -0,0 +1,29 @@ +From: Axel Lin +Date: Sun, 2 Mar 2014 22:25:58 +0800 +Subject: [3/3] spi: sun6i: Set bits_per_word_mask to only support 8 bits word + length +Origin: https://git.kernel.org/linus/743a46b89a59abcc6566d9d90b1f28bfa666702e + +This controller only supports 8 bits word length. +Set bits_per_word_mask so spi core will reject transfers that attempt to use +an unsupported bits_per_word value. + +Signed-off-by: Axel Lin +Acked-by: Maxime Ripard +Signed-off-by: Mark Brown +--- + drivers/spi/spi-sun6i.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/spi/spi-sun6i.c b/drivers/spi/spi-sun6i.c +index 4b9ec08..b3e3498 100644 +--- a/drivers/spi/spi-sun6i.c ++++ b/drivers/spi/spi-sun6i.c +@@ -391,6 +391,7 @@ static int sun6i_spi_probe(struct platform_device *pdev) + master->transfer_one = sun6i_spi_transfer_one; + master->num_chipselect = 4; + master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST; ++ master->bits_per_word_mask = SPI_BPW_MASK(8); + master->dev.of_node = pdev->dev.of_node; + master->auto_runtime_pm = true; + diff --git a/debian/patches/features/arm/ARM-dt-sun4i-Add-A10-SPI-controller-nodes.patch b/debian/patches/features/arm/ARM-dt-sun4i-Add-A10-SPI-controller-nodes.patch new file mode 100644 index 000000000..56f723036 --- /dev/null +++ b/debian/patches/features/arm/ARM-dt-sun4i-Add-A10-SPI-controller-nodes.patch @@ -0,0 +1,72 @@ +From: Maxime Ripard +Date: Sat, 22 Feb 2014 22:35:55 +0100 +Subject: ARM: dt: sun4i: Add A10 SPI controller nodes +Origin: https://git.kernel.org/linus/65918e26069a1aa3f693360a0d77bd41cd1b680b + +The A10 has 4 SPI controllers that are now supported. Add them in the DT. + +Signed-off-by: Maxime Ripard +--- + arch/arm/boot/dts/sun4i-a10.dtsi | 44 ++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 44 insertions(+) + +--- a/arch/arm/boot/dts/sun4i-a10.dtsi ++++ b/arch/arm/boot/dts/sun4i-a10.dtsi +@@ -320,6 +320,28 @@ + #size-cells = <1>; + ranges; + ++ spi0: spi@01c05000 { ++ compatible = "allwinner,sun4i-a10-spi"; ++ reg = <0x01c05000 0x1000>; ++ interrupts = <10>; ++ clocks = <&ahb_gates 20>, <&spi0_clk>; ++ clock-names = "ahb", "mod"; ++ status = "disabled"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ spi1: spi@01c06000 { ++ compatible = "allwinner,sun4i-a10-spi"; ++ reg = <0x01c06000 0x1000>; ++ interrupts = <11>; ++ clocks = <&ahb_gates 21>, <&spi1_clk>; ++ clock-names = "ahb", "mod"; ++ status = "disabled"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ + emac: ethernet@01c0b000 { + compatible = "allwinner,sun4i-a10-emac"; + reg = <0x01c0b000 0x1000>; +@@ -344,6 +366,28 @@ + status = "disabled"; + }; + ++ spi2: spi@01c17000 { ++ compatible = "allwinner,sun4i-a10-spi"; ++ reg = <0x01c17000 0x1000>; ++ interrupts = <12>; ++ clocks = <&ahb_gates 22>, <&spi2_clk>; ++ clock-names = "ahb", "mod"; ++ status = "disabled"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ spi3: spi@01c1f000 { ++ compatible = "allwinner,sun4i-a10-spi"; ++ reg = <0x01c1f000 0x1000>; ++ interrupts = <50>; ++ clocks = <&ahb_gates 23>, <&spi3_clk>; ++ clock-names = "ahb", "mod"; ++ status = "disabled"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ + intc: interrupt-controller@01c20400 { + compatible = "allwinner,sun4i-ic"; + reg = <0x01c20400 0x400>; diff --git a/debian/patches/features/arm/ARM-sun4i-dt-Add-USB-host-bindings.patch b/debian/patches/features/arm/ARM-sun4i-dt-Add-USB-host-bindings.patch new file mode 100644 index 000000000..9c24a0258 --- /dev/null +++ b/debian/patches/features/arm/ARM-sun4i-dt-Add-USB-host-bindings.patch @@ -0,0 +1,82 @@ +From: Roman Byshko +Date: Sat, 1 Mar 2014 20:26:23 +0100 +Subject: ARM: sun4i: dt: Add USB host bindings +Origin: https://git.kernel.org/linus/6ab1ce244be33115b4fbffd10684b734dc14699d + +Add nodes for the usb-phy and ehci- and ohci-usb-host controllers. + +Signed-off-by: Roman Byshko +Signed-off-by: Hans de Goede +Signed-off-by: Maxime Ripard +--- + arch/arm/boot/dts/sun4i-a10.dtsi | 52 ++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 52 insertions(+) + +--- a/arch/arm/boot/dts/sun4i-a10.dtsi ++++ b/arch/arm/boot/dts/sun4i-a10.dtsi +@@ -366,6 +366,38 @@ + status = "disabled"; + }; + ++ usbphy: phy@01c13400 { ++ #phy-cells = <1>; ++ compatible = "allwinner,sun4i-a10-usb-phy"; ++ reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>; ++ reg-names = "phy_ctrl", "pmu1", "pmu2"; ++ clocks = <&usb_clk 8>; ++ clock-names = "usb_phy"; ++ resets = <&usb_clk 1>, <&usb_clk 2>; ++ reset-names = "usb1_reset", "usb2_reset"; ++ status = "disabled"; ++ }; ++ ++ ehci0: usb@01c14000 { ++ compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; ++ reg = <0x01c14000 0x100>; ++ interrupts = <39>; ++ clocks = <&ahb_gates 1>; ++ phys = <&usbphy 1>; ++ phy-names = "usb"; ++ status = "disabled"; ++ }; ++ ++ ohci0: usb@01c14400 { ++ compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; ++ reg = <0x01c14400 0x100>; ++ interrupts = <64>; ++ clocks = <&usb_clk 6>, <&ahb_gates 2>; ++ phys = <&usbphy 1>; ++ phy-names = "usb"; ++ status = "disabled"; ++ }; ++ + spi2: spi@01c17000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c17000 0x1000>; +@@ -377,6 +409,26 @@ + #size-cells = <0>; + }; + ++ ehci1: usb@01c1c000 { ++ compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; ++ reg = <0x01c1c000 0x100>; ++ interrupts = <40>; ++ clocks = <&ahb_gates 3>; ++ phys = <&usbphy 2>; ++ phy-names = "usb"; ++ status = "disabled"; ++ }; ++ ++ ohci1: usb@01c1c400 { ++ compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; ++ reg = <0x01c1c400 0x100>; ++ interrupts = <65>; ++ clocks = <&usb_clk 7>, <&ahb_gates 4>; ++ phys = <&usbphy 2>; ++ phy-names = "usb"; ++ status = "disabled"; ++ }; ++ + spi3: spi@01c1f000 { + compatible = "allwinner,sun4i-a10-spi"; + reg = <0x01c1f000 0x1000>; diff --git a/debian/patches/features/arm/PHY-sunxi-Add-driver-for-sunxi-usb-phy.patch b/debian/patches/features/arm/PHY-sunxi-Add-driver-for-sunxi-usb-phy.patch new file mode 100644 index 000000000..83600c451 --- /dev/null +++ b/debian/patches/features/arm/PHY-sunxi-Add-driver-for-sunxi-usb-phy.patch @@ -0,0 +1,412 @@ +From: Hans de Goede +Date: Sat, 1 Mar 2014 18:09:26 +0100 +Subject: PHY: sunxi: Add driver for sunxi usb phy +Origin: https://git.kernel.org/linus/ba4bdc9e1dc01300490e4f5315b0ac8576bd4c7a + +The Allwinner A1x / A2x SoCs have 2 or 3 usb phys which are all accessed +through a single set of registers. Besides this there are also some other +phy related bits which need poking, which are per phy, but shared between the +ohci and ehci controllers, so these are also controlled from this new phy +driver. + +Signed-off-by: Hans de Goede +Acked-by: Maxime Ripard +Signed-off-by: Kishon Vijay Abraham I +[bwh: Backported to 3.14: adjust context] +--- + .../devicetree/bindings/phy/sun4i-usb-phy.txt | 26 ++ + drivers/phy/Kconfig | 11 + + drivers/phy/Makefile | 1 + + drivers/phy/phy-sun4i-usb.c | 331 +++++++++++++++++++++ + 4 files changed, 369 insertions(+) + create mode 100644 Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt + create mode 100644 drivers/phy/phy-sun4i-usb.c + +--- /dev/null ++++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt +@@ -0,0 +1,26 @@ ++Allwinner sun4i USB PHY ++----------------------- ++ ++Required properties: ++- compatible : should be one of "allwinner,sun4i-a10-usb-phy", ++ "allwinner,sun5i-a13-usb-phy" or "allwinner,sun7i-a20-usb-phy" ++- reg : a list of offset + length pairs ++- reg-names : "phy_ctrl", "pmu1" and for sun4i or sun7i "pmu2" ++- #phy-cells : from the generic phy bindings, must be 1 ++- clocks : phandle + clock specifier for the phy clock ++- clock-names : "usb_phy" ++- resets : a list of phandle + reset specifier pairs ++- reset-names : "usb0_reset", "usb1_reset" and for sun4i or sun7i "usb2_reset" ++ ++Example: ++ usbphy: phy@0x01c13400 { ++ #phy-cells = <1>; ++ compatible = "allwinner,sun4i-a10-usb-phy"; ++ /* phy base regs, phy1 pmu reg, phy2 pmu reg */ ++ reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>; ++ reg-names = "phy_ctrl", "pmu1", "pmu2"; ++ clocks = <&usb_clk 8>; ++ clock-names = "usb_phy"; ++ resets = <&usb_clk 1>, <&usb_clk 2>; ++ reset-names = "usb1_reset", "usb2_reset"; ++ }; +--- a/drivers/phy/Kconfig ++++ b/drivers/phy/Kconfig +@@ -65,4 +65,15 @@ config BCM_KONA_USB2_PHY + help + Enable this to support the Broadcom Kona USB 2.0 PHY. + ++config PHY_SUN4I_USB ++ tristate "Allwinner sunxi SoC USB PHY driver" ++ depends on ARCH_SUNXI && HAS_IOMEM && OF ++ select GENERIC_PHY ++ help ++ Enable this to support the transceiver that is part of Allwinner ++ sunxi SoCs. ++ ++ This driver controls the entire USB PHY block, both the USB OTG ++ parts, as well as the 2 regular USB 2 host PHYs. ++ + endmenu +--- a/drivers/phy/Makefile ++++ b/drivers/phy/Makefile +@@ -9,3 +9,4 @@ obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += p + obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o + obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o + obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o ++obj-$(CONFIG_PHY_SUN4I_USB) += phy-sun4i-usb.o +--- /dev/null ++++ b/drivers/phy/phy-sun4i-usb.c +@@ -0,0 +1,331 @@ ++/* ++ * Allwinner sun4i USB phy driver ++ * ++ * Copyright (C) 2014 Hans de Goede ++ * ++ * Based on code from ++ * Allwinner Technology Co., Ltd. ++ * ++ * Modelled after: Samsung S5P/EXYNOS SoC series MIPI CSIS/DSIM DPHY driver ++ * Copyright (C) 2013 Samsung Electronics Co., Ltd. ++ * Author: Sylwester Nawrocki ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define REG_ISCR 0x00 ++#define REG_PHYCTL 0x04 ++#define REG_PHYBIST 0x08 ++#define REG_PHYTUNE 0x0c ++ ++#define PHYCTL_DATA BIT(7) ++ ++#define SUNXI_AHB_ICHR8_EN BIT(10) ++#define SUNXI_AHB_INCR4_BURST_EN BIT(9) ++#define SUNXI_AHB_INCRX_ALIGN_EN BIT(8) ++#define SUNXI_ULPI_BYPASS_EN BIT(0) ++ ++/* Common Control Bits for Both PHYs */ ++#define PHY_PLL_BW 0x03 ++#define PHY_RES45_CAL_EN 0x0c ++ ++/* Private Control Bits for Each PHY */ ++#define PHY_TX_AMPLITUDE_TUNE 0x20 ++#define PHY_TX_SLEWRATE_TUNE 0x22 ++#define PHY_VBUSVALID_TH_SEL 0x25 ++#define PHY_PULLUP_RES_SEL 0x27 ++#define PHY_OTG_FUNC_EN 0x28 ++#define PHY_VBUS_DET_EN 0x29 ++#define PHY_DISCON_TH_SEL 0x2a ++ ++#define MAX_PHYS 3 ++ ++struct sun4i_usb_phy_data { ++ struct clk *clk; ++ void __iomem *base; ++ struct mutex mutex; ++ int num_phys; ++ u32 disc_thresh; ++ struct sun4i_usb_phy { ++ struct phy *phy; ++ void __iomem *pmu; ++ struct regulator *vbus; ++ struct reset_control *reset; ++ int index; ++ } phys[MAX_PHYS]; ++}; ++ ++#define to_sun4i_usb_phy_data(phy) \ ++ container_of((phy), struct sun4i_usb_phy_data, phys[(phy)->index]) ++ ++static void sun4i_usb_phy_write(struct sun4i_usb_phy *phy, u32 addr, u32 data, ++ int len) ++{ ++ struct sun4i_usb_phy_data *phy_data = to_sun4i_usb_phy_data(phy); ++ u32 temp, usbc_bit = BIT(phy->index * 2); ++ int i; ++ ++ mutex_lock(&phy_data->mutex); ++ ++ for (i = 0; i < len; i++) { ++ temp = readl(phy_data->base + REG_PHYCTL); ++ ++ /* clear the address portion */ ++ temp &= ~(0xff << 8); ++ ++ /* set the address */ ++ temp |= ((addr + i) << 8); ++ writel(temp, phy_data->base + REG_PHYCTL); ++ ++ /* set the data bit and clear usbc bit*/ ++ temp = readb(phy_data->base + REG_PHYCTL); ++ if (data & 0x1) ++ temp |= PHYCTL_DATA; ++ else ++ temp &= ~PHYCTL_DATA; ++ temp &= ~usbc_bit; ++ writeb(temp, phy_data->base + REG_PHYCTL); ++ ++ /* pulse usbc_bit */ ++ temp = readb(phy_data->base + REG_PHYCTL); ++ temp |= usbc_bit; ++ writeb(temp, phy_data->base + REG_PHYCTL); ++ ++ temp = readb(phy_data->base + REG_PHYCTL); ++ temp &= ~usbc_bit; ++ writeb(temp, phy_data->base + REG_PHYCTL); ++ ++ data >>= 1; ++ } ++ mutex_unlock(&phy_data->mutex); ++} ++ ++static void sun4i_usb_phy_passby(struct sun4i_usb_phy *phy, int enable) ++{ ++ u32 bits, reg_value; ++ ++ if (!phy->pmu) ++ return; ++ ++ bits = SUNXI_AHB_ICHR8_EN | SUNXI_AHB_INCR4_BURST_EN | ++ SUNXI_AHB_INCRX_ALIGN_EN | SUNXI_ULPI_BYPASS_EN; ++ ++ reg_value = readl(phy->pmu); ++ ++ if (enable) ++ reg_value |= bits; ++ else ++ reg_value &= ~bits; ++ ++ writel(reg_value, phy->pmu); ++} ++ ++static int sun4i_usb_phy_init(struct phy *_phy) ++{ ++ struct sun4i_usb_phy *phy = phy_get_drvdata(_phy); ++ struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy); ++ int ret; ++ ++ ret = clk_prepare_enable(data->clk); ++ if (ret) ++ return ret; ++ ++ ret = reset_control_deassert(phy->reset); ++ if (ret) { ++ clk_disable_unprepare(data->clk); ++ return ret; ++ } ++ ++ /* Adjust PHY's magnitude and rate */ ++ sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5); ++ ++ /* Disconnect threshold adjustment */ ++ sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL, data->disc_thresh, 2); ++ ++ sun4i_usb_phy_passby(phy, 1); ++ ++ return 0; ++} ++ ++static int sun4i_usb_phy_exit(struct phy *_phy) ++{ ++ struct sun4i_usb_phy *phy = phy_get_drvdata(_phy); ++ struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy); ++ ++ sun4i_usb_phy_passby(phy, 0); ++ reset_control_assert(phy->reset); ++ clk_disable_unprepare(data->clk); ++ ++ return 0; ++} ++ ++static int sun4i_usb_phy_power_on(struct phy *_phy) ++{ ++ struct sun4i_usb_phy *phy = phy_get_drvdata(_phy); ++ int ret = 0; ++ ++ if (phy->vbus) ++ ret = regulator_enable(phy->vbus); ++ ++ return ret; ++} ++ ++static int sun4i_usb_phy_power_off(struct phy *_phy) ++{ ++ struct sun4i_usb_phy *phy = phy_get_drvdata(_phy); ++ ++ if (phy->vbus) ++ regulator_disable(phy->vbus); ++ ++ return 0; ++} ++ ++static struct phy_ops sun4i_usb_phy_ops = { ++ .init = sun4i_usb_phy_init, ++ .exit = sun4i_usb_phy_exit, ++ .power_on = sun4i_usb_phy_power_on, ++ .power_off = sun4i_usb_phy_power_off, ++ .owner = THIS_MODULE, ++}; ++ ++static struct phy *sun4i_usb_phy_xlate(struct device *dev, ++ struct of_phandle_args *args) ++{ ++ struct sun4i_usb_phy_data *data = dev_get_drvdata(dev); ++ ++ if (WARN_ON(args->args[0] == 0 || args->args[0] >= data->num_phys)) ++ return ERR_PTR(-ENODEV); ++ ++ return data->phys[args->args[0]].phy; ++} ++ ++static int sun4i_usb_phy_probe(struct platform_device *pdev) ++{ ++ struct sun4i_usb_phy_data *data; ++ struct device *dev = &pdev->dev; ++ struct device_node *np = dev->of_node; ++ void __iomem *pmu = NULL; ++ struct phy_provider *phy_provider; ++ struct reset_control *reset; ++ struct regulator *vbus; ++ struct resource *res; ++ struct phy *phy; ++ char name[16]; ++ int i; ++ ++ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); ++ if (!data) ++ return -ENOMEM; ++ ++ mutex_init(&data->mutex); ++ ++ if (of_device_is_compatible(np, "allwinner,sun5i-a13-usb-phy")) ++ data->num_phys = 2; ++ else ++ data->num_phys = 3; ++ ++ if (of_device_is_compatible(np, "allwinner,sun4i-a10-usb-phy")) ++ data->disc_thresh = 3; ++ else ++ data->disc_thresh = 2; ++ ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy_ctrl"); ++ data->base = devm_ioremap_resource(dev, res); ++ if (IS_ERR(data->base)) ++ return PTR_ERR(data->base); ++ ++ data->clk = devm_clk_get(dev, "usb_phy"); ++ if (IS_ERR(data->clk)) { ++ dev_err(dev, "could not get usb_phy clock\n"); ++ return PTR_ERR(data->clk); ++ } ++ ++ /* Skip 0, 0 is the phy for otg which is not yet supported. */ ++ for (i = 1; i < data->num_phys; i++) { ++ snprintf(name, sizeof(name), "usb%d_vbus", i); ++ vbus = devm_regulator_get_optional(dev, name); ++ if (IS_ERR(vbus)) { ++ if (PTR_ERR(vbus) == -EPROBE_DEFER) ++ return -EPROBE_DEFER; ++ vbus = NULL; ++ } ++ ++ snprintf(name, sizeof(name), "usb%d_reset", i); ++ reset = devm_reset_control_get(dev, name); ++ if (IS_ERR(reset)) { ++ dev_err(dev, "failed to get reset %s\n", name); ++ return PTR_ERR(reset); ++ } ++ ++ if (i) { /* No pmu for usbc0 */ ++ snprintf(name, sizeof(name), "pmu%d", i); ++ res = platform_get_resource_byname(pdev, ++ IORESOURCE_MEM, name); ++ pmu = devm_ioremap_resource(dev, res); ++ if (IS_ERR(pmu)) ++ return PTR_ERR(pmu); ++ } ++ ++ phy = devm_phy_create(dev, &sun4i_usb_phy_ops, NULL); ++ if (IS_ERR(phy)) { ++ dev_err(dev, "failed to create PHY %d\n", i); ++ return PTR_ERR(phy); ++ } ++ ++ data->phys[i].phy = phy; ++ data->phys[i].pmu = pmu; ++ data->phys[i].vbus = vbus; ++ data->phys[i].reset = reset; ++ data->phys[i].index = i; ++ phy_set_drvdata(phy, &data->phys[i]); ++ } ++ ++ dev_set_drvdata(dev, data); ++ phy_provider = devm_of_phy_provider_register(dev, sun4i_usb_phy_xlate); ++ if (IS_ERR(phy_provider)) ++ return PTR_ERR(phy_provider); ++ ++ return 0; ++} ++ ++static const struct of_device_id sun4i_usb_phy_of_match[] = { ++ { .compatible = "allwinner,sun4i-a10-usb-phy" }, ++ { .compatible = "allwinner,sun5i-a13-usb-phy" }, ++ { .compatible = "allwinner,sun7i-a20-usb-phy" }, ++ { }, ++}; ++MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match); ++ ++static struct platform_driver sun4i_usb_phy_driver = { ++ .probe = sun4i_usb_phy_probe, ++ .driver = { ++ .of_match_table = sun4i_usb_phy_of_match, ++ .name = "sun4i-usb-phy", ++ .owner = THIS_MODULE, ++ } ++}; ++module_platform_driver(sun4i_usb_phy_driver); ++ ++MODULE_DESCRIPTION("Allwinner sun4i USB phy driver"); ++MODULE_AUTHOR("Hans de Goede "); ++MODULE_LICENSE("GPL v2"); diff --git a/debian/patches/series b/debian/patches/series index ab0eb16d0..24e2a8f70 100644 --- a/debian/patches/series +++ b/debian/patches/series @@ -74,3 +74,9 @@ bugfix/arm/bfa-Replace-large-udelay-with-mdelay.patch features/all/support-Thinkpad-X1-Carbon-2nd-generation-s-adaptive.patch features/all/save-and-restore-adaptive-keyboard-mode-for-suspend-.patch features/all/ARM-sunxi-ahci-and-gmac.patch +features/arm/0001-spi-sunxi-Add-Allwinner-A31-SPI-controller-driver.patch +features/arm/0002-spi-sun6i-Fix-define-for-SUN6I_TFR_CTL_CS_MASK.patch +features/arm/0003-spi-sun6i-Set-bits_per_word_mask-to-only-support-8-b.patch +features/arm/ARM-dt-sun4i-Add-A10-SPI-controller-nodes.patch +features/arm/PHY-sunxi-Add-driver-for-sunxi-usb-phy.patch +features/arm/ARM-sun4i-dt-Add-USB-host-bindings.patch