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sync changed from dists/sid 

svn path=/dists/trunk/linux-2.6/; revision=6239
This commit is contained in:
Martin Michlmayr 2006-03-20 15:35:34 +00:00
parent 004e355d75
commit 79427c100c
19 changed files with 111 additions and 671 deletions
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14
debian/arch/arm/config.footbridge vendored
View File

@ -448,6 +448,7 @@ CONFIG_IDEDISK_MULTI_MODE=y
# IDE chipset support/bugfixes
#
CONFIG_IDE_GENERIC=y
# CONFIG_BLK_DEV_IDEPNP is not set
# CONFIG_IDE_ARM is not set
# CONFIG_IDE_CHIPSETS is not set
# CONFIG_IDEDMA_AUTO is not set
@ -961,6 +962,11 @@ CONFIG_SENSORS_MAX6875=m
# CONFIG_I2C_DEBUG_BUS is not set
# CONFIG_I2C_DEBUG_CHIP is not set
#
# Dallas's 1-wire bus
#
# CONFIG_W1 is not set
#
# Hardware Monitoring support
#
@ -1355,11 +1361,14 @@ CONFIG_CRAMFS=y
# Network File Systems
#
CONFIG_NFS_FS=y
CONFIG_LOCKD=m
CONFIG_ROOT_NFS=y
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y
CONFIG_EXPORTFS=m
CONFIG_NFS_ACL_SUPPORT=y
CONFIG_SUNRPC=y
# CONFIG_RPCSEC_GSS_KRB5 is not set
CONFIG_SUNRPC_GSS=y
CONFIG_RPCSEC_GSS_KRB5=y
# CONFIG_RPCSEC_GSS_SPKM3 is not set
# CONFIG_SMB_FS is not set
# CONFIG_CIFS is not set
@ -1491,6 +1500,7 @@ CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1
#
# Cryptographic options
#
CONFIG_CRYPTO_DES=y
#
# Hardware crypto devices

14
debian/arch/arm/config.ixp4xx vendored
View File

@ -83,6 +83,7 @@ CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y
#
# IXP4xx Platforms
#
CONFIG_MACH_NSLU2=y
# CONFIG_ARCH_AVILA is not set
CONFIG_ARCH_ADI_COYOTE=y
CONFIG_ARCH_IXDP425=y
@ -952,6 +953,11 @@ CONFIG_SENSORS_MAX6875=m
# CONFIG_I2C_DEBUG_BUS is not set
# CONFIG_I2C_DEBUG_CHIP is not set
#
# Dallas's 1-wire bus
#
# CONFIG_W1 is not set
#
# Hardware Monitoring support
#
@ -1126,12 +1132,15 @@ CONFIG_JFFS2_RTIME=y
# Network File Systems
#
CONFIG_NFS_FS=y
CONFIG_LOCKD=m
CONFIG_ROOT_NFS=y
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y
CONFIG_EXPORTFS=m
CONFIG_NFS_ACL_SUPPORT=y
CONFIG_SUNRPC=y
# CONFIG_RPCSEC_GSS_KRB5 is not set
CONFIG_SUNRPC_GSS=y
CONFIG_RPCSEC_GSS_KRB5=y
# CONFIG_RPCSEC_GSS_SPKM3 is not set
# CONFIG_RPCSEC_GSS_SPKM3 is not set
# CONFIG_SMB_FS is not set
# CONFIG_CIFS is not set
@ -1253,6 +1262,7 @@ CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1
#
# Cryptographic options
#
CONFIG_CRYPTO_DES=y
#
# Hardware crypto devices

5
debian/arch/arm/config.nslu2 vendored
View File

@ -917,6 +917,11 @@ CONFIG_RTC_X1205_I2C=m
# CONFIG_I2C_DEBUG_BUS is not set
# CONFIG_I2C_DEBUG_CHIP is not set
#
# Dallas's 1-wire bus
#
# CONFIG_W1 is not set
#
# Hardware Monitoring support
#

12
debian/arch/arm/config.rpc vendored
View File

@ -604,6 +604,11 @@ CONFIG_SENSORS_MAX6875=m
# CONFIG_I2C_DEBUG_BUS is not set
# CONFIG_I2C_DEBUG_CHIP is not set
#
# Dallas's 1-wire bus
#
# CONFIG_W1 is not set
#
# Hardware Monitoring support
#
@ -846,11 +851,13 @@ CONFIG_ADFS_FS=y
# Network File Systems
#
CONFIG_NFS_FS=y
CONFIG_LOCKD=m
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y
CONFIG_EXPORTFS=m
CONFIG_NFS_ACL_SUPPORT=y
CONFIG_SUNRPC=y
# CONFIG_RPCSEC_GSS_KRB5 is not set
CONFIG_SUNRPC_GSS=y
CONFIG_RPCSEC_GSS_KRB5=y
# CONFIG_RPCSEC_GSS_SPKM3 is not set
# CONFIG_SMB_FS is not set
# CONFIG_CIFS is not set
@ -978,6 +985,7 @@ CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1
#
# Cryptographic options
#
CONFIG_CRYPTO_DES=y
#
# Hardware crypto devices

16
debian/arch/arm/config.s3c2410 vendored
View File

@ -714,6 +714,11 @@ CONFIG_SENSORS_MAX6875=m
# CONFIG_I2C_DEBUG_BUS is not set
# CONFIG_I2C_DEBUG_CHIP is not set
#
# Dallas's 1-wire bus
#
# CONFIG_W1 is not set
#
# Hardware Monitoring support
#
@ -912,11 +917,15 @@ CONFIG_CRAMFS=y
#
# Network File Systems
#
CONFIG_LOCKD=m
CONFIG_NFS_FS=y
CONFIG_ROOT_NFS=y
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y
CONFIG_EXPORTFS=m
CONFIG_SUNRPC=m
# CONFIG_RPCSEC_GSS_KRB5 is not set
CONFIG_NFS_ACL_SUPPORT=y
CONFIG_SUNRPC=y
CONFIG_SUNRPC_GSS=y
CONFIG_RPCSEC_GSS_KRB5=y
# CONFIG_RPCSEC_GSS_SPKM3 is not set
# CONFIG_SMB_FS is not set
# CONFIG_CIFS is not set
@ -1040,6 +1049,7 @@ CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1
#
# Cryptographic options
#
CONFIG_CRYPTO_DES=y
#
# Hardware crypto devices

1
debian/arch/armeb/config vendored
View File

@ -23,3 +23,4 @@ CONFIG_MODULE_UNLOAD=y
CONFIG_MODVERSIONS=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
# CONFIG_MACLIST is not set
# CONFIG_AEABI is not set

15
debian/arch/armeb/config.nslu2 vendored
View File

@ -44,9 +44,10 @@ CONFIG_CC_ALIGN_FUNCTIONS=0
CONFIG_CC_ALIGN_LABELS=0
CONFIG_CC_ALIGN_LOOPS=0
CONFIG_CC_ALIGN_JUMPS=0
# CONFIG_SLAB is not set
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=0
# CONFIG_SLOB is not set
CONFIG_SLOB=y
CONFIG_OBSOLETE_INTERMODULE=y
#
@ -141,7 +142,7 @@ CONFIG_CPU_TLB_V4WBI=y
# Processor Features
#
# CONFIG_ARM_THUMB is not set
CONFIG_CPU_BIG_ENDIAN=y
# CONFIG_CPU_BIG_ENDIAN is not set
CONFIG_XSCALE_PMU=y
CONFIG_DMABOUNCE=y
@ -916,6 +917,11 @@ CONFIG_RTC_X1205_I2C=m
# CONFIG_I2C_DEBUG_BUS is not set
# CONFIG_I2C_DEBUG_CHIP is not set
#
# Dallas's 1-wire bus
#
# CONFIG_W1 is not set
#
# Hardware Monitoring support
#
@ -1396,6 +1402,7 @@ CONFIG_MSDOS_PARTITION=y
# CONFIG_SGI_PARTITION is not set
# CONFIG_ULTRIX_PARTITION is not set
# CONFIG_SUN_PARTITION is not set
# CONFIG_KARMA_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
#
@ -1468,10 +1475,10 @@ CONFIG_SECURITY_NETWORK=y
CONFIG_SECURITY_NETWORK_XFRM=y
CONFIG_SECURITY_CAPABILITIES=y
CONFIG_SECURITY_ROOTPLUG=m
CONFIG_SECURITY_SECLVL=y
CONFIG_SECURITY_SECLVL=m
CONFIG_SECURITY_SELINUX=y
CONFIG_SECURITY_SELINUX_BOOTPARAM=y
CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=1
CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=0
CONFIG_SECURITY_SELINUX_DISABLE=y
CONFIG_SECURITY_SELINUX_DEVELOP=y
CONFIG_SECURITY_SELINUX_AVC_STATS=y

2
debian/arch/mips/config.r4k-ip22 vendored
View File

@ -176,7 +176,7 @@ CONFIG_CC_ALIGN_LOOPS=0
CONFIG_CC_ALIGN_JUMPS=0
CONFIG_SLAB=y
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=1
CONFIG_BASE_SMALL=0
# CONFIG_SLOB is not set
#

2
debian/arch/mips/config.r5k-ip32 vendored
View File

@ -177,7 +177,7 @@ CONFIG_CC_ALIGN_LOOPS=0
CONFIG_CC_ALIGN_JUMPS=0
CONFIG_SLAB=y
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=1
CONFIG_BASE_SMALL=0
# CONFIG_SLOB is not set
#

2
debian/arch/mips/config.sb1-bcm91250a vendored
View File

@ -191,7 +191,7 @@ CONFIG_CC_ALIGN_LOOPS=0
CONFIG_CC_ALIGN_JUMPS=0
CONFIG_SLAB=y
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=1
CONFIG_BASE_SMALL=0
# CONFIG_SLOB is not set
#

2
debian/arch/mips/config.sb1a-bcm91480b vendored
View File

@ -190,7 +190,7 @@ CONFIG_CC_ALIGN_LOOPS=0
CONFIG_CC_ALIGN_JUMPS=0
CONFIG_SLAB=y
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=1
CONFIG_BASE_SMALL=0
# CONFIG_SLOB is not set
#

2
debian/arch/mipsel/config.sb1-bcm91250a vendored
View File

@ -191,7 +191,7 @@ CONFIG_CC_ALIGN_LOOPS=0
CONFIG_CC_ALIGN_JUMPS=0
CONFIG_SLAB=y
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=1
CONFIG_BASE_SMALL=0
# CONFIG_SLOB is not set
#

2
debian/arch/mipsel/config.sb1a-bcm91480b vendored
View File

@ -190,7 +190,7 @@ CONFIG_CC_ALIGN_LOOPS=0
CONFIG_CC_ALIGN_JUMPS=0
CONFIG_SLAB=y
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=1
CONFIG_BASE_SMALL=0
# CONFIG_SLOB is not set
#

2
debian/changelog vendored
View File

@ -24,6 +24,8 @@ linux-2.6 (2.6.16-1) UNRELEASED; urgency=low
* [mips] SB1: DUART support (Broadcom).
* [mips] Work around bad code generation for <asm/io.h> (Ralf Baechle).
* [mips] Fix VINO drivers when using a 64-bit kernel (Mikael Nousiainen).
* [arm/armeb] Update configs for 2.6.16.
* [mips/mipsel] Update configs for 2.6.16.
[ dann frazier ]
* [ia64] use yaird on ia64 until #341181 is fixed

345
debian/patches/mips-gettimeofday.patch vendored
View File

@ -1,329 +1,50 @@
# DP: Fix for gettimeofday jumping backwards, then forwards.
# DP: Patch author: Dave Johnson <djohnson+linuxmips@sw.starentnetworks.com>
# DP: Upstream status: merged into linux-mips as 4 separate patches;
# one small fix (defined(CONFIG_SIBYTE_SB1250) ||
# defined(CONFIG_SIBYTE_BCM112X for sb1250_hpt_setup) is missing in git
# DP: Avoid linker error on 1480 because sb1250_hpt_setup() is not defined
# DP: Patch author: Martin Michlmayr <tbm@cyrius.com>
# DP: Upstream status: not the ideal solution, but will work for now. Ralf
# Baechle will hopefully write a better fix, but this is needed for 2.6.16
# to link on 1480.
From: Dave Johnson <djohnson+linuxmips@sw.starentnetworks.com>
[MIPS] Fix for gettimeofday jumping backwards, then forwards.
Date: Thu, 16 Mar 2006 14:11:27 +0000
From: Martin Michlmayr <tbm@cyrius.com>
To: linux-mips@linux-mips.org
Subject: Re: [MIPS] Sibyte: Fix race in sb1250_gettimeoffset().
Below are 2 fixes to do with time jumping around as reported by
gettimeofday(). One is SB1250 specific and one appears generic.
* linux-mips@linux-mips.org <linux-mips@linux-mips.org> [2006-03-16 12:57]:
> Commit: 186326fa1e0360450b927ee5b21fb8db028fe7ba
>
> +void __init swarm_time_init(void)
> +{
> + /* Setup HPT */
> + sb1250_hpt_setup();
> +}
The symptom is revealed by running multile copies (1 per cpu) of a
simple test program that calls gettimeofday() as fast as possible
looking for time to go backwards.
This leads to compiler errors on 1480 because sb1250_hpt_setup() is
not defined. We need something like the patch below (or possibly a
proper fix?):
When a jump is detected the program outputs a few samples before and
after each jump:
value delta
1121781527.912525: 1
1121781527.912525: 0
1121781527.912526: 1
1121781527.912526: 0
1121781527.912527: 1
1121781527.912527: 0
1121781527.912527: 0
1121781527.912527: 0
1121781527.911528: -999
1121781527.911529: 1
1121781527.911530: 1
1121781527.912532: 1002
1121781527.912533: 1
1121781527.912533: 0
1121781527.912534: 1
1121781527.912534: 0
1121781527.912535: 1
1121781527.912536: 1
[MIPS] don't call sb1250_hpt_setup on 1480
value delta
1121781545.635524: 1
1121781545.635524: 0
1121781545.635525: 1
1121781545.635525: 0
1121781545.635526: 1
1121781545.635526: 0
1121781545.635527: 1
1121781545.635527: 0
1121781545.634527: -1000
1121781545.635527: 1000
1121781545.635528: 1
1121781545.635529: 1
1121781545.635529: 0
1121781545.635530: 1
1121781545.635530: 0
1121781545.635531: 1
1121781545.635531: 0
1121781545.635532: 1
1121781545.635533: 1
sb1250_hpt_setup() should not be called on the 1480 board since it's
note defined there, leading to a linking error.
Time jumps backwards 1msec then forwards 1msec a few usec
later. Usually lasts < 2us but I've seen it as long as 5us if the
system is under load.
First problem I found is that sb1250_gettimeoffset() simply reads the
current cpu 0 timer remaining value, however once this counter reaches
0 and the interrupt is raised, it immediately resets and begins to
count down again.
If sb1250_gettimeoffset() is called on cpu 1 via do_gettimeofday()
after the timer has reset but prior to cpu 0 processing the interrupt
and taking write_seqlock() in timer_interrupt() it will return a
full value (or close to it) causing time to jump backwards 1ms. Once
cpu 0 handles the interrupt and timer_interrupt() gets far enough
along it will jump forward 1ms.
To fix this problem I implemented mips_hpt_*() on sb1250 using a spare
timer unrelated to the existing periodic interrupt timers. It runs at
1Mhz with a full 23bit counter. This eliminated the custom
do_gettimeoffset() for sb1250 and allowed use of the generic
fixed_rate_gettimeoffset() using mips_hpt_*() and timerhi/timerlo.
The second problem is that more of timer_interrupt() needs to be
protected by xtime_lock:
* do_timer() expects the arch-specific handler to take the lock as it
modifies jiffies[_64] and xtime.
* writing timerhi/lo in timer_interrupt() will mess up
fixed_rate_gettimeoffset() which reads timerhi/lo.
With both changes do_gettimeofday() works correctly on both cpu 0 and
cpu 1.
Other changes/cleanups:
The existing sb1250 periodic timers were slow by 999ppm (given a
perfect 100mhz reference). The timers need to be loaded with 1 less
than the desired interval not the interval itself.
M_SCD_TIMER_INIT and M_SCD_TIMER_CNT had the wrong field width (should
be 23 bits not 20 bits)
Signed-off-by: Dave Johnson <djohnson+linuxmips@sw.starentnetworks.com>
Signed-off-by: Martin Michlmayr <tbm@cyrius.com>
---
arch/mips/kernel/time.c | 6 +-
arch/mips/sibyte/sb1250/time.c | 77 ++++++++++++++++++++++++++---------
arch/mips/sibyte/swarm/setup.c | 7 +++
include/asm-mips/sibyte/sb1250.h | 2
include/asm-mips/sibyte/sb1250_scd.h | 5 +-
5 files changed, 73 insertions(+), 24 deletions(-)
--- a/arch/mips/kernel/time.c
+++ b/arch/mips/kernel/time.c
@@ -424,6 +424,8 @@ irqreturn_t timer_interrupt(int irq, voi
unsigned long j;
unsigned int count;
+ write_seqlock(&xtime_lock);
+
count = mips_hpt_read();
mips_timer_ack();
@@ -441,7 +443,6 @@ irqreturn_t timer_interrupt(int irq, voi
* CMOS clock accordingly every ~11 minutes. rtc_set_time() has to be
* called as close as possible to 500 ms before the new second starts.
*/
- write_seqlock(&xtime_lock);
if (ntp_synced() &&
xtime.tv_sec > last_rtc_update + 660 &&
(xtime.tv_nsec / 1000) >= 500000 - ((unsigned) TICK_SIZE) / 2 &&
@@ -453,7 +454,6 @@ irqreturn_t timer_interrupt(int irq, voi
last_rtc_update = xtime.tv_sec - 600;
}
}
- write_sequnlock(&xtime_lock);
/*
* If jiffies has overflown in this timer_interrupt, we must
@@ -496,6 +496,8 @@ irqreturn_t timer_interrupt(int irq, voi
}
}
+ write_sequnlock(&xtime_lock);
+
/*
* In UP mode, we call local_timer_interrupt() to do profiling
* and process accouting.
--- a/arch/mips/sibyte/sb1250/time.c
+++ b/arch/mips/sibyte/sb1250/time.c
@@ -47,23 +47,51 @@
#define IMR_IP3_VAL K_INT_MAP_I1
#define IMR_IP4_VAL K_INT_MAP_I2
+#define SB1250_HPT_NUM 3
+#define SB1250_HPT_VALUE M_SCD_TIMER_CNT /* max value */
+#define SB1250_HPT_SHIFT ((sizeof(unsigned int)*8)-V_SCD_TIMER_WIDTH)
+
+
extern int sb1250_steal_irq(int irq);
+static unsigned int sb1250_hpt_read(void);
+static void sb1250_hpt_init(unsigned int);
+
+static unsigned int hpt_offset;
+
+void __init sb1250_hpt_setup(void)
+{
+ int cpu = smp_processor_id();
+
+ if (!cpu) {
+ /* Setup hpt using timer #3 but do not enable irq for it */
+ __raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CFG)));
+ __raw_writeq(SB1250_HPT_VALUE,
+ IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_INIT)));
+ __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
+ IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CFG)));
+
+ /*
+ * we need to fill 32 bits, so just use the upper 23 bits and pretend
+ * the timer is going 512Mhz instead of 1Mhz
+ */
+ mips_hpt_frequency = V_SCD_TIMER_FREQ << SB1250_HPT_SHIFT;
+ mips_hpt_init = sb1250_hpt_init;
+ mips_hpt_read = sb1250_hpt_read;
+ }
+}
+
+
void sb1250_time_init(void)
{
int cpu = smp_processor_id();
int irq = K_INT_TIMER_0+cpu;
- /* Only have 4 general purpose timers */
- if (cpu > 3) {
+ /* Only have 4 general purpose timers, and we use last one as hpt */
+ if (cpu > 2) {
BUG();
}
- if (!cpu) {
- /* Use our own gettimeoffset() routine */
- do_gettimeoffset = sb1250_gettimeoffset;
- }
-
sb1250_mask_irq(cpu, irq);
/* Map the timer interrupt to ip[4] of this cpu */
@@ -75,10 +103,10 @@ void sb1250_time_init(void)
/* Disable the timer and set up the count */
__raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
#ifdef CONFIG_SIMULATION
- __raw_writeq(50000 / HZ,
+ __raw_writeq((50000 / HZ) - 1,
IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
#else
- __raw_writeq(1000000 / HZ,
+ __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1,
IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
#endif
@@ -103,7 +131,7 @@ void sb1250_timer_interrupt(struct pt_re
int cpu = smp_processor_id();
int irq = K_INT_TIMER_0 + cpu;
- /* Reset the timer */
+ /* ACK interrupt */
____raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
@@ -122,15 +150,26 @@ void sb1250_timer_interrupt(struct pt_re
}
/*
- * We use our own do_gettimeoffset() instead of the generic one,
- * because the generic one does not work for SMP case.
- * In addition, since we use general timer 0 for system time,
- * we can get accurate intra-jiffy offset without calibration.
+ * The HPT is free running from SB1250_HPT_VALUE down to 0 then starts over
+ * again. There's no easy way to set to a specific value so store init value
+ * in hpt_offset and subtract each time.
+ *
+ * Note: Timer isn't full 32bits so shift it into the upper part making
+ * it appear to run at a higher frequency.
*/
-unsigned long sb1250_gettimeoffset(void)
+static unsigned int sb1250_hpt_read(void)
{
- unsigned long count =
- __raw_readq(IOADDR(A_SCD_TIMER_REGISTER(0, R_SCD_TIMER_CNT)));
+ unsigned int count;
- return 1000000/HZ - count;
- }
+ count = G_SCD_TIMER_CNT(__raw_readq(IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CNT))));
+
+ count = (SB1250_HPT_VALUE - count) << SB1250_HPT_SHIFT;
+
+ return count - hpt_offset;
+}
+
+static void sb1250_hpt_init(unsigned int count)
+{
+ hpt_offset = count;
+ return;
+}
diff --git a/arch/mips/sibyte/swarm/setup.c b/arch/mips/sibyte/swarm/setup.c
index b661d24..4a93f1d 100644
--- a/arch/mips/sibyte/swarm/setup.c
+++ b/arch/mips/sibyte/swarm/setup.c
@@ -70,6 +70,14 @@ const char *get_system_type(void)
return "SiByte " SIBYTE_BOARD_NAME;
@@ -72,8 +72,10 @@ const char *get_system_type(void)
void __init swarm_time_init(void)
{
+#if defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
/* Setup HPT */
sb1250_hpt_setup();
+#endif
}
+void __init swarm_time_init(void)
+{
+#if defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
+ /* Setup HPT */
+ sb1250_hpt_setup();
+#endif
+}
+
void __init swarm_timer_setup(struct irqaction *irq)
{
/*
@@ -109,6 +117,7 @@ void __init plat_setup(void)
panic_timeout = 5; /* For debug. */
+ board_time_init = swarm_time_init;
board_timer_setup = swarm_timer_setup;
board_be_handler = swarm_be_handler;
--- a/include/asm-mips/sibyte/sb1250.h
+++ b/include/asm-mips/sibyte/sb1250.h
@@ -45,8 +45,8 @@ extern unsigned int soc_type;
extern unsigned int periph_rev;
extern unsigned int zbbus_mhz;
+extern void sb1250_hpt_setup(void);
extern void sb1250_time_init(void);
-extern unsigned long sb1250_gettimeoffset(void);
extern void sb1250_mask_irq(int cpu, int irq);
extern void sb1250_unmask_irq(int cpu, int irq);
extern void sb1250_smp_finish(void);
--- a/include/asm-mips/sibyte/sb1250_scd.h
+++ b/include/asm-mips/sibyte/sb1250_scd.h
@@ -359,14 +359,15 @@
*/
#define V_SCD_TIMER_FREQ 1000000
+#define V_SCD_TIMER_WIDTH 23
#define S_SCD_TIMER_INIT 0
-#define M_SCD_TIMER_INIT _SB_MAKEMASK(20,S_SCD_TIMER_INIT)
+#define M_SCD_TIMER_INIT _SB_MAKEMASK(V_SCD_TIMER_WIDTH,S_SCD_TIMER_INIT)
#define V_SCD_TIMER_INIT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_INIT)
#define G_SCD_TIMER_INIT(x) _SB_GETVALUE(x,S_SCD_TIMER_INIT,M_SCD_TIMER_INIT)
#define S_SCD_TIMER_CNT 0
-#define M_SCD_TIMER_CNT _SB_MAKEMASK(20,S_SCD_TIMER_CNT)
+#define M_SCD_TIMER_CNT _SB_MAKEMASK(V_SCD_TIMER_WIDTH,S_SCD_TIMER_CNT)
#define V_SCD_TIMER_CNT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_CNT)
#define G_SCD_TIMER_CNT(x) _SB_GETVALUE(x,S_SCD_TIMER_CNT,M_SCD_TIMER_CNT)

59
debian/patches/mips-io-bad-code.patch vendored
View File

@ -1,59 +0,0 @@
From: linux-mips@linux-mips.org
Date: Wed, 15 Mar 2006 11:28:15 +0000
To: git-commits@linux-mips.org
Subject: [MIPS] Work around bad code generation for <asm/io.h>.
Author: Ralf Baechle <ralf@linux-mips.org> Wed Mar 15 11:36:31 2006 +0000
Commit: 6a186683e0a3d51836b6ef6b971508861c7002b5
Gitweb: http://www.linux-mips.org/g/linux/6a186683
Branch: master
If a call to set_io_port_base() was being followed by usage of
mips_io_port_base in the same function gcc was possibly using the old
value due to some clever abuse of const. Adding a barrier will keep
the optimization and result in correct code with latest gcc.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---
include/asm-mips/io.h | 18 +++++++++++++++---
1 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h
index 5c6d6ab..02995ad 100644
--- a/include/asm-mips/io.h
+++ b/include/asm-mips/io.h
@@ -4,7 +4,7 @@
* for more details.
*
* Copyright (C) 1994, 1995 Waldorf GmbH
- * Copyright (C) 1994 - 2000 Ralf Baechle
+ * Copyright (C) 1994 - 2000, 06 Ralf Baechle
* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
* Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved.
* Author: Maciej W. Rozycki <macro@mips.com>
@@ -103,8 +103,20 @@
*/
extern const unsigned long mips_io_port_base;
-#define set_io_port_base(base) \
- do { * (unsigned long *) &mips_io_port_base = (base); } while (0)
+/*
+ * Gcc will generate code to load the value of mips_io_port_base after each
+ * function call which may be fairly wasteful in some cases. So we don't
+ * play quite by the book. We tell gcc mips_io_port_base is a long variable
+ * which solves the code generation issue. Now we need to violate the
+ * aliasing rules a little to make initialization possible and finally we
+ * will need the barrier() to fight side effects of the aliasing chat.
+ * This trickery will eventually collapse under gcc's optimizer. Oh well.
+ */
+static inline void set_io_port_base(unsigned long base)
+{
+ * (unsigned long *) &mips_io_port_base = base;
+ barrier();
+}
/*
* Thanks to James van Artsdalen for a better timing-fix than

273
debian/patches/mips-sb1-irq-hazard.patch vendored
View File

@ -1,273 +0,0 @@
From: linux-mips@linux-mips.org
Date: Mon, 13 Mar 2006 16:07:47 +0000
To: git-commits@linux-mips.org
Subject: [MIPS] SB1: Fix interrupt disable hazard.
Author: Ralf Baechle <ralf@linux-mips.org> Mon Mar 13 16:16:29 2006 +0000
Commit: fa9e2c8227a0a770fbc748d35d0ec1d906c34614
Gitweb: http://www.linux-mips.org/g/linux/fa9e2c82
Branch: master
The SB1 core has a three cycle interrupt disable hazard but we were
wrongly treating it as fully interlocked.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---
include/asm-mips/hazards.h | 180 +++++++++++++++++++++++++-------------------
1 files changed, 103 insertions(+), 77 deletions(-)
diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h
index 6111a0c..feb29a7 100644
--- a/include/asm-mips/hazards.h
+++ b/include/asm-mips/hazards.h
@@ -3,7 +3,9 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
- * Copyright (C) 2003, 2004 Ralf Baechle
+ * Copyright (C) 2003, 2004 Ralf Baechle <ralf@linux-mips.org>
+ * Copyright (C) MIPS Technologies, Inc.
+ * written by Ralf Baechle <ralf@linux-mips.org>
*/
#ifndef _ASM_HAZARDS_H
#define _ASM_HAZARDS_H
@@ -74,8 +76,7 @@
#define irq_disable_hazard
_ehb
-#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) || \
- defined(CONFIG_CPU_SB1)
+#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000)
/*
* R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
@@ -99,13 +100,13 @@
#else /* __ASSEMBLY__ */
__asm__(
- " .macro _ssnop \n\t"
- " sll $0, $0, 1 \n\t"
- " .endm \n\t"
- " \n\t"
- " .macro _ehb \n\t"
- " sll $0, $0, 3 \n\t"
- " .endm \n\t");
+ " .macro _ssnop \n"
+ " sll $0, $0, 1 \n"
+ " .endm \n"
+ " \n"
+ " .macro _ehb \n"
+ " sll $0, $0, 3 \n"
+ " .endm \n");
#ifdef CONFIG_CPU_RM9000
@@ -117,17 +118,21 @@ __asm__(
#define mtc0_tlbw_hazard() \
__asm__ __volatile__( \
- ".set\tmips32\n\t" \
- "_ssnop; _ssnop; _ssnop; _ssnop\n\t" \
- ".set\tmips0")
+ " .set mips32 \n" \
+ " _ssnop \n" \
+ " _ssnop \n" \
+ " _ssnop \n" \
+ " _ssnop \n" \
+ " .set mips0 \n")
#define tlbw_use_hazard() \
__asm__ __volatile__( \
- ".set\tmips32\n\t" \
- "_ssnop; _ssnop; _ssnop; _ssnop\n\t" \
- ".set\tmips0")
-
-#define back_to_back_c0_hazard() do { } while (0)
+ " .set mips32 \n" \
+ " _ssnop \n" \
+ " _ssnop \n" \
+ " _ssnop \n" \
+ " _ssnop \n" \
+ " .set mips0 \n")
#else
@@ -136,15 +141,25 @@ __asm__(
*/
#define mtc0_tlbw_hazard() \
__asm__ __volatile__( \
- ".set noreorder\n\t" \
- "nop; nop; nop; nop; nop; nop;\n\t" \
- ".set reorder\n\t")
+ " .set noreorder \n" \
+ " nop \n" \
+ " nop \n" \
+ " nop \n" \
+ " nop \n" \
+ " nop \n" \
+ " nop \n" \
+ " .set reorder \n")
#define tlbw_use_hazard() \
__asm__ __volatile__( \
- ".set noreorder\n\t" \
- "nop; nop; nop; nop; nop; nop;\n\t" \
- ".set reorder\n\t")
+ " .set noreorder \n" \
+ " nop \n" \
+ " nop \n" \
+ " nop \n" \
+ " nop \n" \
+ " nop \n" \
+ " nop \n" \
+ " .set reorder \n")
#endif
@@ -156,49 +171,26 @@ __asm__(
#ifdef CONFIG_CPU_MIPSR2
-__asm__(
- " .macro\tirq_enable_hazard \n\t"
- " _ehb \n\t"
- " .endm \n\t"
- " \n\t"
- " .macro\tirq_disable_hazard \n\t"
- " _ehb \n\t"
- " .endm \n\t"
- " \n\t"
- " .macro\tback_to_back_c0_hazard \n\t"
- " _ehb \n\t"
- " .endm");
-
-#define irq_enable_hazard() \
- __asm__ __volatile__( \
- "irq_enable_hazard")
+__asm__(" .macro irq_enable_hazard \n"
+ " _ehb \n"
+ " .endm \n"
+ " \n"
+ " .macro irq_disable_hazard \n"
+ " _ehb \n"
+ " .endm \n");
-#define irq_disable_hazard() \
- __asm__ __volatile__( \
- "irq_disable_hazard")
-
-#define back_to_back_c0_hazard() \
- __asm__ __volatile__( \
- "back_to_back_c0_hazard")
-
-#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) || \
- defined(CONFIG_CPU_SB1)
+#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000)
/*
* R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
*/
__asm__(
- " .macro\tirq_enable_hazard \n\t"
- " .endm \n\t"
- " \n\t"
- " .macro\tirq_disable_hazard \n\t"
- " .endm");
-
-#define irq_enable_hazard() do { } while (0)
-#define irq_disable_hazard() do { } while (0)
-
-#define back_to_back_c0_hazard() do { } while (0)
+ " .macro irq_enable_hazard \n"
+ " .endm \n"
+ " \n"
+ " .macro irq_disable_hazard \n"
+ " .endm \n");
#else
@@ -209,29 +201,63 @@ __asm__(
*/
__asm__(
- " # \n\t"
- " # There is a hazard but we do not care \n\t"
- " # \n\t"
- " .macro\tirq_enable_hazard \n\t"
- " .endm \n\t"
- " \n\t"
- " .macro\tirq_disable_hazard \n\t"
- " _ssnop; _ssnop; _ssnop \n\t"
- " .endm");
+ " # \n"
+ " # There is a hazard but we do not care \n"
+ " # \n"
+ " .macro\tirq_enable_hazard \n"
+ " .endm \n"
+ " \n"
+ " .macro\tirq_disable_hazard \n"
+ " _ssnop \n"
+ " _ssnop \n"
+ " _ssnop \n"
+ " .endm \n");
-#define irq_enable_hazard() do { } while (0)
+#endif
+
+#define irq_enable_hazard() \
+ __asm__ __volatile__("irq_enable_hazard")
#define irq_disable_hazard() \
- __asm__ __volatile__( \
- "irq_disable_hazard")
+ __asm__ __volatile__("irq_disable_hazard")
-#define back_to_back_c0_hazard() \
- __asm__ __volatile__( \
- " .set noreorder \n" \
- " nop; nop; nop \n" \
- " .set reorder \n")
+
+/*
+ * Back-to-back hazards -
+ *
+ * What is needed to separate a move to cp0 from a subsequent read from the
+ * same cp0 register?
+ */
+#ifdef CONFIG_CPU_MIPSR2
+
+__asm__(" .macro back_to_back_c0_hazard \n"
+ " _ehb \n"
+ " .endm \n");
+
+#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) || \
+ defined(CONFIG_CPU_SB1)
+
+__asm__(" .macro back_to_back_c0_hazard \n"
+ " .endm \n");
+
+#else
+
+__asm__(" .macro back_to_back_c0_hazard \n"
+ " .set noreorder \n"
+ " _ssnop \n"
+ " _ssnop \n"
+ " _ssnop \n"
+ " .set reorder \n"
+ " .endm");
#endif
+#define back_to_back_c0_hazard() \
+ __asm__ __volatile__("back_to_back_c0_hazard")
+
+
+/*
+ * Instruction execution hazard
+ */
#ifdef CONFIG_CPU_MIPSR2
/*
* gcc has a tradition of misscompiling the previous construct using the

6
debian/patches/series/1 vendored
View File

@ -16,14 +16,12 @@
+ sparc64-atyfb-xl-gr.patch
+ mips-makefile.patch
+ mips-arch-makefile.patch
#FIXME + mips-gettimeofday.patch
#FIXME + mips-ide-scan.patch
+ mips-gettimeofday.patch
+ mips-ide-scan.patch
+ mips-sb1-probe-ide.patch
#FIXME + mips-sb1-irq-hazard.patch
+ mips-sb1-eth-1480.patch
+ mips-sb1-eth-napi.patch
+ mips-sb1-duart.patch
#FIXME + mips-io-bad-code.patch
+ video-vino-64-bit-fix-kernel.diff
+ s390-drivers-ccw-uevent-modalias.patch
+ s390-drivers-ccw-uevent-cleanup.patch

8
debian/patches/series/1-extra vendored
View File

@ -1,8 +1,8 @@
#+ maclist.patch arm armeb
#+ arm-nslu2-maclist.patch arm armeb
+ maclist.patch arm armeb
+ arm-nslu2-maclist.patch arm armeb
+ vserver-version.patch *_vserver *_xen-vserver
+ vserver-vs2.0.2-rc13.patch *_vserver *_xen-vserver
+ vserver-xen-clash.patch *_xen-vserver
+ xen-tree-merge-21966.patch *_xen *_xen-vserver
#+ mips-tulip.patch mipsel
#+ mips-tulip_dc21143.patch mipsel
+ mips-tulip.patch mipsel
+ mips-tulip_dc21143.patch mipsel