[mips*/octeon] Backport OCTEON SATA controller support from 4.6-rc1. Enable AHCI_OCTEON.
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parent
d514efc4cc
commit
7836b549be
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@ -13,6 +13,10 @@ linux (4.5-1~exp2) UNRELEASED; urgency=medium
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[ Aurelien Jarno ]
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* [mipsel/mips/config.loongson-2f] Disable VIDEO_CX23885, VIDEO_IVTV,
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VIDEO_CX231XX, VIDEO_PVRUSB2 (fixes FTBFS).
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* [mips*/octeon] Backport OCTEON SATA controller support from 4.6-rc1.
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Enable AHCI_OCTEON and SATA_AHCI_PLATFORM.
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* [mips*/octeon] Backport Octeon III CN7xxx interface detection from
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4.7 queue.
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-- Ben Hutchings <ben@decadent.org.uk> Fri, 25 Mar 2016 13:43:57 +0000
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@ -30,9 +30,11 @@ CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY=y
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##
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## file: drivers/ata/Kconfig
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##
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CONFIG_AHCI_OCTEON=m
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CONFIG_ATA=y
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CONFIG_ATA_SFF=y
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CONFIG_PATA_OCTEON_CF=y
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CONFIG_SATA_AHCI_PLATFORM=m
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##
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## file: drivers/char/hw_random/Kconfig
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@ -0,0 +1,272 @@
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From: Aleksey Makarov <aleksey.makarov@caviumnetworks.com>
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Date: Thu, 11 Feb 2016 13:53:08 +0000
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Subject: libata: support AHCI on OCTEON platform
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Origin: https://git.kernel.org/linus/a2127e400edd2258fda6d83fe8b10b878a3595d9
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The OCTEON SATA controller is currently found on cn71XX devices.
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Acked-by: Arnd Bergmann <arnd@arndb.de>
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Acked-by: Hans de Goede <hdegoede@redhat.com>
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Acked-by: Rob Herring <robh@kernel.org>
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Signed-off-by: David Daney <david.daney@cavium.com>
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Signed-off-by: Vinita Gupta <vgupta@caviumnetworks.com>
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Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>
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Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
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Signed-off-by: Tejun Heo <tj@kernel.org>
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---
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.../devicetree/bindings/ata/ahci-platform.txt | 1 +
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.../devicetree/bindings/mips/cavium/sata-uctl.txt | 42 +++++++++
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arch/mips/include/asm/octeon/cvmx.h | 9 ++
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drivers/ata/Kconfig | 9 ++
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drivers/ata/Makefile | 1 +
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drivers/ata/ahci_octeon.c | 105 +++++++++++++++++++++
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drivers/ata/ahci_platform.c | 1 +
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7 files changed, 168 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/mips/cavium/sata-uctl.txt
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create mode 100644 drivers/ata/ahci_octeon.c
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diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt b/Documentation/devicetree/bindings/ata/ahci-platform.txt
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index c2340ee..3d84dca 100644
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--- a/Documentation/devicetree/bindings/ata/ahci-platform.txt
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+++ b/Documentation/devicetree/bindings/ata/ahci-platform.txt
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@@ -11,6 +11,7 @@ Required properties:
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- compatible : compatible string, one of:
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- "allwinner,sun4i-a10-ahci"
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- "hisilicon,hisi-ahci"
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+ - "cavium,octeon-7130-ahci"
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- "ibm,476gtr-ahci"
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- "marvell,armada-380-ahci"
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- "snps,dwc-ahci"
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diff --git a/Documentation/devicetree/bindings/mips/cavium/sata-uctl.txt b/Documentation/devicetree/bindings/mips/cavium/sata-uctl.txt
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new file mode 100644
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index 0000000..3bd3c2f
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/mips/cavium/sata-uctl.txt
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@@ -0,0 +1,42 @@
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+* UCTL SATA controller glue
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+
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+UCTL is the bridge unit between the I/O interconnect (an internal bus)
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+and the SATA AHCI host controller (UAHC). It performs the following functions:
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+ - provides interfaces for the applications to access the UAHC AHCI
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+ registers on the CN71XX I/O space.
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+ - provides a bridge for UAHC to fetch AHCI command table entries and data
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+ buffers from Level 2 Cache.
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+ - posts interrupts to the CIU.
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+ - contains registers that:
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+ - control the behavior of the UAHC
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+ - control the clock/reset generation to UAHC
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+ - control endian swapping for all UAHC registers and DMA accesses
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+
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+Properties:
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+
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+- compatible: "cavium,octeon-7130-sata-uctl"
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+
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+ Compatibility with the cn7130 SOC.
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+
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+- reg: The base address of the UCTL register bank.
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+
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+- #address-cells, #size-cells, ranges and dma-ranges must be present and hold
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+ suitable values to map all child nodes.
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+
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+Example:
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+
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+ uctl@118006c000000 {
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+ compatible = "cavium,octeon-7130-sata-uctl";
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+ reg = <0x11800 0x6c000000 0x0 0x100>;
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+ ranges; /* Direct mapping */
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+ dma-ranges;
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+
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+ sata: sata@16c0000000000 {
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+ compatible = "cavium,octeon-7130-ahci";
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+ reg = <0x16c00 0x00000000 0x0 0x200>;
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+ interrupt-parent = <&cibsata>;
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+ interrupts = <2 4>; /* Bit: 2, level */
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+ };
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+ };
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diff --git a/arch/mips/include/asm/octeon/cvmx.h b/arch/mips/include/asm/octeon/cvmx.h
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index 774bb45..19e139c 100644
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--- a/arch/mips/include/asm/octeon/cvmx.h
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+++ b/arch/mips/include/asm/octeon/cvmx.h
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@@ -275,6 +275,11 @@ static inline void cvmx_write_csr(uint64_t csr_addr, uint64_t val)
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cvmx_read64(CVMX_MIO_BOOT_BIST_STAT);
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}
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+static inline void cvmx_writeq_csr(void __iomem *csr_addr, uint64_t val)
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+{
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+ cvmx_write_csr((__force uint64_t)csr_addr, val);
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+}
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+
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static inline void cvmx_write_io(uint64_t io_addr, uint64_t val)
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{
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cvmx_write64(io_addr, val);
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@@ -287,6 +292,10 @@ static inline uint64_t cvmx_read_csr(uint64_t csr_addr)
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return val;
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}
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+static inline uint64_t cvmx_readq_csr(void __iomem *csr_addr)
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+{
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+ return cvmx_read_csr((__force uint64_t) csr_addr);
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+}
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static inline void cvmx_send_single(uint64_t data)
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{
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diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
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index 861643ea..9c15828 100644
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--- a/drivers/ata/Kconfig
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+++ b/drivers/ata/Kconfig
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@@ -151,6 +151,15 @@ config AHCI_MVEBU
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If unsure, say N.
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+config AHCI_OCTEON
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+ tristate "Cavium Octeon Soc Serial ATA"
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+ depends on SATA_AHCI_PLATFORM && CAVIUM_OCTEON_SOC
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+ default y
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+ help
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+ This option enables support for Cavium Octeon SoC Serial ATA.
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+
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+ If unsure, say N.
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+
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config AHCI_SUNXI
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tristate "Allwinner sunxi AHCI SATA support"
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depends on ARCH_SUNXI
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diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
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index af45eff..1857952 100644
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--- a/drivers/ata/Makefile
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+++ b/drivers/ata/Makefile
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@@ -15,6 +15,7 @@ obj-$(CONFIG_AHCI_CEVA) += ahci_ceva.o libahci.o libahci_platform.o
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obj-$(CONFIG_AHCI_DA850) += ahci_da850.o libahci.o libahci_platform.o
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obj-$(CONFIG_AHCI_IMX) += ahci_imx.o libahci.o libahci_platform.o
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obj-$(CONFIG_AHCI_MVEBU) += ahci_mvebu.o libahci.o libahci_platform.o
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+obj-$(CONFIG_AHCI_OCTEON) += ahci_octeon.o
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obj-$(CONFIG_AHCI_SUNXI) += ahci_sunxi.o libahci.o libahci_platform.o
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obj-$(CONFIG_AHCI_ST) += ahci_st.o libahci.o libahci_platform.o
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obj-$(CONFIG_AHCI_TEGRA) += ahci_tegra.o libahci.o libahci_platform.o
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diff --git a/drivers/ata/ahci_octeon.c b/drivers/ata/ahci_octeon.c
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new file mode 100644
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index 0000000..ea865fe
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--- /dev/null
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+++ b/drivers/ata/ahci_octeon.c
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@@ -0,0 +1,105 @@
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+/*
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+ * SATA glue for Cavium Octeon III SOCs.
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+ *
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+ *
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+ * This file is subject to the terms and conditions of the GNU General Public
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+ * License. See the file "COPYING" in the main directory of this archive
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+ * for more details.
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+ *
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+ * Copyright (C) 2010-2015 Cavium Networks
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+ *
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+ */
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+
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+#include <linux/module.h>
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+#include <linux/dma-mapping.h>
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+#include <linux/platform_device.h>
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+#include <linux/of_platform.h>
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+
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+#include <asm/octeon/octeon.h>
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+#include <asm/bitfield.h>
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+
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+#define CVMX_SATA_UCTL_SHIM_CFG 0xE8
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+
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+#define SATA_UCTL_ENDIAN_MODE_BIG 1
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+#define SATA_UCTL_ENDIAN_MODE_LITTLE 0
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+#define SATA_UCTL_ENDIAN_MODE_MASK 3
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+
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+#define SATA_UCTL_DMA_ENDIAN_MODE_SHIFT 8
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+#define SATA_UCTL_CSR_ENDIAN_MODE_SHIFT 0
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+#define SATA_UCTL_DMA_READ_CMD_SHIFT 12
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+
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+static int ahci_octeon_probe(struct platform_device *pdev)
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+{
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+ struct device *dev = &pdev->dev;
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+ struct device_node *node = dev->of_node;
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+ struct resource *res;
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+ void __iomem *base;
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+ u64 cfg;
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+ int ret;
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+
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+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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+ if (!res) {
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+ dev_err(&pdev->dev, "Platform resource[0] is missing\n");
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+ return -ENODEV;
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+ }
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+
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+ base = devm_ioremap_resource(&pdev->dev, res);
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+ if (IS_ERR(base))
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+ return PTR_ERR(base);
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+
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+ cfg = cvmx_readq_csr(base + CVMX_SATA_UCTL_SHIM_CFG);
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+
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+ cfg &= ~(SATA_UCTL_ENDIAN_MODE_MASK << SATA_UCTL_DMA_ENDIAN_MODE_SHIFT);
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+ cfg &= ~(SATA_UCTL_ENDIAN_MODE_MASK << SATA_UCTL_CSR_ENDIAN_MODE_SHIFT);
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+
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+#ifdef __BIG_ENDIAN
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+ cfg |= SATA_UCTL_ENDIAN_MODE_BIG << SATA_UCTL_DMA_ENDIAN_MODE_SHIFT;
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+ cfg |= SATA_UCTL_ENDIAN_MODE_BIG << SATA_UCTL_CSR_ENDIAN_MODE_SHIFT;
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+#else
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+ cfg |= SATA_UCTL_ENDIAN_MODE_LITTLE << SATA_UCTL_DMA_ENDIAN_MODE_SHIFT;
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+ cfg |= SATA_UCTL_ENDIAN_MODE_LITTLE << SATA_UCTL_CSR_ENDIAN_MODE_SHIFT;
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+#endif
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+
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+ cfg |= 1 << SATA_UCTL_DMA_READ_CMD_SHIFT;
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+
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+ cvmx_writeq_csr(base + CVMX_SATA_UCTL_SHIM_CFG, cfg);
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+
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+ if (!node) {
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+ dev_err(dev, "no device node, failed to add octeon sata\n");
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+ return -ENODEV;
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+ }
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+
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+ ret = of_platform_populate(node, NULL, NULL, dev);
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+ if (ret) {
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+ dev_err(dev, "failed to add ahci-platform core\n");
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+ return ret;
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+ }
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+
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+ return 0;
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+}
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+
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+static int ahci_octeon_remove(struct platform_device *pdev)
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+{
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+ return 0;
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+}
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+
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+static const struct of_device_id octeon_ahci_match[] = {
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+ { .compatible = "cavium,octeon-7130-sata-uctl", },
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+ {},
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+};
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+MODULE_DEVICE_TABLE(of, octeon_ahci_match);
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+
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+static struct platform_driver ahci_octeon_driver = {
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+ .probe = ahci_octeon_probe,
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+ .remove = ahci_octeon_remove,
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+ .driver = {
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+ .name = "octeon-ahci",
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+ .of_match_table = octeon_ahci_match,
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+ },
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+};
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+
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+module_platform_driver(ahci_octeon_driver);
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+
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+MODULE_LICENSE("GPL");
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+MODULE_AUTHOR("Cavium, Inc. <support@cavium.com>");
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+MODULE_DESCRIPTION("Cavium Inc. sata config.");
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diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c
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index 04975b8..4044233 100644
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--- a/drivers/ata/ahci_platform.c
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+++ b/drivers/ata/ahci_platform.c
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@@ -76,6 +76,7 @@ static const struct of_device_id ahci_of_match[] = {
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{ .compatible = "ibm,476gtr-ahci", },
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{ .compatible = "snps,dwc-ahci", },
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{ .compatible = "hisilicon,hisi-ahci", },
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+ { .compatible = "cavium,octeon-7130-ahci", },
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{},
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};
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MODULE_DEVICE_TABLE(of, ahci_of_match);
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--
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2.8.0.rc3
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@ -50,6 +50,7 @@ bugfix/x86/viafb-autoload-on-olpc-xo1.5-only.patch
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features/mips/MIPS-increase-MAX-PHYSMEM-BITS-on-Loongson-3-only.patch
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features/mips/MIPS-Loongson-3-Add-Loongson-LS3A-RS780E-1-way-machi.patch
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features/mips/MIPS-octeon-Add-support-for-the-UBNT-E200-board.patch
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features/mips/libata-support-AHCI-on-OCTEON-platform.patch
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features/x86/x86-memtest-WARN-if-bad-RAM-found.patch
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features/x86/x86-make-x32-syscall-support-conditional.patch
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features/sparc/hwrng-n2-attach-on-t5-m5-t7-m7-sparc-cpus.patch
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