Drop "x86/speculation: Add Special Register Buffer Data Sampling (SRBDS) mitigation"
This commit is contained in:
Salvatore Bonaccorso
parent
8fe5ca8037
commit
68c22bc508
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@ -480,7 +480,6 @@ linux (4.19.128-1) UNRELEASED; urgency=medium
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- staging: rtl8712: Fix IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK
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- CDC-ACM: heed quirk also in error handling
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- nvmem: qfprom: remove incorrect write support
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- x86/speculation: Add Special Register Buffer Data Sampling (SRBDS) mitigation
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- x86/speculation: Add SRBDS vulnerability and mitigation documentation
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- x86/speculation: Add Ivy Bridge to affected list
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- uprobes: ensure that uprobe->offset and ->ref_ctr_offset are properly aligned
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@ -1,383 +0,0 @@
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From: Mark Gross <mgross@linux.intel.com>
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Date: Thu, 16 Apr 2020 17:54:04 +0200
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Subject: [3/5] x86/speculation: Add Special Register Buffer Data Sampling
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(SRBDS) mitigation
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Origin: https://git.kernel.org/linus/7e5b3c267d256822407a22fdce6afdf9cd13f9fb
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Bug-Debian-Security: https://security-tracker.debian.org/tracker/CVE-2020-0543
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SRBDS is an MDS-like speculative side channel that can leak bits from the
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random number generator (RNG) across cores and threads. New microcode
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serializes the processor access during the execution of RDRAND and
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RDSEED. This ensures that the shared buffer is overwritten before it is
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released for reuse.
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While it is present on all affected CPU models, the microcode mitigation
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is not needed on models that enumerate ARCH_CAPABILITIES[MDS_NO] in the
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cases where TSX is not supported or has been disabled with TSX_CTRL.
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The mitigation is activated by default on affected processors and it
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increases latency for RDRAND and RDSEED instructions. Among other
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effects this will reduce throughput from /dev/urandom.
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* Enable administrator to configure the mitigation off when desired using
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either mitigations=off or srbds=off.
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* Export vulnerability status via sysfs
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* Rename file-scoped macros to apply for non-whitelist table initializations.
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[ bp: Massage,
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- s/VULNBL_INTEL_STEPPING/VULNBL_INTEL_STEPPINGS/g,
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- do not read arch cap MSR a second time in tsx_fused_off() - just pass it in,
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- flip check in cpu_set_bug_bits() to save an indentation level,
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- reflow comments.
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jpoimboe: s/Mitigated/Mitigation/ in user-visible strings
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tglx: Dropped the fused off magic for now
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]
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Signed-off-by: Mark Gross <mgross@linux.intel.com>
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Signed-off-by: Borislav Petkov <bp@suse.de>
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Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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Reviewed-by: Tony Luck <tony.luck@intel.com>
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Reviewed-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
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Reviewed-by: Josh Poimboeuf <jpoimboe@redhat.com>
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Tested-by: Neelima Krishnan <neelima.krishnan@intel.com>
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---
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.../ABI/testing/sysfs-devices-system-cpu | 1 +
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.../admin-guide/kernel-parameters.txt | 20 ++++
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arch/x86/include/asm/cpufeatures.h | 2 +
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arch/x86/include/asm/msr-index.h | 4 +
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arch/x86/kernel/cpu/bugs.c | 106 ++++++++++++++++++
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arch/x86/kernel/cpu/common.c | 31 +++++
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arch/x86/kernel/cpu/cpu.h | 1 +
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drivers/base/cpu.c | 8 ++
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8 files changed, 173 insertions(+)
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diff --git a/Documentation/ABI/testing/sysfs-devices-system-cpu b/Documentation/ABI/testing/sysfs-devices-system-cpu
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index b492fb6057c9..b9c14c11efc5 100644
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--- a/Documentation/ABI/testing/sysfs-devices-system-cpu
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+++ b/Documentation/ABI/testing/sysfs-devices-system-cpu
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@@ -478,6 +478,7 @@ What: /sys/devices/system/cpu/vulnerabilities
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/sys/devices/system/cpu/vulnerabilities/spec_store_bypass
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/sys/devices/system/cpu/vulnerabilities/l1tf
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/sys/devices/system/cpu/vulnerabilities/mds
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+ /sys/devices/system/cpu/vulnerabilities/srbds
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/sys/devices/system/cpu/vulnerabilities/tsx_async_abort
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/sys/devices/system/cpu/vulnerabilities/itlb_multihit
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Date: January 2018
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diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
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index 1a5101b7e853..30752db57587 100644
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--- a/Documentation/admin-guide/kernel-parameters.txt
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+++ b/Documentation/admin-guide/kernel-parameters.txt
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@@ -4415,6 +4415,26 @@
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spia_pedr=
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spia_peddr=
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+ srbds= [X86,INTEL]
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+ Control the Special Register Buffer Data Sampling
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+ (SRBDS) mitigation.
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+
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+ Certain CPUs are vulnerable to an MDS-like
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+ exploit which can leak bits from the random
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+ number generator.
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+
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+ By default, this issue is mitigated by
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+ microcode. However, the microcode fix can cause
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+ the RDRAND and RDSEED instructions to become
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+ much slower. Among other effects, this will
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+ result in reduced throughput from /dev/urandom.
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+
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+ The microcode mitigation can be disabled with
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+ the following option:
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+
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+ off: Disable mitigation and remove
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+ performance impact to RDRAND and RDSEED
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+
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srcutree.counter_wrap_check [KNL]
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Specifies how frequently to check for
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grace-period sequence counter wrap for the
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diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
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index 8c13b99b9507..9f03ac233566 100644
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--- a/arch/x86/include/asm/cpufeatures.h
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+++ b/arch/x86/include/asm/cpufeatures.h
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@@ -347,6 +347,7 @@
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/* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */
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#define X86_FEATURE_AVX512_4VNNIW (18*32+ 2) /* AVX-512 Neural Network Instructions */
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#define X86_FEATURE_AVX512_4FMAPS (18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */
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+#define X86_FEATURE_SRBDS_CTRL (18*32+ 9) /* "" SRBDS mitigation MSR available */
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#define X86_FEATURE_TSX_FORCE_ABORT (18*32+13) /* "" TSX_FORCE_ABORT */
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#define X86_FEATURE_MD_CLEAR (18*32+10) /* VERW clears CPU buffers */
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#define X86_FEATURE_PCONFIG (18*32+18) /* Intel PCONFIG */
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@@ -391,5 +392,6 @@
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#define X86_BUG_SWAPGS X86_BUG(21) /* CPU is affected by speculation through SWAPGS */
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#define X86_BUG_TAA X86_BUG(22) /* CPU is affected by TSX Async Abort(TAA) */
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#define X86_BUG_ITLB_MULTIHIT X86_BUG(23) /* CPU may incur MCE during certain page attribute changes */
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+#define X86_BUG_SRBDS X86_BUG(24) /* CPU may leak RNG bits if not mitigated */
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#endif /* _ASM_X86_CPUFEATURES_H */
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diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
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index d2c25a13e1ce..5bb11a8c245e 100644
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--- a/arch/x86/include/asm/msr-index.h
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+++ b/arch/x86/include/asm/msr-index.h
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@@ -110,6 +110,10 @@
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#define TSX_CTRL_RTM_DISABLE BIT(0) /* Disable RTM feature */
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#define TSX_CTRL_CPUID_CLEAR BIT(1) /* Disable TSX enumeration */
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+/* SRBDS support */
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+#define MSR_IA32_MCU_OPT_CTRL 0x00000123
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+#define RNGDS_MITG_DIS BIT(0)
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+
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#define MSR_IA32_SYSENTER_CS 0x00000174
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#define MSR_IA32_SYSENTER_ESP 0x00000175
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#define MSR_IA32_SYSENTER_EIP 0x00000176
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diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
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index 2d23a448e72d..cf07437cd106 100644
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--- a/arch/x86/kernel/cpu/bugs.c
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+++ b/arch/x86/kernel/cpu/bugs.c
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@@ -41,6 +41,7 @@ static void __init l1tf_select_mitigation(void);
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static void __init mds_select_mitigation(void);
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static void __init mds_print_mitigation(void);
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static void __init taa_select_mitigation(void);
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+static void __init srbds_select_mitigation(void);
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/* The base value of the SPEC_CTRL MSR that always has to be preserved. */
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u64 x86_spec_ctrl_base;
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@@ -108,6 +109,7 @@ void __init check_bugs(void)
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l1tf_select_mitigation();
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mds_select_mitigation();
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taa_select_mitigation();
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+ srbds_select_mitigation();
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/*
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* As MDS and TAA mitigations are inter-related, print MDS
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@@ -390,6 +392,97 @@ static int __init tsx_async_abort_parse_cmdline(char *str)
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}
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early_param("tsx_async_abort", tsx_async_abort_parse_cmdline);
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+#undef pr_fmt
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+#define pr_fmt(fmt) "SRBDS: " fmt
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+
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+enum srbds_mitigations {
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+ SRBDS_MITIGATION_OFF,
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+ SRBDS_MITIGATION_UCODE_NEEDED,
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+ SRBDS_MITIGATION_FULL,
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+ SRBDS_MITIGATION_TSX_OFF,
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+ SRBDS_MITIGATION_HYPERVISOR,
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+};
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+
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+static enum srbds_mitigations srbds_mitigation __ro_after_init = SRBDS_MITIGATION_FULL;
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+
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+static const char * const srbds_strings[] = {
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+ [SRBDS_MITIGATION_OFF] = "Vulnerable",
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+ [SRBDS_MITIGATION_UCODE_NEEDED] = "Vulnerable: No microcode",
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+ [SRBDS_MITIGATION_FULL] = "Mitigation: Microcode",
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+ [SRBDS_MITIGATION_TSX_OFF] = "Mitigation: TSX disabled",
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+ [SRBDS_MITIGATION_HYPERVISOR] = "Unknown: Dependent on hypervisor status",
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+};
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+
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+static bool srbds_off;
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+
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+void update_srbds_msr(void)
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+{
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+ u64 mcu_ctrl;
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+
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+ if (!boot_cpu_has_bug(X86_BUG_SRBDS))
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+ return;
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+
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+ if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
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+ return;
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+
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+ if (srbds_mitigation == SRBDS_MITIGATION_UCODE_NEEDED)
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+ return;
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+
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+ rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
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+
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+ switch (srbds_mitigation) {
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+ case SRBDS_MITIGATION_OFF:
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+ case SRBDS_MITIGATION_TSX_OFF:
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+ mcu_ctrl |= RNGDS_MITG_DIS;
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+ break;
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+ case SRBDS_MITIGATION_FULL:
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+ mcu_ctrl &= ~RNGDS_MITG_DIS;
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+ break;
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+ default:
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+ break;
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+ }
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+
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+ wrmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
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+}
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+
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+static void __init srbds_select_mitigation(void)
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+{
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+ u64 ia32_cap;
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+
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+ if (!boot_cpu_has_bug(X86_BUG_SRBDS))
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+ return;
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+
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+ /*
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+ * Check to see if this is one of the MDS_NO systems supporting
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+ * TSX that are only exposed to SRBDS when TSX is enabled.
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+ */
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+ ia32_cap = x86_read_arch_cap_msr();
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+ if ((ia32_cap & ARCH_CAP_MDS_NO) && !boot_cpu_has(X86_FEATURE_RTM))
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+ srbds_mitigation = SRBDS_MITIGATION_TSX_OFF;
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+ else if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
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+ srbds_mitigation = SRBDS_MITIGATION_HYPERVISOR;
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+ else if (!boot_cpu_has(X86_FEATURE_SRBDS_CTRL))
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+ srbds_mitigation = SRBDS_MITIGATION_UCODE_NEEDED;
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+ else if (cpu_mitigations_off() || srbds_off)
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+ srbds_mitigation = SRBDS_MITIGATION_OFF;
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+
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+ update_srbds_msr();
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+ pr_info("%s\n", srbds_strings[srbds_mitigation]);
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+}
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+
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+static int __init srbds_parse_cmdline(char *str)
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+{
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+ if (!str)
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+ return -EINVAL;
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+
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+ if (!boot_cpu_has_bug(X86_BUG_SRBDS))
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+ return 0;
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+
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+ srbds_off = !strcmp(str, "off");
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+ return 0;
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+}
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+early_param("srbds", srbds_parse_cmdline);
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+
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#undef pr_fmt
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#define pr_fmt(fmt) "Spectre V1 : " fmt
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@@ -1491,6 +1584,11 @@ static char *ibpb_state(void)
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return "";
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}
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+static ssize_t srbds_show_state(char *buf)
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+{
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+ return sprintf(buf, "%s\n", srbds_strings[srbds_mitigation]);
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+}
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+
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static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr,
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char *buf, unsigned int bug)
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{
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@@ -1535,6 +1633,9 @@ static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr
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case X86_BUG_ITLB_MULTIHIT:
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return itlb_multihit_show_state(buf);
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+ case X86_BUG_SRBDS:
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+ return srbds_show_state(buf);
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+
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default:
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break;
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}
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@@ -1581,4 +1682,9 @@ ssize_t cpu_show_itlb_multihit(struct device *dev, struct device_attribute *attr
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{
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return cpu_show_common(dev, attr, buf, X86_BUG_ITLB_MULTIHIT);
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}
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+
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+ssize_t cpu_show_srbds(struct device *dev, struct device_attribute *attr, char *buf)
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+{
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+ return cpu_show_common(dev, attr, buf, X86_BUG_SRBDS);
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+}
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#endif
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diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
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index 375e1d459b68..2058e8c0e61d 100644
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--- a/arch/x86/kernel/cpu/common.c
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+++ b/arch/x86/kernel/cpu/common.c
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@@ -1013,6 +1013,27 @@ static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = {
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{}
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};
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+#define VULNBL_INTEL_STEPPINGS(model, steppings, issues) \
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+ X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE(INTEL, 6, \
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+ INTEL_FAM6_##model, steppings, \
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+ X86_FEATURE_ANY, issues)
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+
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+#define SRBDS BIT(0)
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+
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+static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = {
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+ VULNBL_INTEL_STEPPINGS(IVYBRIDGE, X86_STEPPING_ANY, SRBDS),
|
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+ VULNBL_INTEL_STEPPINGS(HASWELL_CORE, X86_STEPPING_ANY, SRBDS),
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+ VULNBL_INTEL_STEPPINGS(HASWELL_ULT, X86_STEPPING_ANY, SRBDS),
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+ VULNBL_INTEL_STEPPINGS(HASWELL_GT3E, X86_STEPPING_ANY, SRBDS),
|
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+ VULNBL_INTEL_STEPPINGS(BROADWELL_GT3E, X86_STEPPING_ANY, SRBDS),
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+ VULNBL_INTEL_STEPPINGS(BROADWELL_CORE, X86_STEPPING_ANY, SRBDS),
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+ VULNBL_INTEL_STEPPINGS(SKYLAKE_MOBILE, X86_STEPPING_ANY, SRBDS),
|
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+ VULNBL_INTEL_STEPPINGS(SKYLAKE_DESKTOP, X86_STEPPING_ANY, SRBDS),
|
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+ VULNBL_INTEL_STEPPINGS(KABYLAKE_MOBILE, X86_STEPPINGS(0x0, 0xC), SRBDS),
|
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+ VULNBL_INTEL_STEPPINGS(KABYLAKE_DESKTOP,X86_STEPPINGS(0x0, 0xD), SRBDS),
|
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+ {}
|
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+};
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+
|
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static bool __init cpu_matches(const struct x86_cpu_id *table, unsigned long which)
|
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{
|
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const struct x86_cpu_id *m = x86_match_cpu(table);
|
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@@ -1078,6 +1099,15 @@ static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c)
|
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(ia32_cap & ARCH_CAP_TSX_CTRL_MSR)))
|
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setup_force_cpu_bug(X86_BUG_TAA);
|
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|
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+ /*
|
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+ * SRBDS affects CPUs which support RDRAND or RDSEED and are listed
|
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+ * in the vulnerability blacklist.
|
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+ */
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+ if ((cpu_has(c, X86_FEATURE_RDRAND) ||
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+ cpu_has(c, X86_FEATURE_RDSEED)) &&
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+ cpu_matches(cpu_vuln_blacklist, SRBDS))
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+ setup_force_cpu_bug(X86_BUG_SRBDS);
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+
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if (cpu_matches(cpu_vuln_whitelist, NO_MELTDOWN))
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return;
|
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|
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@@ -1522,6 +1552,7 @@ void identify_secondary_cpu(struct cpuinfo_x86 *c)
|
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mtrr_ap_init();
|
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validate_apic_and_package_id(c);
|
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x86_spec_ctrl_setup_ap();
|
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+ update_srbds_msr();
|
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}
|
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|
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static __init int setup_noclflush(char *arg)
|
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diff --git a/arch/x86/kernel/cpu/cpu.h b/arch/x86/kernel/cpu/cpu.h
|
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index 236582c90d3f..e89602d2aff5 100644
|
||||
--- a/arch/x86/kernel/cpu/cpu.h
|
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+++ b/arch/x86/kernel/cpu/cpu.h
|
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@@ -80,6 +80,7 @@ extern void detect_ht(struct cpuinfo_x86 *c);
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unsigned int aperfmperf_get_khz(int cpu);
|
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|
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extern void x86_spec_ctrl_setup_ap(void);
|
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+extern void update_srbds_msr(void);
|
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extern u64 x86_read_arch_cap_msr(void);
|
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diff --git a/drivers/base/cpu.c b/drivers/base/cpu.c
|
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index f3ecf7418ed4..1df057486176 100644
|
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--- a/drivers/base/cpu.c
|
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+++ b/drivers/base/cpu.c
|
||||
@@ -565,6 +565,12 @@ ssize_t __weak cpu_show_itlb_multihit(struct device *dev,
|
||||
return sprintf(buf, "Not affected\n");
|
||||
}
|
||||
|
||||
+ssize_t __weak cpu_show_srbds(struct device *dev,
|
||||
+ struct device_attribute *attr, char *buf)
|
||||
+{
|
||||
+ return sprintf(buf, "Not affected\n");
|
||||
+}
|
||||
+
|
||||
static DEVICE_ATTR(meltdown, 0444, cpu_show_meltdown, NULL);
|
||||
static DEVICE_ATTR(spectre_v1, 0444, cpu_show_spectre_v1, NULL);
|
||||
static DEVICE_ATTR(spectre_v2, 0444, cpu_show_spectre_v2, NULL);
|
||||
@@ -573,6 +579,7 @@ static DEVICE_ATTR(l1tf, 0444, cpu_show_l1tf, NULL);
|
||||
static DEVICE_ATTR(mds, 0444, cpu_show_mds, NULL);
|
||||
static DEVICE_ATTR(tsx_async_abort, 0444, cpu_show_tsx_async_abort, NULL);
|
||||
static DEVICE_ATTR(itlb_multihit, 0444, cpu_show_itlb_multihit, NULL);
|
||||
+static DEVICE_ATTR(srbds, 0444, cpu_show_srbds, NULL);
|
||||
|
||||
static struct attribute *cpu_root_vulnerabilities_attrs[] = {
|
||||
&dev_attr_meltdown.attr,
|
||||
@@ -583,6 +590,7 @@ static struct attribute *cpu_root_vulnerabilities_attrs[] = {
|
||||
&dev_attr_mds.attr,
|
||||
&dev_attr_tsx_async_abort.attr,
|
||||
&dev_attr_itlb_multihit.attr,
|
||||
+ &dev_attr_srbds.attr,
|
||||
NULL
|
||||
};
|
||||
|
||||
|
|
@ -296,7 +296,6 @@ features/arm/staging-vc04_services-Use-correct-cache-line-size.patch
|
|||
# Security fixes
|
||||
debian/i386-686-pae-pci-set-pci-nobios-by-default.patch
|
||||
debian/ntfs-mark-it-as-broken.patch
|
||||
bugfix/x86/srbds/0003-x86-speculation-Add-Special-Register-Buffer-Data-Sam.patch
|
||||
bugfix/x86/srbds/0004-x86-speculation-Add-SRBDS-vulnerability-and-mitigati.patch
|
||||
bugfix/x86/srbds/0005-x86-speculation-Add-Ivy-Bridge-to-affected-list.patch
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue