diff --git a/debian/changelog b/debian/changelog
index c6694d8d8..422864253 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -152,6 +152,14 @@ linux (3.15~rc5-1~exp1) experimental; urgency=medium
 
  -- maximilian attems <maks@debian.org>  Fri, 16 May 2014 14:33:57 +0200
 
+linux (3.14.15-2) unstable; urgency=medium
+
+  [ Aurelien Jarno ]
+  * [mips*/4kc-malta] Remove ABI reference as previous kernels were not
+    really usable, and the fix changes the ABI.
+
+ -- Ben Hutchings <ben@decadent.org.uk>  Sat, 09 Aug 2014 01:09:38 +0100
+
 linux (3.14.15-1) unstable; urgency=medium
 
   * New upstream stable update:
diff --git a/debian/patches/bugfix/mips/MIPS-O32-32-bit-Fix-bug-which-can-cause-incorrect-sy.patch b/debian/patches/bugfix/mips/MIPS-O32-32-bit-Fix-bug-which-can-cause-incorrect-sy.patch
index e15ce085a..330613f1b 100644
--- a/debian/patches/bugfix/mips/MIPS-O32-32-bit-Fix-bug-which-can-cause-incorrect-sy.patch
+++ b/debian/patches/bugfix/mips/MIPS-O32-32-bit-Fix-bug-which-can-cause-incorrect-sy.patch
@@ -2,7 +2,7 @@ From: Alex Smith <alex.smith@imgtec.com>
 Date: Wed, 23 Jul 2014 14:40:11 +0100
 Subject: MIPS: O32/32-bit: Fix bug which can cause incorrect system
  call restarts
-Origin: https://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/commit/?id=0ae0fe30fc3415727960270bd8fd61aea4c8a882 
+Origin: https://git.kernel.org/linus/e90e6fddc57055c4c6b57f92787fea1c065d440b
 
 On 32-bit/O32, pt_regs has a padding area at the beginning into which the
 syscall arguments passed via the user stack are copied. 4 arguments
diff --git a/debian/patches/bugfix/mips/MIPS-prevent-user-from-setting-FCSR-cause-bits.patch b/debian/patches/bugfix/mips/MIPS-prevent-user-from-setting-FCSR-cause-bits.patch
index ed2498fb6..bcff7aaa3 100644
--- a/debian/patches/bugfix/mips/MIPS-prevent-user-from-setting-FCSR-cause-bits.patch
+++ b/debian/patches/bugfix/mips/MIPS-prevent-user-from-setting-FCSR-cause-bits.patch
@@ -1,7 +1,7 @@
 From: Paul Burton <paul.burton@imgtec.com>
 Date: Tue, 22 Jul 2014 14:21:21 +0100
 Subject: MIPS: prevent user from setting FCSR cause bits
-Origin: https://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/commit/?id=b1442d39fac2fcfbe6a4814979020e993ca59c9e 
+Origin: https://git.kernel.org/linus/b1442d39fac2fcfbe6a4814979020e993ca59c9e
 
 If one or more matching FCSR cause & enable bits are set in saved thread
 context then when that context is restored the kernel will take an FP
diff --git a/debian/patches/bugfix/mips/MIPS-tlbex-fix-a-missing-statement-for-HUGETLB.patch b/debian/patches/bugfix/mips/MIPS-tlbex-fix-a-missing-statement-for-HUGETLB.patch
index 46cd961b9..c9225b6c1 100644
--- a/debian/patches/bugfix/mips/MIPS-tlbex-fix-a-missing-statement-for-HUGETLB.patch
+++ b/debian/patches/bugfix/mips/MIPS-tlbex-fix-a-missing-statement-for-HUGETLB.patch
@@ -1,7 +1,7 @@
 From: Huacai Chen <chenhc@lemote.com>
 Date: Tue, 29 Jul 2014 14:54:40 +0800
 Subject: MIPS: tlbex: fix a missing statement for HUGETLB
-Origin: https://git.kernel.org/cgit/linux/kernel/git/next/linux-next.git/commit/?id=8393c524a25609a30129e4a8975cf3b91f6c16a5 
+Origin: https://git.kernel.org/linus/8393c524a25609a30129e4a8975cf3b91f6c16a5
 
 In commit 2c8c53e28f1 (MIPS: Optimize TLB handlers for Octeon CPUs)
 build_r4000_tlb_refill_handler() is modified. But it doesn't compatible