ip32: Enable FAST-20 for onboard scsi
svn path=/dists/trunk/linux-2.6/; revision=11747
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@ -86,6 +86,7 @@ linux-2.6 (2.6.26~rc8-1~experimental.1) UNRELEASED; urgency=low
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- IP22: Set MIPS_L1_CACHE_SHIFT to 7
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- IP32: fix unexpected irq 71
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- gbefb: fix cmap FIFO timeout (closes: #487257)
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- Enable FAST-20 for onboard scsi
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* [arm/ixp4xx] Add support for Freecom FSG-3 (Rod Whitby).
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* [arm/ixp4xx] Enable CONFIG_MACH_DSMG600.
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* [arm/iop32x] Unset NET_DMA since it actually leads to worse network
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@ -0,0 +1,29 @@
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Both onboard controller of the O2 support FAST-20 transfer speeds,
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but the bit, which signals that to the aic driver, isn't set. Instead
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of adding detection code to the scsi driver, we just fake the missing
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bit in the PCI config space of the scsi chips.
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Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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---
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arch/mips/pci/ops-mace.c | 7 +++++++
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1 files changed, 7 insertions(+), 0 deletions(-)
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diff --git a/arch/mips/pci/ops-mace.c b/arch/mips/pci/ops-mace.c
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index e958818..1cfb558 100644
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--- a/arch/mips/pci/ops-mace.c
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+++ b/arch/mips/pci/ops-mace.c
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@@ -61,6 +61,13 @@ mace_pci_read_config(struct pci_bus *bus, unsigned int devfn,
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/* ack possible master abort */
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mace->pci.error &= ~MACEPCI_ERROR_MASTER_ABORT;
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mace->pci.control = control;
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+ /*
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+ * someone forgot to set the ultra bit for the onboard
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+ * scsi chips; we fake it here
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+ */
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+ if (bus->number == 0 && reg == 0x40 && size == 4 &&
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+ (devfn == (1 << 3) || devfn == (2 << 3)))
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+ *val |= 0x1000;
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DPRINTK("read%d: reg=%08x,val=%02x\n", size * 8, reg, *val);
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@ -25,6 +25,7 @@
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+ bugfix/mips/ip32_fix_unexpected_irq_71.patch
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+ bugfix/mips/ip22_cache_shift.patch
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+ bugfix/mips/gbefb_fix_cmap_fifo_timeout.patch
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+ bugfix/mips/ip32_enable_fast_20.patch
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+ bugfix/arm/disable-dvb_b2c2_flexcop.patch
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+ bugfix/arm/disable-dvb_budget.patch
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+ bugfix/arm/disable-netxen_nic.patch
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