* backport mips/swarm: fix M3 TLB exception handler.
svn path=/dists/sid/linux-2.6/; revision=15650
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668cc1521c
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@ -25,6 +25,7 @@ linux-2.6 (2.6.32-13) UNRELEASED; urgency=low
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[ Aurelien Jarno ]
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* mips/swarm: fix boot from IDE based media (Sebastian Andrzej Siewior)
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(closes: #466977).
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* backport mips/swarm: fix M3 TLB exception handler.
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-- Frederik Schüler <fs@debian.org> Wed, 05 May 2010 17:54:01 +0200
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@ -0,0 +1,164 @@
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commit 8d9df29db273ab9a330828f4f4f6669d293a730a
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Author: Ralf Baechle <ralf@linux-mips.org>
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Date: Tue Mar 23 00:02:43 2010 +0100
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MIPS: Sibyte: Apply M3 workaround only on affected chip types and versions.
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Previously it was unconditionally used on all Sibyte family SOCs. The
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M3 bug has to be handled in the TLB exception handler which is extremly
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performance sensitive, so this modification is expected to deliver around
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2-3% performance improvment. This is important as required changes to the
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M3 workaround will make it more costly.
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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diff --git a/arch/mips/include/asm/mach-sibyte/war.h b/arch/mips/include/asm/mach-sibyte/war.h
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index 7950ef4..743385d 100644
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--- a/arch/mips/include/asm/mach-sibyte/war.h
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+++ b/arch/mips/include/asm/mach-sibyte/war.h
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@@ -16,7 +16,11 @@
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#if defined(CONFIG_SB1_PASS_1_WORKAROUNDS) || \
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defined(CONFIG_SB1_PASS_2_WORKAROUNDS)
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-#define BCM1250_M3_WAR 1
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+#ifndef __ASSEMBLY__
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+extern int sb1250_m3_workaround_needed(void);
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+#endif
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+
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+#define BCM1250_M3_WAR sb1250_m3_workaround_needed()
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#define SIBYTE_1956_WAR 1
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#else
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diff --git a/arch/mips/sibyte/sb1250/setup.c b/arch/mips/sibyte/sb1250/setup.c
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index 0444da1..92da315 100644
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--- a/arch/mips/sibyte/sb1250/setup.c
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+++ b/arch/mips/sibyte/sb1250/setup.c
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@@ -87,6 +87,21 @@ static int __init setup_bcm1250(void)
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return ret;
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}
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+int sb1250_m3_workaround_needed(void)
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+{
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+ switch (soc_type) {
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+ case K_SYS_SOC_TYPE_BCM1250:
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+ case K_SYS_SOC_TYPE_BCM1250_ALT:
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+ case K_SYS_SOC_TYPE_BCM1250_ALT2:
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+ case K_SYS_SOC_TYPE_BCM1125:
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+ case K_SYS_SOC_TYPE_BCM1125H:
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+ return soc_pass < K_SYS_REVISION_BCM1250_C0;
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+
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+ default:
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+ return 0;
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+ }
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+}
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+
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static int __init setup_bcm112x(void)
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{
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int ret = 0;
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commit 5808184f1b2fe06ef8a54a2b7fb1596d58098acf
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Author: Ralf Baechle <ralf@linux-mips.org>
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Date: Tue Mar 23 15:54:50 2010 +0100
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MIPS: uasm: Add OR instruction.
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This is needed for the fix of the M3 workaround.
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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diff --git a/arch/mips/mm/uasm.h b/arch/mips/mm/uasm.h
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index 32fe2ec..11a8b52 100644
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--- a/arch/mips/mm/uasm.h
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+++ b/arch/mips/mm/uasm.h
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@@ -84,6 +84,7 @@ Ip_u2s3u1(_lw);
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Ip_u1u2u3(_mfc0);
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Ip_u1u2u3(_mtc0);
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Ip_u2u1u3(_ori);
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+Ip_u3u1u2(_or);
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Ip_u2s3u1(_pref);
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Ip_0(_rfe);
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Ip_u2s3u1(_sc);
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diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c
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index d22d7bc..611d564 100644
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--- a/arch/mips/mm/uasm.c
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+++ b/arch/mips/mm/uasm.c
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@@ -62,7 +62,7 @@
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insn_dmtc0, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl,
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insn_dsrl32, insn_dsubu, insn_eret, insn_j, insn_jal, insn_jr,
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insn_ld, insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0,
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- insn_mtc0, insn_ori, insn_pref, insn_rfe, insn_sc, insn_scd,
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+ insn_mtc0, insn_or, insn_ori, insn_pref, insn_rfe, insn_sc, insn_scd,
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insn_sd, insn_sll, insn_sra, insn_srl, insn_subu, insn_sw,
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insn_tlbp, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori
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};
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@@ -120,6 +120,7 @@ static struct insn insn_table[] __cpuinitdata = {
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{ insn_lw, M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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{ insn_mfc0, M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET},
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{ insn_mtc0, M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET},
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+ { insn_or, M(spec_op, 0, 0, 0, 0, or_op), RS | RT | RD },
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{ insn_ori, M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
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{ insn_pref, M(pref_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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{ insn_rfe, M(cop0_op, cop_op, 0, 0, 0, rfe_op), 0 },
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@@ -387,6 +388,7 @@ I_u2s3u1(_lw)
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I_u1u2u3(_mfc0)
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I_u1u2u3(_mtc0)
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I_u2u1u3(_ori)
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+I_u3u1u2(_or)
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I_u2s3u1(_pref)
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I_0(_rfe)
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I_u2s3u1(_sc)
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commit 3d45285dd1ff4d4a1361b95e2d6508579a4402b5
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Author: Ralf Baechle <ralf@linux-mips.org>
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Date: Tue Mar 23 17:56:38 2010 +0100
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MIPS: Sibyte: Fix M3 TLB exception handler workaround.
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The M3 workaround needs to cmpare the region and VPN2 fields only.
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
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index 0de0e41..d1f68aa 100644
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--- a/arch/mips/mm/tlbex.c
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+++ b/arch/mips/mm/tlbex.c
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@@ -788,10 +788,15 @@ static void __cpuinit build_r4000_tlb_refill_handler(void)
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* create the plain linear handler
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*/
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if (bcm1250_m3_war()) {
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- UASM_i_MFC0(&p, K0, C0_BADVADDR);
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- UASM_i_MFC0(&p, K1, C0_ENTRYHI);
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+ unsigned int segbits = 44;
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+
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+ uasm_i_dmfc0(&p, K0, C0_BADVADDR);
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+ uasm_i_dmfc0(&p, K1, C0_ENTRYHI);
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uasm_i_xor(&p, K0, K0, K1);
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- UASM_i_SRL(&p, K0, K0, PAGE_SHIFT + 1);
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+ uasm_i_dsrl32(&p, K1, K0, 62 - 32);
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+ uasm_i_dsrl(&p, K0, K0, 12 + 1);
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+ uasm_i_dsll32(&p, K0, K0, 64 + 12 + 1 - segbits - 32);
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+ uasm_i_or(&p, K0, K0, K1);
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uasm_il_bnez(&p, &r, K0, label_leave);
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/* No need for uasm_i_nop */
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}
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@@ -1312,10 +1317,15 @@ static void __cpuinit build_r4000_tlb_load_handler(void)
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memset(relocs, 0, sizeof(relocs));
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if (bcm1250_m3_war()) {
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- UASM_i_MFC0(&p, K0, C0_BADVADDR);
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- UASM_i_MFC0(&p, K1, C0_ENTRYHI);
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+ unsigned int segbits = 44;
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+
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+ uasm_i_dmfc0(&p, K0, C0_BADVADDR);
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+ uasm_i_dmfc0(&p, K1, C0_ENTRYHI);
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uasm_i_xor(&p, K0, K0, K1);
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- UASM_i_SRL(&p, K0, K0, PAGE_SHIFT + 1);
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+ uasm_i_dsrl32(&p, K1, K0, 62 - 32);
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+ uasm_i_dsrl(&p, K0, K0, 12 + 1);
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+ uasm_i_dsll32(&p, K0, K0, 64 + 12 + 1 - segbits - 32);
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+ uasm_i_or(&p, K0, K0, K1);
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uasm_il_bnez(&p, &r, K0, label_leave);
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/* No need for uasm_i_nop */
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}
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@ -9,3 +9,4 @@
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+ features/all/rtl8192su-add-Support-for-Belkin-F5D8053-v6.patch
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+ features/all/rtl8192su-Add-Sitecom-WL-349.patch
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+ bugfix/mips/mips-ide-flush-dcache.patch
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+ bugfix/mips/sibyte-m3-tlb-exception.patch
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