[armhf] Fixup cache maintenance during boot time relocation.
Fixes boot on various platforms. svn path=/dists/sid/linux/; revision=22102
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Ian Campbell
parent
13c48296be
commit
34264d5fa9
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@ -132,6 +132,8 @@ linux (3.16.7-ckt1-1) UNRELEASED; urgency=medium
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* [device-tree] Reserve memreserve regions even if they partially overlap
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with an existing reservation. Fixes boot on Midway.
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* [arm64] Enable reboot on the Xgene platform.
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* [armhf] Fixup cache maintenance during boot time relocation. Fixes boot on
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various platforms.
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-- Ben Hutchings <ben@decadent.org.uk> Sun, 09 Nov 2014 10:13:09 +0000
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@ -0,0 +1,112 @@
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From 238962ac71910d6c20162ea5230685fead1836a4 Mon Sep 17 00:00:00 2001
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From: Will Deacon <will.deacon@arm.com>
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Date: Tue, 4 Nov 2014 11:40:46 +0100
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Subject: [PATCH] ARM: 8191/1: decompressor: ensure I-side picks up relocated
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code
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Origin: https://git.kernel.org/linus/238962ac71910d6c20162ea5230685fead1836a4
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To speed up decompression, the decompressor sets up a flat, cacheable
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mapping of memory. However, when there is insufficient space to hold
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the page tables for this mapping, we don't bother to enable the caches
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and subsequently skip all the cache maintenance hooks.
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Skipping the cache maintenance before jumping to the relocated code
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allows the processor to predict the branch and populate the I-cache
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with stale data before the relocation loop has completed (since a
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bootloader may have SCTLR.I set, which permits normal, cacheable
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instruction fetches regardless of SCTLR.M).
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This patch moves the cache maintenance check into the maintenance
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routines themselves, allowing the v6/v7 versions to invalidate the
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I-cache regardless of the MMU state.
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Cc: <stable@vger.kernel.org>
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Reported-by: Marc Carino <marc.ceeeee@gmail.com>
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Tested-by: Julien Grall <julien.grall@linaro.org>
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Signed-off-by: Will Deacon <will.deacon@arm.com>
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Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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---
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arch/arm/boot/compressed/head.S | 20 ++++++++++++++++----
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1 file changed, 16 insertions(+), 4 deletions(-)
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diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
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index 413fd94..68be901 100644
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--- a/arch/arm/boot/compressed/head.S
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+++ b/arch/arm/boot/compressed/head.S
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@@ -397,8 +397,7 @@ dtb_check_done:
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add sp, sp, r6
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#endif
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- tst r4, #1
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- bleq cache_clean_flush
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+ bl cache_clean_flush
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adr r0, BSYM(restart)
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add r0, r0, r6
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@@ -1047,6 +1046,8 @@ cache_clean_flush:
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b call_cache_fn
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__armv4_mpu_cache_flush:
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+ tst r4, #1
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+ movne pc, lr
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mov r2, #1
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mov r3, #0
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mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
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@@ -1064,6 +1065,8 @@ __armv4_mpu_cache_flush:
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mov pc, lr
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__fa526_cache_flush:
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+ tst r4, #1
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+ movne pc, lr
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mov r1, #0
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mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache
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mcr p15, 0, r1, c7, c5, 0 @ flush I cache
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@@ -1072,13 +1075,16 @@ __fa526_cache_flush:
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__armv6_mmu_cache_flush:
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mov r1, #0
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- mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D
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+ tst r4, #1
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+ mcreq p15, 0, r1, c7, c14, 0 @ clean+invalidate D
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mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
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- mcr p15, 0, r1, c7, c15, 0 @ clean+invalidate unified
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+ mcreq p15, 0, r1, c7, c15, 0 @ clean+invalidate unified
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mcr p15, 0, r1, c7, c10, 4 @ drain WB
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mov pc, lr
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__armv7_mmu_cache_flush:
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+ tst r4, #1
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+ bne iflush
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mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
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tst r10, #0xf << 16 @ hierarchical cache (ARMv7)
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mov r10, #0
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@@ -1139,6 +1145,8 @@ iflush:
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mov pc, lr
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__armv5tej_mmu_cache_flush:
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+ tst r4, #1
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+ movne pc, lr
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1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache
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bne 1b
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mcr p15, 0, r0, c7, c5, 0 @ flush I cache
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@@ -1146,6 +1154,8 @@ __armv5tej_mmu_cache_flush:
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mov pc, lr
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__armv4_mmu_cache_flush:
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+ tst r4, #1
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+ movne pc, lr
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mov r2, #64*1024 @ default: 32K dcache size (*2)
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mov r11, #32 @ default: 32 byte line size
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mrc p15, 0, r3, c0, c0, 1 @ read cache type
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@@ -1179,6 +1189,8 @@ no_cache_id:
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__armv3_mmu_cache_flush:
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__armv3_mpu_cache_flush:
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+ tst r4, #1
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+ movne pc, lr
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mov r1, #0
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mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3
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mov pc, lr
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--
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2.1.3
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@ -60,6 +60,7 @@ bugfix/x86/drm-i915-Add-some-L3-registers-to-the-parser-whiteli.patch
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bugfix/parisc/parisc-reduce-sigrtmin-from-37-to-32-to-behave-like-.patch
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bugfix/arm64/arm64-add-missing-dts-entry-for-X-Gene-platform.patch
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bugfix/arm64/arm64-removed-using-of-the-mask-attribute-in-the-dts.patch
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bugfix/arm/decompressor-ensure-I-side-picks-up-reloc.patch
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# Arch features
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features/mips/MIPS-Support-hard-limit-of-cpu-count-nr_cpu_ids.patch
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