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open 2.6.29-4 with drm fix 

make sure it makes it for next release,
although  most probably will be in 2.6.29.2.

Reported-by: Yves-Alexis Perez <corsac@debian.org>

svn path=/dists/sid/linux-2.6/; revision=13434
This commit is contained in:
Maximilian Attems 2009-04-17 09:33:00 +00:00
parent a4aa1d658d
commit 3121cb2329
3 changed files with 72 additions and 0 deletions
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6
debian/changelog vendored
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@ -1,3 +1,9 @@
linux-2.6 (2.6.29-4) unstable; urgency=low
* drm/i915: allow tiled front buffers on 965+.
-- maximilian attems <maks@debian.org> Fri, 17 Apr 2009 11:30:55 +0200
linux-2.6 (2.6.29-3) unstable; urgency=low
[ maximilian attems ]

65
debian/patches/bugfix/all/drm-intel.git-f544847fbaf099278343f875987a983f2b913134.patch vendored Normal file
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From: Jesse Barnes <jbarnes@virtuousgeek.org>
Date: Tue, 14 Apr 2009 21:17:47 +0000 (-0700)
Subject: drm/i915: allow tiled front buffers on 965+
X-Git-Url: http://git.kernel.org/?p=linux%2Fkernel%2Fgit%2Fanholt%2Fdrm-intel.git;a=commitdiff_plain;h=f544847fbaf099278343f875987a983f2b913134;hp=cd97824994042b809493807ea644ba26c0c23290
drm/i915: allow tiled front buffers on 965+
This patch corrects a pretty big oversight in the KMS code for 965+
chips. The current code is missing tiled surface register programming,
so userland can allocate a tiled surface and use it for mode setting,
resulting in corruption. This patch fixes that, allowing for tiled
front buffers on 965+.
Cc: stable@kernel.org
Tested-by: Arkadiusz Miskiewicz <arekm@maven.pl>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
---
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e805b59..5211947 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1446,6 +1446,7 @@
#define DISPPLANE_NO_LINE_DOUBLE 0
#define DISPPLANE_STEREO_POLARITY_FIRST 0
#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
+#define DISPPLANE_TILED (1<<10)
#define DSPAADDR 0x70184
#define DSPASTRIDE 0x70188
#define DSPAPOS 0x7018C /* reserved */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c2c8e95..bdcda36 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -657,6 +657,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
int dspbase = (pipe == 0 ? DSPAADDR : DSPBADDR);
int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF);
int dspstride = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE;
+ int dsptileoff = (pipe == 0 ? DSPATILEOFF : DSPBTILEOFF);
int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
u32 dspcntr, alignment;
int ret;
@@ -733,6 +734,13 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
mutex_unlock(&dev->struct_mutex);
return -EINVAL;
}
+ if (IS_I965G(dev)) {
+ if (obj_priv->tiling_mode != I915_TILING_NONE)
+ dspcntr |= DISPPLANE_TILED;
+ else
+ dspcntr &= ~DISPPLANE_TILED;
+ }
+
I915_WRITE(dspcntr_reg, dspcntr);
Start = obj_priv->gtt_offset;
@@ -745,6 +753,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
I915_READ(dspbase);
I915_WRITE(dspsurf, Start);
I915_READ(dspsurf);
+ I915_WRITE(dsptileoff, (y << 16) | x);
} else {
I915_WRITE(dspbase, Start + Offset);
I915_READ(dspbase);

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+ bugfix/all/drm-intel.git-f544847fbaf099278343f875987a983f2b913134.patch