Readded powerpc-g4-l2-flush-errata.patch after cleanup.
svn path=/trunk/kernel/source/linux-2.6-2.6.12/; revision=3552
This commit is contained in:
Sven Luther
parent
3f9f73d660
commit
2b15000a31
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@ -100,6 +100,7 @@ linux-2.6 (2.6.12-1) UNRELEASED; urgency=low
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it and thinks it is not needed.
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- Disabled swim3 on powerpc-smp, FTBFS.
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- Disabled software-suspend on powerpc-smp, FTBFS, amd64/i386 only smp code.
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- Rediffed and readded the G4 L2 hardware flush assist patch from Jacob Pan.
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(Sven Luther)
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-- Joshua Kwan <joshk@triplehelix.org> Sat, 16 Jul 2005 05:54:16 +0300
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@ -0,0 +1,243 @@
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# Description: Fixes g4 l2 cache flush and MSR erratas.
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# Patch author: Jacob Pan.
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# Rediffed for 2.6.12 by Sven Luther <luther@debian.org>
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# Upstream status: under review by benh.
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. $(dirname $0)/DPATCH
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@DPATCH@
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--- linux-kernel-2.6.12-2.6.12/./arch/ppc/kernel/cputable.c.orig 2005-06-17 19:48:29.000000000 +0000
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+++ linux-kernel-2.6.12-2.6.12/./arch/ppc/kernel/cputable.c 2005-07-16 12:09:33.000000000 +0000
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@@ -380,7 +380,7 @@
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CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
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CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
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CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
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- CPU_FTR_NEED_COHERENT,
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+ CPU_FTR_NEED_COHERENT | CPU_FTR_HWFLUSH_L2_CACHE,
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.cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
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.icache_bsize = 32,
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.dcache_bsize = 32,
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@@ -397,7 +397,7 @@
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CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
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CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
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CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
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- CPU_FTR_NEED_COHERENT,
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+ CPU_FTR_NEED_COHERENT | CPU_FTR_HWFLUSH_L2_CACHE,
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.cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
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.icache_bsize = 32,
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.dcache_bsize = 32,
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@@ -413,7 +413,8 @@
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CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
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CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
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CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
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- CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT,
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+ CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT |
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+ CPU_FTR_HWFLUSH_L2_CACHE,
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.cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
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.icache_bsize = 32,
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.dcache_bsize = 32,
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@@ -428,7 +429,8 @@
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CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
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CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
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CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
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- CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
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+ CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT |
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+ CPU_FTR_HWFLUSH_L2_CACHE,
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.cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
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.icache_bsize = 32,
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.dcache_bsize = 32,
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@@ -445,7 +447,8 @@
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CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
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CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
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CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
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- CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS,
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+ CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS |
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+ CPU_FTR_HWFLUSH_L2_CACHE,
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.cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
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.icache_bsize = 32,
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.dcache_bsize = 32,
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@@ -462,7 +465,7 @@
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CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
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CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
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CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
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- CPU_FTR_NEED_COHERENT,
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+ CPU_FTR_NEED_COHERENT | CPU_FTR_HWFLUSH_L2_CACHE,
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.cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
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.icache_bsize = 32,
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.dcache_bsize = 32,
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@@ -479,7 +482,8 @@
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CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
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CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
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CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
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- CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
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+ CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC |
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+ CPU_FTR_HWFLUSH_L2_CACHE,
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.cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
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.icache_bsize = 32,
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.dcache_bsize = 32,
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@@ -496,7 +500,8 @@
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CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
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CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
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CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
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- CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
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+ CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC |
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+ CPU_FTR_HWFLUSH_L2_CACHE,
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.cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
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.icache_bsize = 32,
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.dcache_bsize = 32,
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@@ -513,7 +518,7 @@
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CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
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CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
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CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
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- CPU_FTR_NEED_COHERENT,
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+ CPU_FTR_NEED_COHERENT CPU_FTR_HWFLUSH_L2_CACHE,
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.cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
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.icache_bsize = 32,
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.dcache_bsize = 32,
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@@ -529,7 +534,8 @@
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CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
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CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
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CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
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- CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
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+ CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT |
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+ CPU_FTR_HWFLUSH_L2_CACHE,
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.cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
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.icache_bsize = 32,
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.dcache_bsize = 32,
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@@ -537,7 +543,7 @@
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.cpu_setup = __setup_cpu_745x
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},
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{ /* 82xx (8240, 8245, 8260 are all 603e cores) */
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- .pvr_mask = 0x7fff0000,
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+ .pvr_mask = 0x7fff0000,
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.pvr_value = 0x00810000,
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.cpu_name = "82xx",
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.cpu_features = CPU_FTR_COMMON |
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--- linux-kernel-2.6.12-2.6.12/./arch/ppc/kernel/l2cr.S.orig 2005-06-17 19:48:29.000000000 +0000
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+++ linux-kernel-2.6.12-2.6.12/./arch/ppc/kernel/l2cr.S 2005-07-16 11:50:39.000000000 +0000
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@@ -36,7 +36,9 @@
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several months. The L2CR is similar, but I'm going
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to assume the user of this functions knows what they
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are doing.
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-
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+ June 17, 2004.
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+ - JPAN: Fixed 745X L3 cache enablement routine, also use HW flush assist.
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+
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Author: Terry Greeniaus (tgree@phys.ualberta.ca)
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Please e-mail updates to this file to me, thanks!
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*/
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@@ -155,9 +157,7 @@
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Don't do this unless you accomodate all processor variations.
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The bit moved on the 7450.....
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****/
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-
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- /* TODO: use HW flush assist when available */
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-
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+BEGIN_FTR_SECTION
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lis r4,0x0002
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mtctr r4
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li r4,0
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@@ -176,7 +176,23 @@
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dcbf 0,r4
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addi r4,r4,32 /* Go to start of next cache line */
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bdnz 1b
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+END_FTR_SECTION_IFCLR(CPU_FTR_HWFLUSH_L2_CACHE)
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+BEGIN_FTR_SECTION
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+ /* Use HW flush assist, MPC7447A errata #3 */
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+ oris r4,r4,0x0010 /* Set L2CR[IONLY/11] = 1 */
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+ oris r4,r4,0x0001 /* Set L2CR[DONLY/15] = 1 */
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+ mtspr L2CR,r4 /* Lock the L2 */
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+ sync
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+ ori r4,r4,0x0800 /* Set L2CR[L2HWF/20] = 1 */
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+ mtspr L2CR,r4 /* Flush the L2 */
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+1:
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+ mfspr r4,L2CR
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+ andi. r4,r4,0x0800 /* L2HWF still set? */
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+ bne 1b
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+ sync /* sync to clear the store queues before L3 flush (UM step 5)*/
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+END_FTR_SECTION_IFSET(CPU_FTR_HWFLUSH_L2_CACHE)
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+
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2:
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/* Set up the L2CR configuration bits (and switch L2 off) */
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/* CPU errata: Make sure the mtspr below is already in the
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@@ -293,17 +309,18 @@
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/* Flush the cache.
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*/
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-
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- /* TODO: use HW flush assist */
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-
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- lis r4,0x0008
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- mtctr r4
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- li r4,0
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-1:
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- lwzx r0,r0,r4
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- dcbf 0,r4
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- addi r4,r4,32 /* Go to start of next cache line */
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- bdnz 1b
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+ /* use HW flush assist. (UM 3.6.3.1.5) */
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+ mfspr r4, SPRN_L3CR
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+ oris r4,r4,0x0040 /* Set L3CR[L3IO/9] = 1. */
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+ ori r4,r4,0x0040 /* Set L3CR[L3DO/29] = 1.*/
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+ mtspr 1018,r4 /* Lock the L3 by making IONLY and DONLY */
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+ ori r4,r4,0x0800 /* Set L3CR[L3HWF/20] for hardware flush */
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+ mtspr SPRN_L3CR,r4
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+flush_745x_L3_poll:
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+ mfspr r4,SPRN_L3CR
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+ rlwinm. r4,r4,0,20,20
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+ bne flush_745x_L3_poll
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+ sync /* Clear the store queues per procedure (UM step 8) */
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2:
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/* Set up the L3CR configuration bits (and switch L3 off) */
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@@ -349,8 +366,8 @@
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cmplwi r5,0
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beq 4f
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- /* Enable the cache */
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- oris r3,r3,(L3CR_L3E | L3CR_L3CLKEN)@h
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+ /* enable L3 clock */
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+ oris r3,r3,(L3CR_L3CLKEN)@h
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mtspr SPRN_L3CR,r3
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sync
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@@ -358,6 +375,15 @@
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li r0,256
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mtctr r0
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1: bdnz 1b
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+
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+ /* Clear MSSSR0 which may cause parity error */
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+ xor r5,r5,r5
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+ mtspr 1015, r5
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+
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+ /* Enable L3 cache */
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+ oris r3,r3,(L3CR_L3E)@h
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+ mtspr SPRN_L3CR,r3
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+ sync
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/* Restore MSR (restores EE and DR bits to original state) */
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4: SYNC
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--- linux-kernel-2.6.12-2.6.12/./arch/ppc/kernel/traps.c.orig 2005-06-17 19:48:29.000000000 +0000
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+++ linux-kernel-2.6.12-2.6.12/./arch/ppc/kernel/traps.c 2005-07-16 11:50:39.000000000 +0000
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@@ -307,7 +307,9 @@
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case 0x80000:
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printk("Machine check signal\n");
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break;
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- case 0: /* for 601 */
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+ case 0: /* for 601 and 744x */
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+ printk("Transfer error ack signal if 601, or MCP if 744x \n");
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+ break;
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case 0x40000:
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case 0x140000: /* 7450 MSS error and TEA */
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printk("Transfer error ack signal\n");
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--- linux-kernel-2.6.12-2.6.12/./include/asm-ppc/cputable.h.orig 2005-06-17 19:48:29.000000000 +0000
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+++ linux-kernel-2.6.12-2.6.12/./include/asm-ppc/cputable.h 2005-07-16 11:52:01.000000000 +0000
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@@ -89,6 +89,7 @@
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#define CPU_FTR_NEED_COHERENT 0x00020000
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#define CPU_FTR_NO_BTIC 0x00040000
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#define CPU_FTR_BIG_PHYS 0x00080000
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+#define CPU_FTR_HWFLUSH_L2_CACHE 0x00100000
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#ifdef __ASSEMBLY__
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@ -24,3 +24,4 @@
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+ powerpc-mkvmlinuz-support.patch
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+ patch-2.6.12.3
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+ sparc64-hme-lockup.patch
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+ powerpc-g4-l2-flush-errata.dpatch
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