diff --git a/debian/changelog b/debian/changelog
index eff67c1eb..0c0ada1d3 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -100,6 +100,11 @@ linux (3.2.41-1) UNRELEASED; urgency=low
     - kexec: remove KMSG_DUMP_KEXEC
     - kmsg_dump: don't run on non-error paths by default
   * [x86] i915: initialize CADL in opregion (Closes: #703271)
+  * drm, agp: Update to 3.4.37:
+    - drm/radeon/dce6: fix display powergating
+    - drm: don't add inferred modes for monitors that don't support them
+    - drm/i915: EBUSY status handling added to i915_gem_fault().
+    - drm/i915: Increase the RC6p threshold.
 
  -- Ben Hutchings <ben@decadent.org.uk>  Wed, 27 Feb 2013 03:48:30 +0000
 
diff --git a/debian/patches/features/all/drm/drm-3.4.patch b/debian/patches/features/all/drm/drm-3.4.patch
index 47740fac3..5d13db0e4 100644
--- a/debian/patches/features/all/drm/drm-3.4.patch
+++ b/debian/patches/features/all/drm/drm-3.4.patch
@@ -351,7 +351,7 @@ index 6d440fb..325365f 100644
  		return -EINVAL;
  
 diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
-index 3f1799b..4fd363f 100644
+index 3f1799b..c61e672 100644
 --- a/drivers/gpu/drm/drm_crtc.c
 +++ b/drivers/gpu/drm/drm_crtc.c
 @@ -36,11 +36,7 @@
@@ -1373,7 +1373,7 @@ index 3f1799b..4fd363f 100644
 +
 +	switch (bpp) {
 +	case 8:
-+		fmt = DRM_FORMAT_RGB332;
++		fmt = DRM_FORMAT_C8;
 +		break;
 +	case 16:
 +		if (depth == 15)
@@ -1923,7 +1923,7 @@ index 3f1799b..4fd363f 100644
  	}
  
  out:
-@@ -2777,3 +3400,71 @@ int drm_mode_destroy_dumb_ioctl(struct drm_device *dev,
+@@ -2777,3 +3400,72 @@ int drm_mode_destroy_dumb_ioctl(struct drm_device *dev,
  
  	return dev->driver->dumb_destroy(file_priv, dev, args->handle);
  }
@@ -1936,6 +1936,7 @@ index 3f1799b..4fd363f 100644
 +			  int *bpp)
 +{
 +	switch (format) {
++	case DRM_FORMAT_C8:
 +	case DRM_FORMAT_RGB332:
 +	case DRM_FORMAT_BGR233:
 +		*depth = 8;
@@ -2237,7 +2238,7 @@ index 40c187c..6116e3b 100644
  	atomic_inc(&dev->counts[_DRM_STAT_IOCTLS]);
  	++file_priv->ioctl_count;
 diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
-index 9080eb7..9d9835a 100644
+index 9080eb7..384edc6 100644
 --- a/drivers/gpu/drm/drm_edid.c
 +++ b/drivers/gpu/drm/drm_edid.c
 @@ -154,8 +154,7 @@ EXPORT_SYMBOL(drm_edid_header_is_valid);
@@ -2408,13 +2409,10 @@ index 9080eb7..9d9835a 100644
  	eld[5] |= sad_count << 4;
  	eld[2] = (20 + mnl + sad_count * 3 + 3) / 4;
  
-@@ -1740,8 +1769,8 @@ int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
- 	num_modes += add_cvt_modes(connector, edid);
- 	num_modes += add_standard_modes(connector, edid);
+@@ -1742,6 +1771,7 @@ int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
  	num_modes += add_established_modes(connector, edid);
--	if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
--		num_modes += add_inferred_modes(connector, edid);
-+	num_modes += add_inferred_modes(connector, edid);
+ 	if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
+ 		num_modes += add_inferred_modes(connector, edid);
 +	num_modes += add_cea_modes(connector, edid);
  
  	if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
@@ -4310,7 +4308,7 @@ index 0f9ef9b..5a7bd51 100644
  
  
 diff --git a/drivers/gpu/drm/drm_usb.c b/drivers/gpu/drm/drm_usb.c
-index 471f453..37c9a52 100644
+index 471f453..767782a 100644
 --- a/drivers/gpu/drm/drm_usb.c
 +++ b/drivers/gpu/drm/drm_usb.c
 @@ -1,8 +1,7 @@
@@ -4323,15 +4321,6 @@ index 471f453..37c9a52 100644
  int drm_get_usb_dev(struct usb_interface *interface,
  		    const struct usb_device_id *id,
  		    struct drm_driver *driver)
-@@ -19,7 +18,7 @@ int drm_get_usb_dev(struct usb_interface *interface,
- 
- 	usbdev = interface_to_usbdev(interface);
- 	dev->usbdev = usbdev;
--	dev->dev = &interface->dev;
-+	dev->dev = &usbdev->dev;
- 
- 	mutex_lock(&drm_global_mutex);
- 
 @@ -115,4 +114,7 @@ void drm_usb_exit(struct drm_driver *driver,
  	usb_deregister(udriver);
  }
@@ -44481,7 +44470,7 @@ index 012a9d2..45c5cf8 100644
  #define __i915_read(x, y) \
  	u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
 diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
-index b0186b8..a230a93 100644
+index b0186b8..eb33945 100644
 --- a/drivers/gpu/drm/i915/i915_gem.c
 +++ b/drivers/gpu/drm/i915/i915_gem.c
 @@ -58,6 +58,7 @@ static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj);
@@ -44990,19 +44979,7 @@ index b0186b8..a230a93 100644
  	drm_gem_object_unreference_unlocked(obj);
  	if (IS_ERR((void *)addr))
  		return addr;
-@@ -1259,11 +1186,6 @@ out:
- 	case 0:
- 	case -ERESTARTSYS:
- 	case -EINTR:
--	case -EBUSY:
--		/*
--		 * EBUSY is ok: this just means that another thread
--		 * already did the job.
--		 */
- 		return VM_FAULT_NOPAGE;
- 	case -ENOMEM:
- 		return VM_FAULT_OOM;
-@@ -1687,12 +1609,20 @@ i915_add_request(struct intel_ring_buffer *ring,
+@@ -1687,12 +1614,20 @@ i915_add_request(struct intel_ring_buffer *ring,
  {
  	drm_i915_private_t *dev_priv = ring->dev->dev_private;
  	uint32_t seqno;
@@ -45023,7 +45000,7 @@ index b0186b8..a230a93 100644
  	ret = ring->add_request(ring, &seqno);
  	if (ret)
  	    return ret;
-@@ -1701,6 +1631,7 @@ i915_add_request(struct intel_ring_buffer *ring,
+@@ -1701,6 +1636,7 @@ i915_add_request(struct intel_ring_buffer *ring,
  
  	request->seqno = seqno;
  	request->ring = ring;
@@ -45031,7 +45008,7 @@ index b0186b8..a230a93 100644
  	request->emitted_jiffies = jiffies;
  	was_empty = list_empty(&ring->request_list);
  	list_add_tail(&request->list, &ring->request_list);
-@@ -1715,7 +1646,7 @@ i915_add_request(struct intel_ring_buffer *ring,
+@@ -1715,7 +1651,7 @@ i915_add_request(struct intel_ring_buffer *ring,
  		spin_unlock(&file_priv->mm.lock);
  	}
  
@@ -45040,7 +45017,7 @@ index b0186b8..a230a93 100644
  
  	if (!dev_priv->mm.suspended) {
  		if (i915_enable_hangcheck) {
-@@ -1837,7 +1768,7 @@ void i915_gem_reset(struct drm_device *dev)
+@@ -1837,7 +1773,7 @@ void i915_gem_reset(struct drm_device *dev)
  /**
   * This function clears the request list as sequence numbers are passed.
   */
@@ -45049,7 +45026,7 @@ index b0186b8..a230a93 100644
  i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
  {
  	uint32_t seqno;
-@@ -1865,6 +1796,12 @@ i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
+@@ -1865,6 +1801,12 @@ i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
  			break;
  
  		trace_i915_gem_request_retire(ring, request->seqno);
@@ -45062,7 +45039,7 @@ index b0186b8..a230a93 100644
  
  		list_del(&request->list);
  		i915_gem_request_remove_from_client(request);
-@@ -1977,7 +1914,8 @@ i915_gem_retire_work_handler(struct work_struct *work)
+@@ -1977,7 +1919,8 @@ i915_gem_retire_work_handler(struct work_struct *work)
   */
  int
  i915_wait_request(struct intel_ring_buffer *ring,
@@ -45072,7 +45049,7 @@ index b0186b8..a230a93 100644
  {
  	drm_i915_private_t *dev_priv = ring->dev->dev_private;
  	u32 ier;
-@@ -2040,9 +1978,9 @@ i915_wait_request(struct intel_ring_buffer *ring,
+@@ -2040,9 +1983,9 @@ i915_wait_request(struct intel_ring_buffer *ring,
  					   || atomic_read(&dev_priv->mm.wedged));
  
  			ring->irq_put(ring);
@@ -45085,7 +45062,7 @@ index b0186b8..a230a93 100644
  			ret = -EBUSY;
  		ring->waiting_seqno = 0;
  
-@@ -2051,17 +1989,12 @@ i915_wait_request(struct intel_ring_buffer *ring,
+@@ -2051,17 +1994,12 @@ i915_wait_request(struct intel_ring_buffer *ring,
  	if (atomic_read(&dev_priv->mm.wedged))
  		ret = -EAGAIN;
  
@@ -45104,7 +45081,7 @@ index b0186b8..a230a93 100644
  		i915_gem_retire_requests_ring(ring);
  
  	return ret;
-@@ -2085,7 +2018,8 @@ i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj)
+@@ -2085,7 +2023,8 @@ i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj)
  	 * it.
  	 */
  	if (obj->active) {
@@ -45114,7 +45091,7 @@ index b0186b8..a230a93 100644
  		if (ret)
  			return ret;
  	}
-@@ -2123,6 +2057,7 @@ static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
+@@ -2123,6 +2062,7 @@ static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
  int
  i915_gem_object_unbind(struct drm_i915_gem_object *obj)
  {
@@ -45122,7 +45099,7 @@ index b0186b8..a230a93 100644
  	int ret = 0;
  
  	if (obj->gtt_space == NULL)
-@@ -2167,6 +2102,11 @@ i915_gem_object_unbind(struct drm_i915_gem_object *obj)
+@@ -2167,6 +2107,11 @@ i915_gem_object_unbind(struct drm_i915_gem_object *obj)
  	trace_i915_gem_object_unbind(obj);
  
  	i915_gem_gtt_unbind_object(obj);
@@ -45134,7 +45111,7 @@ index b0186b8..a230a93 100644
  	i915_gem_object_put_pages_gtt(obj);
  
  	list_del_init(&obj->gtt_list);
-@@ -2206,7 +2146,7 @@ i915_gem_flush_ring(struct intel_ring_buffer *ring,
+@@ -2206,7 +2151,7 @@ i915_gem_flush_ring(struct intel_ring_buffer *ring,
  	return 0;
  }
  
@@ -45143,7 +45120,7 @@ index b0186b8..a230a93 100644
  {
  	int ret;
  
-@@ -2220,18 +2160,18 @@ static int i915_ring_idle(struct intel_ring_buffer *ring)
+@@ -2220,18 +2165,18 @@ static int i915_ring_idle(struct intel_ring_buffer *ring)
  			return ret;
  	}
  
@@ -45166,7 +45143,7 @@ index b0186b8..a230a93 100644
  		if (ret)
  			return ret;
  	}
-@@ -2434,7 +2374,8 @@ i915_gem_object_flush_fence(struct drm_i915_gem_object *obj,
+@@ -2434,7 +2379,8 @@ i915_gem_object_flush_fence(struct drm_i915_gem_object *obj,
  		if (!ring_passed_seqno(obj->last_fenced_ring,
  				       obj->last_fenced_seqno)) {
  			ret = i915_wait_request(obj->last_fenced_ring,
@@ -45176,7 +45153,7 @@ index b0186b8..a230a93 100644
  			if (ret)
  				return ret;
  		}
-@@ -2466,6 +2407,8 @@ i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
+@@ -2466,6 +2412,8 @@ i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
  
  	if (obj->fence_reg != I915_FENCE_REG_NONE) {
  		struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
@@ -45185,7 +45162,7 @@ index b0186b8..a230a93 100644
  		i915_gem_clear_fence_reg(obj->base.dev,
  					 &dev_priv->fence_regs[obj->fence_reg]);
  
-@@ -2490,7 +2433,7 @@ i915_find_fence_reg(struct drm_device *dev,
+@@ -2490,7 +2438,7 @@ i915_find_fence_reg(struct drm_device *dev,
  		if (!reg->obj)
  			return reg;
  
@@ -45194,7 +45171,7 @@ index b0186b8..a230a93 100644
  			avail = reg;
  	}
  
-@@ -2500,7 +2443,7 @@ i915_find_fence_reg(struct drm_device *dev,
+@@ -2500,7 +2448,7 @@ i915_find_fence_reg(struct drm_device *dev,
  	/* None available, try to steal one or wait for a user to finish */
  	avail = first = NULL;
  	list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
@@ -45203,7 +45180,7 @@ index b0186b8..a230a93 100644
  			continue;
  
  		if (first == NULL)
-@@ -2575,7 +2518,8 @@ i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
+@@ -2575,7 +2523,8 @@ i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
  				if (!ring_passed_seqno(obj->last_fenced_ring,
  						       reg->setup_seqno)) {
  					ret = i915_wait_request(obj->last_fenced_ring,
@@ -45213,7 +45190,7 @@ index b0186b8..a230a93 100644
  					if (ret)
  						return ret;
  				}
-@@ -2594,7 +2538,7 @@ i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
+@@ -2594,7 +2543,7 @@ i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
  
  	reg = i915_find_fence_reg(dev, pipelined);
  	if (reg == NULL)
@@ -45222,7 +45199,7 @@ index b0186b8..a230a93 100644
  
  	ret = i915_gem_object_flush_fence(obj, pipelined);
  	if (ret)
-@@ -2694,6 +2638,7 @@ i915_gem_clear_fence_reg(struct drm_device *dev,
+@@ -2694,6 +2643,7 @@ i915_gem_clear_fence_reg(struct drm_device *dev,
  	list_del_init(&reg->lru_list);
  	reg->obj = NULL;
  	reg->setup_seqno = 0;
@@ -45230,7 +45207,7 @@ index b0186b8..a230a93 100644
  }
  
  /**
-@@ -2980,6 +2925,8 @@ i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
+@@ -2980,6 +2930,8 @@ i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
  int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
  				    enum i915_cache_level cache_level)
  {
@@ -45239,7 +45216,7 @@ index b0186b8..a230a93 100644
  	int ret;
  
  	if (obj->cache_level == cache_level)
-@@ -3008,6 +2955,9 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
+@@ -3008,6 +2960,9 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
  		}
  
  		i915_gem_gtt_rebind_object(obj, cache_level);
@@ -45249,7 +45226,7 @@ index b0186b8..a230a93 100644
  	}
  
  	if (cache_level == I915_CACHE_NONE) {
-@@ -3346,8 +3296,8 @@ i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
+@@ -3346,8 +3301,8 @@ i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
  
  			if (ret == 0 && atomic_read(&dev_priv->mm.wedged))
  				ret = -EIO;
@@ -45260,7 +45237,7 @@ index b0186b8..a230a93 100644
  				    atomic_read(&dev_priv->mm.wedged), 3000)) {
  			ret = -EBUSY;
  		}
-@@ -3456,15 +3406,14 @@ i915_gem_pin_ioctl(struct drm_device *dev, void *data,
+@@ -3456,15 +3411,14 @@ i915_gem_pin_ioctl(struct drm_device *dev, void *data,
  		goto out;
  	}
  
@@ -45279,7 +45256,7 @@ index b0186b8..a230a93 100644
  	/* XXX - flush the CPU caches for pinned objects
  	 * as the X server doesn't manage domains yet
  	 */
-@@ -3658,8 +3607,8 @@ struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
+@@ -3658,8 +3612,8 @@ struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
  	obj->base.write_domain = I915_GEM_DOMAIN_CPU;
  	obj->base.read_domains = I915_GEM_DOMAIN_CPU;
  
@@ -45290,7 +45267,7 @@ index b0186b8..a230a93 100644
  		 * cache) for about a 10% performance improvement
  		 * compared to uncached.  Graphics requests other than
  		 * display scanout are coherent with the CPU in
-@@ -3749,7 +3698,7 @@ i915_gem_idle(struct drm_device *dev)
+@@ -3749,7 +3703,7 @@ i915_gem_idle(struct drm_device *dev)
  		return 0;
  	}
  
@@ -45299,7 +45276,7 @@ index b0186b8..a230a93 100644
  	if (ret) {
  		mutex_unlock(&dev->struct_mutex);
  		return ret;
-@@ -3784,12 +3733,91 @@ i915_gem_idle(struct drm_device *dev)
+@@ -3784,12 +3738,91 @@ i915_gem_idle(struct drm_device *dev)
  	return 0;
  }
  
@@ -45392,7 +45369,7 @@ index b0186b8..a230a93 100644
  	ret = intel_init_render_ring_buffer(dev);
  	if (ret)
  		return ret;
-@@ -3808,6 +3836,8 @@ i915_gem_init_ringbuffer(struct drm_device *dev)
+@@ -3808,6 +3841,8 @@ i915_gem_init_ringbuffer(struct drm_device *dev)
  
  	dev_priv->next_seqno = 1;
  
@@ -45401,7 +45378,7 @@ index b0186b8..a230a93 100644
  	return 0;
  
  cleanup_bsd_ring:
-@@ -3845,7 +3875,7 @@ i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
+@@ -3845,7 +3880,7 @@ i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
  	mutex_lock(&dev->struct_mutex);
  	dev_priv->mm.suspended = 0;
  
@@ -45410,7 +45387,7 @@ index b0186b8..a230a93 100644
  	if (ret != 0) {
  		mutex_unlock(&dev->struct_mutex);
  		return ret;
-@@ -4240,7 +4270,7 @@ rescan:
+@@ -4240,7 +4275,7 @@ rescan:
  		 * This has a dramatic impact to reduce the number of
  		 * OOM-killer events whilst running the GPU aggressively.
  		 */
@@ -47732,7 +47709,7 @@ index fee0ad0..342ffb7 100644
  
  	drm_encoder_helper_add(&crt->base.base, &intel_crt_helper_funcs);
 diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
-index 4591582..3c9b9c5 100644
+index 4591582..7ccf896 100644
 --- a/drivers/gpu/drm/i915/intel_display.c
 +++ b/drivers/gpu/drm/i915/intel_display.c
 @@ -75,7 +75,7 @@ struct intel_limit {
@@ -47770,17 +47747,6 @@ index 4591582..3c9b9c5 100644
  
  static inline u32 /* units of 100MHz */
  intel_fdi_link_freq(struct drm_device *dev)
-@@ -138,8 +142,8 @@ static const intel_limit_t intel_limits_i9xx_sdvo = {
- 	.vco = { .min = 1400000, .max = 2800000 },
- 	.n = { .min = 1, .max = 6 },
- 	.m = { .min = 70, .max = 120 },
--	.m1 = { .min = 8, .max = 18 },
--	.m2 = { .min = 3, .max = 7 },
-+	.m1 = { .min = 10, .max = 22 },
-+	.m2 = { .min = 5, .max = 9 },
- 	.p = { .min = 5, .max = 80 },
- 	.p1 = { .min = 1, .max = 8 },
- 	.p2 = { .dot_limit = 200000,
 @@ -534,7 +538,8 @@ static bool intel_PLL_is_valid(struct drm_device *dev,
  
  static bool
@@ -48079,29 +48045,7 @@ index 4591582..3c9b9c5 100644
  
  	intel_fdi_normal_train(crtc);
  
-@@ -3242,7 +3303,6 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
- 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- 	int pipe = intel_crtc->pipe;
- 	int plane = intel_crtc->plane;
--	u32 pctl;
- 
- 	if (!intel_crtc->active)
- 		return;
-@@ -3258,13 +3318,6 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
- 
- 	intel_disable_plane(dev_priv, plane, pipe);
- 	intel_disable_pipe(dev_priv, pipe);
--
--	/* Disable pannel fitter if it is on this pipe. */
--	pctl = I915_READ(PFIT_CONTROL);
--	if ((pctl & PFIT_ENABLE) &&
--	    ((pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT) == pipe)
--		I915_WRITE(PFIT_CONTROL, 0);
--
- 	intel_disable_pll(dev_priv, pipe);
- 
- 	intel_crtc->active = false;
-@@ -3339,10 +3392,12 @@ static void intel_crtc_disable(struct drm_crtc *crtc)
+@@ -3339,10 +3400,12 @@ static void intel_crtc_disable(struct drm_crtc *crtc)
  	struct drm_device *dev = crtc->dev;
  
  	crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
@@ -48115,7 +48059,7 @@ index 4591582..3c9b9c5 100644
  		mutex_unlock(&dev->struct_mutex);
  	}
  }
-@@ -3416,10 +3471,10 @@ static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
+@@ -3416,10 +3479,10 @@ static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
  			return false;
  	}
  
@@ -48130,7 +48074,7 @@ index 4591582..3c9b9c5 100644
  		drm_mode_set_crtcinfo(adjusted_mode, 0);
  
  	return true;
-@@ -4535,10 +4590,11 @@ static void ironlake_update_wm(struct drm_device *dev)
+@@ -4535,10 +4598,11 @@ static void ironlake_update_wm(struct drm_device *dev)
  	 */
  }
  
@@ -48143,7 +48087,7 @@ index 4591582..3c9b9c5 100644
  	int fbc_wm, plane_wm, cursor_wm;
  	unsigned int enabled;
  
-@@ -4547,8 +4603,10 @@ static void sandybridge_update_wm(struct drm_device *dev)
+@@ -4547,8 +4611,10 @@ static void sandybridge_update_wm(struct drm_device *dev)
  			    &sandybridge_display_wm_info, latency,
  			    &sandybridge_cursor_wm_info, latency,
  			    &plane_wm, &cursor_wm)) {
@@ -48156,7 +48100,7 @@ index 4591582..3c9b9c5 100644
  		DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
  			      " plane %d, " "cursor: %d\n",
  			      plane_wm, cursor_wm);
-@@ -4559,8 +4617,10 @@ static void sandybridge_update_wm(struct drm_device *dev)
+@@ -4559,8 +4625,10 @@ static void sandybridge_update_wm(struct drm_device *dev)
  			    &sandybridge_display_wm_info, latency,
  			    &sandybridge_cursor_wm_info, latency,
  			    &plane_wm, &cursor_wm)) {
@@ -48169,7 +48113,7 @@ index 4591582..3c9b9c5 100644
  		DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
  			      " plane %d, cursor: %d\n",
  			      plane_wm, cursor_wm);
-@@ -4573,8 +4633,10 @@ static void sandybridge_update_wm(struct drm_device *dev)
+@@ -4573,8 +4641,10 @@ static void sandybridge_update_wm(struct drm_device *dev)
  			    &sandybridge_display_wm_info, latency,
  			    &sandybridge_cursor_wm_info, latency,
  			    &plane_wm, &cursor_wm)) {
@@ -48182,7 +48126,7 @@ index 4591582..3c9b9c5 100644
  		DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
  			      " plane %d, cursor: %d\n",
  			      plane_wm, cursor_wm);
-@@ -4595,7 +4657,8 @@ static void sandybridge_update_wm(struct drm_device *dev)
+@@ -4595,7 +4665,8 @@ static void sandybridge_update_wm(struct drm_device *dev)
  	I915_WRITE(WM2_LP_ILK, 0);
  	I915_WRITE(WM1_LP_ILK, 0);
  
@@ -48192,7 +48136,7 @@ index 4591582..3c9b9c5 100644
  		return;
  	enabled = ffs(enabled) - 1;
  
-@@ -4645,6 +4708,161 @@ static void sandybridge_update_wm(struct drm_device *dev)
+@@ -4645,6 +4716,161 @@ static void sandybridge_update_wm(struct drm_device *dev)
  		   cursor_wm);
  }
  
@@ -48354,7 +48298,7 @@ index 4591582..3c9b9c5 100644
  /**
   * intel_update_watermarks - update FIFO watermark values based on current modes
   *
-@@ -4685,6 +4903,16 @@ static void intel_update_watermarks(struct drm_device *dev)
+@@ -4685,6 +4911,16 @@ static void intel_update_watermarks(struct drm_device *dev)
  		dev_priv->display.update_wm(dev);
  }
  
@@ -48371,7 +48315,7 @@ index 4591582..3c9b9c5 100644
  static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
  {
  	if (i915_panel_use_ssc >= 0)
-@@ -4832,6 +5060,82 @@ static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
+@@ -4832,6 +5068,82 @@ static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
  	return display_bpc != bpc;
  }
  
@@ -48454,7 +48398,7 @@ index 4591582..3c9b9c5 100644
  static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
  			      struct drm_display_mode *mode,
  			      struct drm_display_mode *adjusted_mode,
-@@ -4845,7 +5149,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
+@@ -4845,7 +5157,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
  	int plane = intel_crtc->plane;
  	int refclk, num_connectors = 0;
  	intel_clock_t clock, reduced_clock;
@@ -48463,7 +48407,7 @@ index 4591582..3c9b9c5 100644
  	bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
  	bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
  	struct drm_mode_config *mode_config = &dev->mode_config;
-@@ -4886,15 +5190,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
+@@ -4886,15 +5198,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
  		num_connectors++;
  	}
  
@@ -48480,7 +48424,7 @@ index 4591582..3c9b9c5 100644
  
  	/*
  	 * Returns a set of divisors for the desired target clock with the given
-@@ -4902,7 +5198,8 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
+@@ -4902,7 +5206,8 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
  	 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
  	 */
  	limit = intel_limit(crtc, refclk);
@@ -48490,7 +48434,7 @@ index 4591582..3c9b9c5 100644
  	if (!ok) {
  		DRM_ERROR("Couldn't find PLL settings for mode!\n");
  		return -EINVAL;
-@@ -4912,53 +5209,24 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
+@@ -4912,53 +5217,24 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
  	intel_crtc_update_cursor(crtc, true);
  
  	if (is_lvds && dev_priv->lvds_downclock_avail) {
@@ -48556,7 +48500,7 @@ index 4591582..3c9b9c5 100644
  
  	dpll = DPLL_VGA_MODE_DIS;
  
-@@ -5032,8 +5300,6 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
+@@ -5032,8 +5308,6 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
  	/* Set up the display plane register */
  	dspcntr = DISPPLANE_GAMMA_ENABLE;
  
@@ -48565,7 +48509,7 @@ index 4591582..3c9b9c5 100644
  	if (pipe == 0)
  		dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
  	else
-@@ -5068,7 +5334,6 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
+@@ -5068,7 +5342,6 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
  	DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
  	drm_mode_debug_printmodeline(mode);
  
@@ -48573,7 +48517,7 @@ index 4591582..3c9b9c5 100644
  	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
  
  	POSTING_READ(DPLL(pipe));
-@@ -5155,33 +5420,32 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
+@@ -5155,33 +5428,32 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
  		I915_WRITE(DPLL(pipe), dpll);
  	}
  
@@ -48622,7 +48566,7 @@ index 4591582..3c9b9c5 100644
  
  	I915_WRITE(HTOTAL(pipe),
  		   (adjusted_mode->crtc_hdisplay - 1) |
-@@ -5298,7 +5562,8 @@ void ironlake_init_pch_refclk(struct drm_device *dev)
+@@ -5298,7 +5570,8 @@ void ironlake_init_pch_refclk(struct drm_device *dev)
  		if (intel_panel_use_ssc(dev_priv) && can_ssc) {
  			DRM_DEBUG_KMS("Using SSC on panel\n");
  			temp |= DREF_SSC1_ENABLE;
@@ -48632,7 +48576,7 @@ index 4591582..3c9b9c5 100644
  
  		/* Get SSC going before enabling the outputs */
  		I915_WRITE(PCH_DREF_CONTROL, temp);
-@@ -5447,7 +5712,8 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
+@@ -5447,7 +5720,8 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
  	 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
  	 */
  	limit = intel_limit(crtc, refclk);
@@ -48642,7 +48586,7 @@ index 4591582..3c9b9c5 100644
  	if (!ok) {
  		DRM_ERROR("Couldn't find PLL settings for mode!\n");
  		return -EINVAL;
-@@ -5457,21 +5723,17 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
+@@ -5457,21 +5731,17 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
  	intel_crtc_update_cursor(crtc, true);
  
  	if (is_lvds && dev_priv->lvds_downclock_avail) {
@@ -48671,7 +48615,7 @@ index 4591582..3c9b9c5 100644
  	}
  	/* SDVO TV has fixed PLL values depend on its clock range,
  	   this mirrors vbios setting. */
-@@ -5766,17 +6028,19 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
+@@ -5766,17 +6036,19 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
  		}
  	}
  
@@ -48698,7 +48642,7 @@ index 4591582..3c9b9c5 100644
  
  	I915_WRITE(HTOTAL(pipe),
  		   (adjusted_mode->crtc_hdisplay - 1) |
-@@ -5819,12 +6083,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
+@@ -5819,12 +6091,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
  
  	intel_wait_for_vblank(dev, pipe);
  
@@ -48711,7 +48655,7 @@ index 4591582..3c9b9c5 100644
  	I915_WRITE(DSPCNTR(plane), dspcntr);
  	POSTING_READ(DSPCNTR(plane));
  
-@@ -5851,14 +6109,45 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
+@@ -5851,14 +6117,45 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
  
  	ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
  					      x, y, old_fb);
@@ -48759,7 +48703,7 @@ index 4591582..3c9b9c5 100644
  static void g4x_write_eld(struct drm_connector *connector,
  			  struct drm_crtc *crtc)
  {
-@@ -5875,6 +6164,12 @@ static void g4x_write_eld(struct drm_connector *connector,
+@@ -5875,6 +6172,12 @@ static void g4x_write_eld(struct drm_connector *connector,
  	else
  		eldv = G4X_ELDV_DEVCTG;
  
@@ -48772,7 +48716,7 @@ index 4591582..3c9b9c5 100644
  	i = I915_READ(G4X_AUD_CNTL_ST);
  	i &= ~(eldv | G4X_ELD_ADDR);
  	len = (i >> 9) & 0x1f;		/* ELD buffer size */
-@@ -5902,22 +6197,26 @@ static void ironlake_write_eld(struct drm_connector *connector,
+@@ -5902,22 +6205,26 @@ static void ironlake_write_eld(struct drm_connector *connector,
  	uint32_t i;
  	int len;
  	int hdmiw_hdmiedid;
@@ -48805,7 +48749,7 @@ index 4591582..3c9b9c5 100644
  
  	DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
  
-@@ -5926,14 +6225,27 @@ static void ironlake_write_eld(struct drm_connector *connector,
+@@ -5926,14 +6233,27 @@ static void ironlake_write_eld(struct drm_connector *connector,
  	if (!i) {
  		DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
  		/* operate blindly on all ports */
@@ -48837,7 +48781,7 @@ index 4591582..3c9b9c5 100644
  	i = I915_READ(aud_cntrl_st2);
  	i &= ~eldv;
  	I915_WRITE(aud_cntrl_st2, i);
-@@ -5941,13 +6253,8 @@ static void ironlake_write_eld(struct drm_connector *connector,
+@@ -5941,13 +6261,8 @@ static void ironlake_write_eld(struct drm_connector *connector,
  	if (!eld[0])
  		return;
  
@@ -48852,7 +48796,7 @@ index 4591582..3c9b9c5 100644
  	I915_WRITE(aud_cntl_st, i);
  
  	len = min_t(uint8_t, eld[2], 21);	/* 84 bytes of hw ELD buffer */
-@@ -6327,7 +6634,7 @@ static struct drm_display_mode load_detect_mode = {
+@@ -6327,7 +6642,7 @@ static struct drm_display_mode load_detect_mode = {
  
  static struct drm_framebuffer *
  intel_framebuffer_create(struct drm_device *dev,
@@ -48861,7 +48805,7 @@ index 4591582..3c9b9c5 100644
  			 struct drm_i915_gem_object *obj)
  {
  	struct intel_framebuffer *intel_fb;
-@@ -6369,7 +6676,7 @@ intel_framebuffer_create_for_mode(struct drm_device *dev,
+@@ -6369,7 +6684,7 @@ intel_framebuffer_create_for_mode(struct drm_device *dev,
  				  int depth, int bpp)
  {
  	struct drm_i915_gem_object *obj;
@@ -48870,7 +48814,7 @@ index 4591582..3c9b9c5 100644
  
  	obj = i915_gem_alloc_object(dev,
  				    intel_framebuffer_size_for_mode(mode, bpp));
-@@ -6378,9 +6685,9 @@ intel_framebuffer_create_for_mode(struct drm_device *dev,
+@@ -6378,9 +6693,9 @@ intel_framebuffer_create_for_mode(struct drm_device *dev,
  
  	mode_cmd.width = mode->hdisplay;
  	mode_cmd.height = mode->vdisplay;
@@ -48883,7 +48827,7 @@ index 4591582..3c9b9c5 100644
  
  	return intel_framebuffer_create(dev, &mode_cmd, obj);
  }
-@@ -6401,11 +6708,11 @@ mode_fits_in_fbdev(struct drm_device *dev,
+@@ -6401,11 +6716,11 @@ mode_fits_in_fbdev(struct drm_device *dev,
  		return NULL;
  
  	fb = &dev_priv->fbdev->ifb.base;
@@ -48898,7 +48842,7 @@ index 4591582..3c9b9c5 100644
  		return NULL;
  
  	return fb;
-@@ -6737,9 +7044,7 @@ static void intel_increase_pllclock(struct drm_crtc *crtc)
+@@ -6737,9 +7052,7 @@ static void intel_increase_pllclock(struct drm_crtc *crtc)
  	if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
  		DRM_DEBUG_DRIVER("upclocking LVDS\n");
  
@@ -48909,7 +48853,7 @@ index 4591582..3c9b9c5 100644
  
  		dpll &= ~DISPLAY_RATE_SELECT_FPA1;
  		I915_WRITE(dpll_reg, dpll);
-@@ -6748,9 +7053,6 @@ static void intel_increase_pllclock(struct drm_crtc *crtc)
+@@ -6748,9 +7061,6 @@ static void intel_increase_pllclock(struct drm_crtc *crtc)
  		dpll = I915_READ(dpll_reg);
  		if (dpll & DISPLAY_RATE_SELECT_FPA1)
  			DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
@@ -48919,7 +48863,7 @@ index 4591582..3c9b9c5 100644
  	}
  
  	/* Schedule downclock */
-@@ -6763,9 +7065,6 @@ static void intel_decrease_pllclock(struct drm_crtc *crtc)
+@@ -6763,9 +7073,6 @@ static void intel_decrease_pllclock(struct drm_crtc *crtc)
  	struct drm_device *dev = crtc->dev;
  	drm_i915_private_t *dev_priv = dev->dev_private;
  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
@@ -48929,7 +48873,7 @@ index 4591582..3c9b9c5 100644
  
  	if (HAS_PCH_SPLIT(dev))
  		return;
-@@ -6778,23 +7077,22 @@ static void intel_decrease_pllclock(struct drm_crtc *crtc)
+@@ -6778,23 +7085,22 @@ static void intel_decrease_pllclock(struct drm_crtc *crtc)
  	 * the manual case.
  	 */
  	if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
@@ -48959,7 +48903,7 @@ index 4591582..3c9b9c5 100644
  }
  
  /**
-@@ -6907,7 +7205,7 @@ static void intel_unpin_work_fn(struct work_struct *__work)
+@@ -6907,7 +7213,7 @@ static void intel_unpin_work_fn(struct work_struct *__work)
  		container_of(__work, struct intel_unpin_work, work);
  
  	mutex_lock(&work->dev->struct_mutex);
@@ -48968,7 +48912,7 @@ index 4591582..3c9b9c5 100644
  	drm_gem_object_unreference(&work->pending_flip_obj->base);
  	drm_gem_object_unreference(&work->old_fb_obj->base);
  
-@@ -6935,18 +7233,11 @@ static void do_intel_finish_page_flip(struct drm_device *dev,
+@@ -6935,18 +7241,11 @@ static void do_intel_finish_page_flip(struct drm_device *dev,
  
  	spin_lock_irqsave(&dev->event_lock, flags);
  	work = intel_crtc->unpin_work;
@@ -48988,7 +48932,7 @@ index 4591582..3c9b9c5 100644
  	intel_crtc->unpin_work = NULL;
  
  	if (work->event) {
-@@ -7018,25 +7309,16 @@ void intel_prepare_page_flip(struct drm_device *dev, int plane)
+@@ -7018,25 +7317,16 @@ void intel_prepare_page_flip(struct drm_device *dev, int plane)
  		to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
  	unsigned long flags;
  
@@ -49020,7 +48964,7 @@ index 4591582..3c9b9c5 100644
  static int intel_gen2_queue_flip(struct drm_device *dev,
  				 struct drm_crtc *crtc,
  				 struct drm_framebuffer *fb,
-@@ -7053,7 +7335,7 @@ static int intel_gen2_queue_flip(struct drm_device *dev,
+@@ -7053,7 +7343,7 @@ static int intel_gen2_queue_flip(struct drm_device *dev,
  		goto err;
  
  	/* Offset into the new buffer for cases of shared fbs between CRTCs */
@@ -49029,7 +48973,7 @@ index 4591582..3c9b9c5 100644
  
  	ret = BEGIN_LP_RING(6);
  	if (ret)
-@@ -7070,16 +7352,14 @@ static int intel_gen2_queue_flip(struct drm_device *dev,
+@@ -7070,16 +7360,14 @@ static int intel_gen2_queue_flip(struct drm_device *dev,
  	OUT_RING(MI_NOOP);
  	OUT_RING(MI_DISPLAY_FLIP |
  		 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
@@ -49049,7 +48993,7 @@ index 4591582..3c9b9c5 100644
  err:
  	return ret;
  }
-@@ -7100,7 +7380,7 @@ static int intel_gen3_queue_flip(struct drm_device *dev,
+@@ -7100,7 +7388,7 @@ static int intel_gen3_queue_flip(struct drm_device *dev,
  		goto err;
  
  	/* Offset into the new buffer for cases of shared fbs between CRTCs */
@@ -49058,7 +49002,7 @@ index 4591582..3c9b9c5 100644
  
  	ret = BEGIN_LP_RING(6);
  	if (ret)
-@@ -7114,16 +7394,15 @@ static int intel_gen3_queue_flip(struct drm_device *dev,
+@@ -7114,16 +7402,15 @@ static int intel_gen3_queue_flip(struct drm_device *dev,
  	OUT_RING(MI_NOOP);
  	OUT_RING(MI_DISPLAY_FLIP_I915 |
  		 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
@@ -49077,7 +49021,7 @@ index 4591582..3c9b9c5 100644
  err:
  	return ret;
  }
-@@ -7152,7 +7431,7 @@ static int intel_gen4_queue_flip(struct drm_device *dev,
+@@ -7152,7 +7439,7 @@ static int intel_gen4_queue_flip(struct drm_device *dev,
  	 */
  	OUT_RING(MI_DISPLAY_FLIP |
  		 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
@@ -49086,7 +49030,7 @@ index 4591582..3c9b9c5 100644
  	OUT_RING(obj->gtt_offset | obj->tiling_mode);
  
  	/* XXX Enabling the panel-fitter across page-flip is so far
-@@ -7162,13 +7441,11 @@ static int intel_gen4_queue_flip(struct drm_device *dev,
+@@ -7162,13 +7449,11 @@ static int intel_gen4_queue_flip(struct drm_device *dev,
  	pf = 0;
  	pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
  	OUT_RING(pf | pipesrc);
@@ -49101,7 +49045,7 @@ index 4591582..3c9b9c5 100644
  err:
  	return ret;
  }
-@@ -7193,19 +7470,23 @@ static int intel_gen6_queue_flip(struct drm_device *dev,
+@@ -7193,19 +7478,23 @@ static int intel_gen6_queue_flip(struct drm_device *dev,
  
  	OUT_RING(MI_DISPLAY_FLIP |
  		 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
@@ -49130,7 +49074,7 @@ index 4591582..3c9b9c5 100644
  err:
  	return ret;
  }
-@@ -7252,16 +7533,14 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
+@@ -7252,16 +7541,14 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
  		goto err_unpin;
  
  	intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
@@ -49149,7 +49093,7 @@ index 4591582..3c9b9c5 100644
  err:
  	return ret;
  }
-@@ -7280,8 +7559,8 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
+@@ -7280,8 +7567,8 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
  {
  	struct drm_device *dev = crtc->dev;
  	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -49160,7 +49104,7 @@ index 4591582..3c9b9c5 100644
  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  	struct intel_unpin_work *work;
  	unsigned long flags;
-@@ -7293,7 +7572,8 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
+@@ -7293,7 +7580,8 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
  
  	work->event = event;
  	work->dev = crtc->dev;
@@ -49170,7 +49114,7 @@ index 4591582..3c9b9c5 100644
  	INIT_WORK(&work->work, intel_unpin_work_fn);
  
  	ret = drm_vblank_get(dev, intel_crtc->pipe);
-@@ -7313,6 +7593,9 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
+@@ -7313,6 +7601,9 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
  	intel_crtc->unpin_work = work;
  	spin_unlock_irqrestore(&dev->event_lock, flags);
  
@@ -49180,7 +49124,7 @@ index 4591582..3c9b9c5 100644
  	mutex_lock(&dev->struct_mutex);
  
  	/* Reference the objects for the scheduled work. */
-@@ -7343,7 +7626,6 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
+@@ -7343,7 +7634,6 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
  
  cleanup_pending:
  	atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
@@ -49188,7 +49132,7 @@ index 4591582..3c9b9c5 100644
  	drm_gem_object_unreference(&work->old_fb_obj->base);
  	drm_gem_object_unreference(&obj->base);
  	mutex_unlock(&dev->struct_mutex);
-@@ -7556,10 +7838,9 @@ static void intel_setup_outputs(struct drm_device *dev)
+@@ -7556,10 +7846,9 @@ static void intel_setup_outputs(struct drm_device *dev)
  	struct drm_i915_private *dev_priv = dev->dev_private;
  	struct intel_encoder *encoder;
  	bool dpd_is_edp = false;
@@ -49201,7 +49145,7 @@ index 4591582..3c9b9c5 100644
  	if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
  		/* disable the panel fitter on everything but LVDS */
  		I915_WRITE(PFIT_CONTROL, 0);
-@@ -7688,7 +7969,7 @@ static const struct drm_framebuffer_funcs intel_fb_funcs = {
+@@ -7688,7 +7977,7 @@ static const struct drm_framebuffer_funcs intel_fb_funcs = {
  
  int intel_framebuffer_init(struct drm_device *dev,
  			   struct intel_framebuffer *intel_fb,
@@ -49210,7 +49154,7 @@ index 4591582..3c9b9c5 100644
  			   struct drm_i915_gem_object *obj)
  {
  	int ret;
-@@ -7696,21 +7977,27 @@ int intel_framebuffer_init(struct drm_device *dev,
+@@ -7696,21 +7985,27 @@ int intel_framebuffer_init(struct drm_device *dev,
  	if (obj->tiling_mode == I915_TILING_Y)
  		return -EINVAL;
  
@@ -49248,7 +49192,7 @@ index 4591582..3c9b9c5 100644
  		return -EINVAL;
  	}
  
-@@ -7728,11 +8015,12 @@ int intel_framebuffer_init(struct drm_device *dev,
+@@ -7728,11 +8023,12 @@ int intel_framebuffer_init(struct drm_device *dev,
  static struct drm_framebuffer *
  intel_user_framebuffer_create(struct drm_device *dev,
  			      struct drm_file *filp,
@@ -49263,7 +49207,7 @@ index 4591582..3c9b9c5 100644
  	if (&obj->base == NULL)
  		return ERR_PTR(-ENOENT);
  
-@@ -8001,7 +8289,7 @@ void intel_init_emon(struct drm_device *dev)
+@@ -8001,7 +8297,7 @@ void intel_init_emon(struct drm_device *dev)
  	dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
  }
  
@@ -49272,7 +49216,7 @@ index 4591582..3c9b9c5 100644
  {
  	/*
  	 * Respect the kernel parameter if it is set
-@@ -8019,11 +8307,11 @@ static bool intel_enable_rc6(struct drm_device *dev)
+@@ -8019,11 +8315,11 @@ static bool intel_enable_rc6(struct drm_device *dev)
  	 * Disable rc6 on Sandybridge
  	 */
  	if (INTEL_INFO(dev)->gen == 6) {
@@ -49288,7 +49232,7 @@ index 4591582..3c9b9c5 100644
  }
  
  void gen6_enable_rps(struct drm_i915_private *dev_priv)
-@@ -8031,7 +8319,9 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv)
+@@ -8031,7 +8327,9 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv)
  	u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
  	u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
  	u32 pcu_mbox, rc6_mask = 0;
@@ -49298,7 +49242,7 @@ index 4591582..3c9b9c5 100644
  	int i;
  
  	/* Here begins a magic sequence of register writes to enable
-@@ -8042,6 +8332,13 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv)
+@@ -8042,6 +8340,13 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv)
  	 */
  	I915_WRITE(GEN6_RC_STATE, 0);
  	mutex_lock(&dev_priv->dev->struct_mutex);
@@ -49312,8 +49256,12 @@ index 4591582..3c9b9c5 100644
  	gen6_gt_force_wake_get(dev_priv);
  
  	/* disable the counters and set deterministic thresholds */
-@@ -8062,9 +8359,20 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv)
- 	I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
+@@ -8059,12 +8364,23 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv)
+ 	I915_WRITE(GEN6_RC_SLEEP, 0);
+ 	I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
+ 	I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
+-	I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
++	I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
  	I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
  
 -	if (intel_enable_rc6(dev_priv->dev))
@@ -49336,7 +49284,7 @@ index 4591582..3c9b9c5 100644
  
  	I915_WRITE(GEN6_RC_CONTROL,
  		   rc6_mask |
-@@ -8292,6 +8600,10 @@ static void gen6_init_clock_gating(struct drm_device *dev)
+@@ -8292,6 +8608,10 @@ static void gen6_init_clock_gating(struct drm_device *dev)
  	I915_WRITE(WM2_LP_ILK, 0);
  	I915_WRITE(WM1_LP_ILK, 0);
  
@@ -49347,7 +49295,7 @@ index 4591582..3c9b9c5 100644
  	/* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
  	 * gating disable must be set.  Failure to set it results in
  	 * flickering pixels due to Z write ordering failures after
-@@ -8370,6 +8682,10 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
+@@ -8370,6 +8690,10 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
  
  	I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
  
@@ -49358,7 +49306,7 @@ index 4591582..3c9b9c5 100644
  	/* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
  	I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
  		   GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
-@@ -8680,9 +8996,15 @@ static void intel_init_display(struct drm_device *dev)
+@@ -8680,9 +9004,15 @@ static void intel_init_display(struct drm_device *dev)
  		if (IS_IVYBRIDGE(dev)) {
  			u32	ecobus;
  
@@ -49375,7 +49323,7 @@ index 4591582..3c9b9c5 100644
  			__gen6_gt_force_wake_mt_put(dev_priv);
  			mutex_unlock(&dev->struct_mutex);
  
-@@ -8714,6 +9036,7 @@ static void intel_init_display(struct drm_device *dev)
+@@ -8714,6 +9044,7 @@ static void intel_init_display(struct drm_device *dev)
  		} else if (IS_GEN6(dev)) {
  			if (SNB_READ_WM0_LATENCY()) {
  				dev_priv->display.update_wm = sandybridge_update_wm;
@@ -49383,7 +49331,7 @@ index 4591582..3c9b9c5 100644
  			} else {
  				DRM_DEBUG_KMS("Failed to read display plane latency. "
  					      "Disable CxSR\n");
-@@ -8727,6 +9050,7 @@ static void intel_init_display(struct drm_device *dev)
+@@ -8727,6 +9058,7 @@ static void intel_init_display(struct drm_device *dev)
  			dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
  			if (SNB_READ_WM0_LATENCY()) {
  				dev_priv->display.update_wm = sandybridge_update_wm;
@@ -49391,7 +49339,7 @@ index 4591582..3c9b9c5 100644
  			} else {
  				DRM_DEBUG_KMS("Failed to read display plane latency. "
  					      "Disable CxSR\n");
-@@ -8839,8 +9163,6 @@ struct intel_quirk {
+@@ -8839,8 +9171,6 @@ struct intel_quirk {
  };
  
  struct intel_quirk intel_quirks[] = {
@@ -49400,7 +49348,7 @@ index 4591582..3c9b9c5 100644
  	/* HP Mini needs pipe A force quirk (LP: #322104) */
  	{ 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
  
-@@ -8907,33 +9229,19 @@ static void i915_disable_vga(struct drm_device *dev)
+@@ -8907,33 +9237,19 @@ static void i915_disable_vga(struct drm_device *dev)
  	POSTING_READ(vga_reg);
  }
  
@@ -49438,7 +49386,7 @@ index 4591582..3c9b9c5 100644
  	dev->mode_config.funcs = (void *)&intel_mode_funcs;
  
  	intel_init_quirks(dev);
-@@ -8957,6 +9265,9 @@ void intel_modeset_init(struct drm_device *dev)
+@@ -8957,6 +9273,9 @@ void intel_modeset_init(struct drm_device *dev)
  
  	for (i = 0; i < dev_priv->num_pipe; i++) {
  		intel_crtc_init(dev, i);
@@ -71935,7 +71883,7 @@ index 4760466..4b04ba3 100644
  
  
 diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
-index a25d08a..15594a3 100644
+index a25d08a..ebbfbd2 100644
 --- a/drivers/gpu/drm/radeon/atombios_crtc.c
 +++ b/drivers/gpu/drm/radeon/atombios_crtc.c
 @@ -231,6 +231,22 @@ static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
@@ -71961,19 +71909,16 @@ index a25d08a..15594a3 100644
  void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
  {
  	struct drm_device *dev = crtc->dev;
-@@ -242,8 +258,10 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
- 		radeon_crtc->enabled = true;
+@@ -243,7 +259,7 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
  		/* adjust pm to dpms changes BEFORE enabling crtcs */
  		radeon_pm_compute_clocks(rdev);
-+		if (ASIC_IS_DCE6(rdev) && !radeon_crtc->in_mode_set)
-+			atombios_powergate_crtc(crtc, ATOM_DISABLE);
  		atombios_enable_crtc(crtc, ATOM_ENABLE);
 -		if (ASIC_IS_DCE3(rdev))
 +		if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
  			atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
  		atombios_blank_crtc(crtc, ATOM_DISABLE);
  		drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
-@@ -255,10 +273,12 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
+@@ -255,7 +271,7 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
  		drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
  		if (radeon_crtc->enabled)
  			atombios_blank_crtc(crtc, ATOM_ENABLE);
@@ -71982,12 +71927,7 @@ index a25d08a..15594a3 100644
  			atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
  		atombios_enable_crtc(crtc, ATOM_DISABLE);
  		radeon_crtc->enabled = false;
-+		if (ASIC_IS_DCE6(rdev) && !radeon_crtc->in_mode_set)
-+			atombios_powergate_crtc(crtc, ATOM_ENABLE);
- 		/* adjust pm to dpms changes AFTER disabling crtcs */
- 		radeon_pm_compute_clocks(rdev);
- 		break;
-@@ -355,15 +375,12 @@ static void atombios_crtc_set_timing(struct drm_crtc *crtc,
+@@ -355,15 +371,12 @@ static void atombios_crtc_set_timing(struct drm_crtc *crtc,
  	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  }
  
@@ -72005,7 +71945,7 @@ index a25d08a..15594a3 100644
  		case ATOM_PPLL1:
  			ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
  			ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
-@@ -379,7 +396,7 @@ static void atombios_disable_ss(struct drm_crtc *crtc)
+@@ -379,7 +392,7 @@ static void atombios_disable_ss(struct drm_crtc *crtc)
  			return;
  		}
  	} else if (ASIC_IS_AVIVO(rdev)) {
@@ -72014,7 +71954,7 @@ index a25d08a..15594a3 100644
  		case ATOM_PPLL1:
  			ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
  			ss_cntl &= ~1;
-@@ -406,16 +423,31 @@ union atom_enable_ss {
+@@ -406,16 +419,31 @@ union atom_enable_ss {
  	ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
  };
  
@@ -72049,7 +71989,7 @@ index a25d08a..15594a3 100644
  	memset(&args, 0, sizeof(args));
  
  	if (ASIC_IS_DCE5(rdev)) {
-@@ -441,7 +473,7 @@ static void atombios_crtc_program_ss(struct drm_crtc *crtc,
+@@ -441,7 +469,7 @@ static void atombios_crtc_program_ss(struct drm_crtc *crtc,
  			return;
  		}
  		args.v3.ucEnable = enable;
@@ -72058,7 +71998,7 @@ index a25d08a..15594a3 100644
  			args.v3.ucEnable = ATOM_DISABLE;
  	} else if (ASIC_IS_DCE4(rdev)) {
  		args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
-@@ -479,7 +511,7 @@ static void atombios_crtc_program_ss(struct drm_crtc *crtc,
+@@ -479,7 +507,7 @@ static void atombios_crtc_program_ss(struct drm_crtc *crtc,
  	} else if (ASIC_IS_AVIVO(rdev)) {
  		if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
  		    (ss->type & ATOM_EXTERNAL_SS_MASK)) {
@@ -72067,7 +72007,7 @@ index a25d08a..15594a3 100644
  			return;
  		}
  		args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
-@@ -491,7 +523,7 @@ static void atombios_crtc_program_ss(struct drm_crtc *crtc,
+@@ -491,7 +519,7 @@ static void atombios_crtc_program_ss(struct drm_crtc *crtc,
  	} else {
  		if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
  		    (ss->type & ATOM_EXTERNAL_SS_MASK)) {
@@ -72076,7 +72016,7 @@ index a25d08a..15594a3 100644
  			return;
  		}
  		args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
-@@ -523,6 +555,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
+@@ -523,6 +551,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
  	int encoder_mode = 0;
  	u32 dp_clock = mode->clock;
  	int bpc = 8;
@@ -72084,7 +72024,7 @@ index a25d08a..15594a3 100644
  
  	/* reset the pll flags */
  	pll->flags = 0;
-@@ -542,9 +575,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
+@@ -542,9 +571,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
  		if (rdev->family < CHIP_RV770)
  			pll->flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;
  		/* use frac fb div on APUs */
@@ -72095,7 +72035,7 @@ index a25d08a..15594a3 100644
  			pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
  	} else {
  		pll->flags |= RADEON_PLL_LEGACY;
-@@ -559,9 +590,10 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
+@@ -559,9 +586,10 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
  		if (encoder->crtc == crtc) {
  			radeon_encoder = to_radeon_encoder(encoder);
  			connector = radeon_get_connector_for_encoder(encoder);
@@ -72108,7 +72048,7 @@ index a25d08a..15594a3 100644
  			if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
  			    (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
  				if (connector) {
-@@ -657,7 +689,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
+@@ -657,7 +685,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
  					if (dig->coherent_mode)
  						args.v3.sInput.ucDispPllConfig |=
  							DISPPLL_CONFIG_COHERENT_MODE;
@@ -72117,7 +72057,7 @@ index a25d08a..15594a3 100644
  						args.v3.sInput.ucDispPllConfig |=
  							DISPPLL_CONFIG_DUAL_LINK;
  				}
-@@ -707,11 +739,9 @@ union set_pixel_clock {
+@@ -707,11 +735,9 @@ union set_pixel_clock {
  /* on DCE5, make sure the voltage is high enough to support the
   * required disp clk.
   */
@@ -72130,7 +72070,7 @@ index a25d08a..15594a3 100644
  	u8 frev, crev;
  	int index;
  	union set_pixel_clock args;
-@@ -739,7 +769,12 @@ static void atombios_crtc_set_dcpll(struct drm_crtc *crtc,
+@@ -739,7 +765,12 @@ static void atombios_crtc_set_dcpll(struct drm_crtc *crtc,
  			 * SetPixelClock provides the dividers
  			 */
  			args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
@@ -72144,7 +72084,7 @@ index a25d08a..15594a3 100644
  			break;
  		default:
  			DRM_ERROR("Unknown table version %d %d\n", frev, crev);
-@@ -932,7 +967,9 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
+@@ -932,7 +963,9 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
  		struct radeon_connector_atom_dig *dig_connector =
  			radeon_connector->con_priv;
  		int dp_clock;
@@ -72155,7 +72095,7 @@ index a25d08a..15594a3 100644
  
  		switch (encoder_mode) {
  		case ATOM_ENCODER_MODE_DP_MST:
-@@ -1001,7 +1038,7 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
+@@ -1001,7 +1034,7 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
  		radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
  					  &ref_div, &post_div);
  
@@ -72164,7 +72104,7 @@ index a25d08a..15594a3 100644
  
  	atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
  				  encoder_mode, radeon_encoder->encoder_id, mode->clock,
-@@ -1024,7 +1061,7 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
+@@ -1024,7 +1057,7 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
  			ss.step = step_size;
  		}
  
@@ -72173,7 +72113,7 @@ index a25d08a..15594a3 100644
  	}
  }
  
-@@ -1041,6 +1078,7 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
+@@ -1041,6 +1074,7 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
  	struct radeon_bo *rbo;
  	uint64_t fb_location;
  	uint32_t fb_format, fb_pitch_pixels, tiling_flags;
@@ -72181,7 +72121,7 @@ index a25d08a..15594a3 100644
  	u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
  	u32 tmp, viewport_w, viewport_h;
  	int r;
-@@ -1131,20 +1169,13 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
+@@ -1131,20 +1165,13 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
  			break;
  		}
  
@@ -72208,7 +72148,7 @@ index a25d08a..15594a3 100644
  	} else if (tiling_flags & RADEON_TILING_MICRO)
  		fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
  
-@@ -1189,7 +1220,7 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
+@@ -1189,7 +1216,7 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
  	WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
  	WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
  
@@ -72217,7 +72157,7 @@ index a25d08a..15594a3 100644
  	WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
  	WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
  
-@@ -1358,7 +1389,7 @@ static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
+@@ -1358,7 +1385,7 @@ static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
  	WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
  	WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
  
@@ -72226,7 +72166,7 @@ index a25d08a..15594a3 100644
  	WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
  	WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
  
-@@ -1460,7 +1491,36 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
+@@ -1460,7 +1487,36 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
  	struct drm_crtc *test_crtc;
  	uint32_t pll_in_use = 0;
  
@@ -72264,7 +72204,7 @@ index a25d08a..15594a3 100644
  		list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
  			if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
  				/* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
-@@ -1475,6 +1535,8 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
+@@ -1475,6 +1531,8 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
  				if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) {
  					if (rdev->clock.dp_extclk)
  						return ATOM_PPLL_INVALID;
@@ -72273,7 +72213,7 @@ index a25d08a..15594a3 100644
  					else if (ASIC_IS_DCE5(rdev))
  						return ATOM_DCPLL;
  				}
-@@ -1501,6 +1563,26 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
+@@ -1501,6 +1559,26 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
  
  }
  
@@ -72300,7 +72240,7 @@ index a25d08a..15594a3 100644
  int atombios_crtc_mode_set(struct drm_crtc *crtc,
  			   struct drm_display_mode *mode,
  			   struct drm_display_mode *adjusted_mode,
-@@ -1522,19 +1604,6 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc,
+@@ -1522,19 +1600,6 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc,
  		}
  	}
  
@@ -72320,7 +72260,7 @@ index a25d08a..15594a3 100644
  	atombios_crtc_set_pll(crtc, adjusted_mode);
  
  	if (ASIC_IS_DCE4(rdev))
-@@ -1568,18 +1637,28 @@ static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
+@@ -1568,18 +1633,28 @@ static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
  static void atombios_crtc_prepare(struct drm_crtc *crtc)
  {
  	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
@@ -72349,7 +72289,16 @@ index a25d08a..15594a3 100644
  }
  
  static void atombios_crtc_disable(struct drm_crtc *crtc)
-@@ -1611,6 +1690,12 @@ static void atombios_crtc_disable(struct drm_crtc *crtc)
+@@ -1591,6 +1666,8 @@ static void atombios_crtc_disable(struct drm_crtc *crtc)
+ 	int i;
+ 
+ 	atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
++	if (ASIC_IS_DCE6(rdev))
++		atombios_powergate_crtc(crtc, ATOM_ENABLE);
+ 
+ 	for (i = 0; i < rdev->num_crtc; i++) {
+ 		if (rdev->mode_info.crtcs[i] &&
+@@ -1611,6 +1688,12 @@ static void atombios_crtc_disable(struct drm_crtc *crtc)
  		atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
  					  0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
  		break;
@@ -85795,26 +85744,10 @@ index b6e18c8..9c6b29a 100644
  			tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
  			tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |
 diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c
-index c32fd93..a2470d9 100644
+index c32fd93..2b2c557 100644
 --- a/drivers/gpu/drm/radeon/radeon_combios.c
 +++ b/drivers/gpu/drm/radeon/radeon_combios.c
-@@ -958,15 +958,6 @@ struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
- 			found = 1;
- 	}
- 
--	/* quirks */
--	/* Radeon 9100 (R200) */
--	if ((dev->pdev->device == 0x514D) &&
--	    (dev->pdev->subsystem_vendor == 0x174B) &&
--	    (dev->pdev->subsystem_device == 0x7149)) {
--		/* vbios value is bad, use the default */
--		found = 0;
--	}
--
- 	if (!found) /* fallback to defaults */
- 		radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
- 
-@@ -1545,9 +1536,6 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
+@@ -1545,9 +1545,6 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
  			   of_machine_is_compatible("PowerBook6,7")) {
  			/* ibook */
  			rdev->mode_info.connector_table = CT_IBOOK;
@@ -85824,7 +85757,7 @@ index c32fd93..a2470d9 100644
  		} else if (of_machine_is_compatible("PowerMac4,4")) {
  			/* emac */
  			rdev->mode_info.connector_table = CT_EMAC;
-@@ -1573,11 +1561,6 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
+@@ -1573,11 +1570,6 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
  			   (rdev->pdev->subsystem_device == 0x4150)) {
  			/* Mac G5 tower 9600 */
  			rdev->mode_info.connector_table = CT_MAC_G5_9600;
@@ -85836,7 +85769,7 @@ index c32fd93..a2470d9 100644
  		} else
  #endif /* CONFIG_PPC_PMAC */
  #ifdef CONFIG_PPC64
-@@ -2151,115 +2134,6 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
+@@ -2151,115 +2143,6 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
  					    CONNECTOR_OBJECT_ID_SVIDEO,
  					    &hpd);
  		break;
@@ -85952,7 +85885,7 @@ index c32fd93..a2470d9 100644
  	default:
  		DRM_INFO("Connector table: %d (invalid)\n",
  			 rdev->mode_info.connector_table);
-@@ -2979,7 +2853,7 @@ bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
+@@ -2979,7 +2862,7 @@ bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
  					case 4:
  						val = RBIOS16(index);
  						index += 2;
@@ -85961,7 +85894,7 @@ index c32fd93..a2470d9 100644
  						break;
  					case 6:
  						slave_addr = id & 0xff;
-@@ -3178,7 +3052,7 @@ static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
+@@ -3178,7 +3061,7 @@ static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
  					udelay(150);
  					break;
  				case 2:
@@ -85970,7 +85903,7 @@ index c32fd93..a2470d9 100644
  					break;
  				case 3:
  					while (tmp--) {
-@@ -3209,13 +3083,13 @@ static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
+@@ -3209,13 +3092,13 @@ static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
  						/*mclk_cntl |= 0x00001111;*//* ??? */
  						WREG32_PLL(RADEON_MCLK_CNTL,
  							   mclk_cntl);
@@ -101254,10 +101187,10 @@ index 0000000..08eff0d
 +module_exit(udl_exit);
 diff --git a/drivers/gpu/drm/udl/udl_drv.h b/drivers/gpu/drm/udl/udl_drv.h
 new file mode 100644
-index 0000000..e760575
+index 0000000..2b8c4fd
 --- /dev/null
 +++ b/drivers/gpu/drm/udl/udl_drv.h
-@@ -0,0 +1,142 @@
+@@ -0,0 +1,144 @@
 +/*
 + * Copyright (C) 2012 Red Hat
 + *
@@ -101334,6 +101267,8 @@ index 0000000..e760575
 +	struct drm_framebuffer base;
 +	struct udl_gem_object *obj;
 +	bool active_16; /* active on the 16-bit channel */
++	int x1, y1, x2, y2; /* dirty rect */
++	spinlock_t dirty_lock;
 +};
 +
 +#define to_udl_fb(x) container_of(x, struct udl_framebuffer, base)
@@ -101488,10 +101423,10 @@ index 0000000..56e75f0
 +}
 diff --git a/drivers/gpu/drm/udl/udl_fb.c b/drivers/gpu/drm/udl/udl_fb.c
 new file mode 100644
-index 0000000..b9282cf
+index 0000000..f02d223
 --- /dev/null
 +++ b/drivers/gpu/drm/udl/udl_fb.c
-@@ -0,0 +1,613 @@
+@@ -0,0 +1,649 @@
 +/*
 + * Copyright (C) 2012 Red Hat
 + *
@@ -101516,9 +101451,9 @@ index 0000000..b9282cf
 +
 +#include "drm_fb_helper.h"
 +
-+#define DL_DEFIO_WRITE_DELAY    5 /* fb_deferred_io.delay in jiffies */
++#define DL_DEFIO_WRITE_DELAY    (HZ/20) /* fb_deferred_io.delay in jiffies */
 +
-+static int fb_defio = 1;  /* Optionally enable experimental fb_defio mmap support */
++static int fb_defio = 0;  /* Optionally enable experimental fb_defio mmap support */
 +static int fb_bpp = 16;
 +
 +module_param(fb_bpp, int, S_IWUSR | S_IRUSR | S_IWGRP | S_IRGRP);
@@ -101647,6 +101582,9 @@ index 0000000..b9282cf
 +	struct urb *urb;
 +	int aligned_x;
 +	int bpp = (fb->base.bits_per_pixel / 8);
++	int x2, y2;
++	bool store_for_later = false;
++	unsigned long flags;
 +
 +	if (!fb->active_16)
 +		return 0;
@@ -101654,8 +101592,6 @@ index 0000000..b9282cf
 +	if (!fb->obj->vmapping)
 +		udl_gem_vmap(fb->obj);
 +
-+	start_cycles = get_cycles();
-+
 +	aligned_x = DL_ALIGN_DOWN(x, sizeof(unsigned long));
 +	width = DL_ALIGN_UP(width + (x-aligned_x), sizeof(unsigned long));
 +	x = aligned_x;
@@ -101665,19 +101601,53 @@ index 0000000..b9282cf
 +	    (y + height > fb->base.height))
 +		return -EINVAL;
 +
++	/* if we are in atomic just store the info
++	   can't test inside spin lock */
++	if (in_atomic())
++		store_for_later = true;
++
++	x2 = x + width - 1;
++	y2 = y + height - 1;
++
++	spin_lock_irqsave(&fb->dirty_lock, flags);
++
++	if (fb->y1 < y)
++		y = fb->y1;
++	if (fb->y2 > y2)
++		y2 = fb->y2;
++	if (fb->x1 < x)
++		x = fb->x1;
++	if (fb->x2 > x2)
++		x2 = fb->x2;
++
++	if (store_for_later) {
++		fb->x1 = x;
++		fb->x2 = x2;
++		fb->y1 = y;
++		fb->y2 = y2;
++		spin_unlock_irqrestore(&fb->dirty_lock, flags);
++		return 0;
++	}
++
++	fb->x1 = fb->y1 = INT_MAX;
++	fb->x2 = fb->y2 = 0;
++
++	spin_unlock_irqrestore(&fb->dirty_lock, flags);
++	start_cycles = get_cycles();
++
 +	urb = udl_get_urb(dev);
 +	if (!urb)
 +		return 0;
 +	cmd = urb->transfer_buffer;
 +
-+	for (i = y; i < y + height ; i++) {
++	for (i = y; i <= y2 ; i++) {
 +		const int line_offset = fb->base.pitches[0] * i;
 +		const int byte_offset = line_offset + (x * bpp);
 +		const int dev_byte_offset = (fb->base.width * bpp * i) + (x * bpp);
 +		if (udl_render_hline(dev, bpp, &urb,
 +				     (char *) fb->obj->vmapping,
 +				     &cmd, byte_offset, dev_byte_offset,
-+				     width * bpp,
++				     (x2 - x + 1) * bpp,
 +				     &bytes_identical, &bytes_sent))
 +			goto error;
 +	}
@@ -101902,6 +101872,7 @@ index 0000000..b9282cf
 +{
 +	int ret;
 +
++	spin_lock_init(&ufb->dirty_lock);
 +	ufb->obj = obj;
 +	ret = drm_framebuffer_init(dev, &ufb->base, &udlfb_funcs);
 +	drm_helper_mode_fill_fb_struct(&ufb->base, mode_cmd);