Add some patches from Marvell's Orion tree
svn path=/dists/trunk/linux-2.6/; revision=11350
This commit is contained in:
Martin Michlmayr
parent
2ebd19a615
commit
110a9434a0
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@ -22,6 +22,11 @@ linux-2.6 (2.6.26~rc1-1~experimental.1) UNRELEASED; urgency=low
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[ Martin Michlmayr ]
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* [arm/orion5x] Update the config to reflect upstream renaming this
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subarch.
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* [arm/orion5x] Add some patches from Marvell's Orion tree:
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- cache align destination pointer when copying memory for some processors
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- cache align memset and memzero
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- Feroceon: speed up flushing of the entire cache
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- support for 5281 D0 stepping
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-- maximilian attems <maks@debian.org> Sat, 26 Apr 2008 23:11:17 +0200
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@ -0,0 +1,52 @@
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From: Lennert Buytenhek <buytenh@marvell.com>
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Date: Mon, 5 May 2008 18:19:55 +0000 (-0400)
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Subject: Orion: support for D0 stepping
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X-Git-Url: http://git.kernel.org/?p=linux%2Fkernel%2Fgit%2Fnico%2Forion.git;a=commitdiff_plain;h=0e33c8a37f7c05bf85944cf10ca499b2d3754c1b
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Orion: support for D0 stepping
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Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
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Signed-off-by: Nicolas Pitre <nico@marvell.com>
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---
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diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
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index 4f13fd0..3e40e96 100644
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--- a/arch/arm/mach-orion5x/common.c
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+++ b/arch/arm/mach-orion5x/common.c
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@@ -338,6 +338,8 @@ static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name)
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*dev_name = "MV88F5281-D2";
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} else if (*rev == MV88F5281_REV_D1) {
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*dev_name = "MV88F5281-D1";
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+ } else if (*rev == MV88F5281_REV_D0) {
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+ *dev_name = "MV88F5281-D0";
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} else {
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*dev_name = "MV88F5281-Rev-Unsupported";
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}
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@@ -372,6 +374,15 @@ void __init orion5x_init(void)
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orion5x_setup_cpu_mbus_bridge();
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/*
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+ * Don't issue "Wait for Interrupt" instruction if we are
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+ * running on D0 5281 silicon.
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+ */
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+ if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) {
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+ printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n");
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+ disable_hlt();
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+ }
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+
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+ /*
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* Register devices.
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*/
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platform_device_register(&orion5x_uart);
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diff --git a/include/asm-arm/arch-orion5x/orion5x.h b/include/asm-arm/arch-orion5x/orion5x.h
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index 206ddd7..25ec775 100644
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--- a/include/asm-arm/arch-orion5x/orion5x.h
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+++ b/include/asm-arm/arch-orion5x/orion5x.h
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@@ -71,6 +71,7 @@
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#define MV88F5182_REV_A2 2
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/* Orion-2 (88F5281) */
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#define MV88F5281_DEV_ID 0x5281
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+#define MV88F5281_REV_D0 4
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#define MV88F5281_REV_D1 5
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#define MV88F5281_REV_D2 6
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@ -0,0 +1,120 @@
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From: Nicolas Pitre <nico@cam.org>
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Date: Mon, 31 Mar 2008 16:38:31 +0000 (-0400)
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Subject: [ARM] cache align destination pointer when copying memory for some processors
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X-Git-Url: http://git.kernel.org/?p=linux%2Fkernel%2Fgit%2Fnico%2Forion.git;a=commitdiff_plain;h=f25c9c5b9b3eca2f4a41ac72fec6244c0cbd87cc
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[ARM] cache align destination pointer when copying memory for some processors
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The implementation for memory copy functions on ARM had a (disabled)
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provision for aligning the source pointer before loading registers with
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data. Turns out that aligning the _destination_ pointer is much more
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useful, as the read side is already sufficiently helped with the use of
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preload.
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So this changes the definition of the CALGN() macro to target the
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destination pointer instead, and turns it on for Feroceon processors
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where the gain is very notable.
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Signed-off-by: Nicolas Pitre <nico@marvell.com>
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---
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diff --git a/arch/arm/lib/copy_template.S b/arch/arm/lib/copy_template.S
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index cab355c..139cce6 100644
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--- a/arch/arm/lib/copy_template.S
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+++ b/arch/arm/lib/copy_template.S
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@@ -13,14 +13,6 @@
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*/
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/*
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- * This can be used to enable code to cacheline align the source pointer.
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- * Experiments on tested architectures (StrongARM and XScale) didn't show
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- * this a worthwhile thing to do. That might be different in the future.
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- */
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-//#define CALGN(code...) code
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-#define CALGN(code...)
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-
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-/*
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* Theory of operation
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* -------------------
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*
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@@ -82,7 +74,7 @@
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stmfd sp!, {r5 - r8}
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blt 5f
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- CALGN( ands ip, r1, #31 )
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+ CALGN( ands ip, r0, #31 )
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CALGN( rsb r3, ip, #32 )
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CALGN( sbcnes r4, r3, r2 ) @ C is always set here
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CALGN( bcs 2f )
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@@ -168,7 +160,7 @@
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subs r2, r2, #28
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blt 14f
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- CALGN( ands ip, r1, #31 )
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+ CALGN( ands ip, r0, #31 )
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CALGN( rsb ip, ip, #32 )
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CALGN( sbcnes r4, ip, r2 ) @ C is always set here
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CALGN( subcc r2, r2, ip )
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diff --git a/arch/arm/lib/memmove.S b/arch/arm/lib/memmove.S
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index ef7fddc..415e3d1 100644
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--- a/arch/arm/lib/memmove.S
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+++ b/arch/arm/lib/memmove.S
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@@ -13,14 +13,6 @@
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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-/*
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- * This can be used to enable code to cacheline align the source pointer.
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- * Experiments on tested architectures (StrongARM and XScale) didn't show
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- * this a worthwhile thing to do. That might be different in the future.
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- */
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-//#define CALGN(code...) code
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-#define CALGN(code...)
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-
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.text
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/*
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@@ -55,7 +47,7 @@ ENTRY(memmove)
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stmfd sp!, {r5 - r8}
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blt 5f
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- CALGN( ands ip, r1, #31 )
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+ CALGN( ands ip, r0, #31 )
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CALGN( sbcnes r4, ip, r2 ) @ C is always set here
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CALGN( bcs 2f )
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CALGN( adr r4, 6f )
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@@ -138,7 +130,7 @@ ENTRY(memmove)
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subs r2, r2, #28
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blt 14f
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- CALGN( ands ip, r1, #31 )
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+ CALGN( ands ip, r0, #31 )
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CALGN( rsb ip, ip, #32 )
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CALGN( sbcnes r4, ip, r2 ) @ C is always set here
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CALGN( subcc r2, r2, ip )
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diff --git a/include/asm-arm/assembler.h b/include/asm-arm/assembler.h
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index fce8328..911393b 100644
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--- a/include/asm-arm/assembler.h
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+++ b/include/asm-arm/assembler.h
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@@ -56,6 +56,21 @@
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#endif
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/*
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+ * This can be used to enable code to cacheline align the destination
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+ * pointer when bulk writing to memory. Experiments on StrongARM and
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+ * XScale didn't show this a worthwhile thing to do when the cache is not
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+ * set to write-allocate (this would need further testing on XScale when WA
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+ * is used).
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+ *
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+ * On Feroceon there is much to gain however, regardless of cache mode.
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+ */
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+#ifdef CONFIG_CPU_FEROCEON
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+#define CALGN(code...) code
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+#else
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+#define CALGN(code...)
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+#endif
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+
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+/*
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* Enable and disable interrupts
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*/
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#if __LINUX_ARM_ARCH__ >= 6
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@ -0,0 +1,139 @@
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From: Nicolas Pitre <nico@cam.org>
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Date: Sat, 12 Apr 2008 01:04:28 +0000 (-0400)
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Subject: [ARM] cache align memset and memzero
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X-Git-Url: http://git.kernel.org/?p=linux%2Fkernel%2Fgit%2Fnico%2Forion.git;a=commitdiff_plain;h=74fa6238bc1602038532b548b954020f06b596cc
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[ARM] cache align memset and memzero
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This is a natural extension following the previous patch.
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Non Feroceon based targets are unchanged.
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Signed-off-by: Nicolas Pitre <nico@marvell.com>
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---
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diff --git a/arch/arm/lib/memset.S b/arch/arm/lib/memset.S
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index 95b110b..cf75188 100644
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--- a/arch/arm/lib/memset.S
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+++ b/arch/arm/lib/memset.S
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@@ -39,6 +39,9 @@ ENTRY(memset)
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mov r3, r1
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cmp r2, #16
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blt 4f
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+
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+#if CALGN(1)-1 != 0
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+
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/*
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* We need an extra register for this loop - save the return address and
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* use the LR
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@@ -64,6 +67,49 @@ ENTRY(memset)
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stmneia r0!, {r1, r3, ip, lr}
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ldr lr, [sp], #4
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+#else
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+
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+/*
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+ * This version aligns the destination pointer in order to write
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+ * whole cache lines at once.
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+ */
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+
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+ stmfd sp!, {r4-r7, lr}
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+ mov r4, r1
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+ mov r5, r1
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+ mov r6, r1
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+ mov r7, r1
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+ mov ip, r1
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+ mov lr, r1
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+
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+ cmp r2, #96
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+ tstgt r0, #31
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+ ble 3f
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+
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+ and ip, r0, #31
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+ rsb ip, ip, #32
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+ sub r2, r2, ip
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+ movs ip, ip, lsl #(32 - 4)
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+ stmcsia r0!, {r4, r5, r6, r7}
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+ stmmiia r0!, {r4, r5}
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+ tst ip, #(1 << 30)
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+ mov ip, r1
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+ strne r1, [r0], #4
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+
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+3: subs r2, r2, #64
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+ stmgeia r0!, {r1, r3-r7, ip, lr}
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+ stmgeia r0!, {r1, r3-r7, ip, lr}
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+ bgt 3b
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+ ldmeqfd sp!, {r4-r7, pc}
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+
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+ tst r2, #32
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+ stmneia r0!, {r1, r3-r7, ip, lr}
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+ tst r2, #16
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+ stmneia r0!, {r4-r7}
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+ ldmfd sp!, {r4-r7, lr}
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+
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+#endif
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+
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4: tst r2, #8
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stmneia r0!, {r1, r3}
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tst r2, #4
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diff --git a/arch/arm/lib/memzero.S b/arch/arm/lib/memzero.S
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index abf2508..a9bfef5 100644
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--- a/arch/arm/lib/memzero.S
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+++ b/arch/arm/lib/memzero.S
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@@ -39,6 +39,9 @@ ENTRY(__memzero)
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*/
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cmp r1, #16 @ 1 we can skip this chunk if we
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blt 4f @ 1 have < 16 bytes
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+
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+#if CALGN(1)-1 != 0
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+
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/*
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* We need an extra register for this loop - save the return address and
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* use the LR
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@@ -64,6 +67,47 @@ ENTRY(__memzero)
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stmneia r0!, {r2, r3, ip, lr} @ 4
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ldr lr, [sp], #4 @ 1
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+#else
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+
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+/*
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+ * This version aligns the destination pointer in order to write
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+ * whole cache lines at once.
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+ */
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+
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+ stmfd sp!, {r4-r7, lr}
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+ mov r4, r2
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+ mov r5, r2
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+ mov r6, r2
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+ mov r7, r2
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+ mov ip, r2
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+ mov lr, r2
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+
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+ cmp r1, #96
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+ andgts ip, r0, #31
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+ ble 3f
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+
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+ rsb ip, ip, #32
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+ sub r1, r1, ip
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+ movs ip, ip, lsl #(32 - 4)
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+ stmcsia r0!, {r4, r5, r6, r7}
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+ stmmiia r0!, {r4, r5}
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+ movs ip, ip, lsl #2
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+ strcs r2, [r0], #4
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+
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+3: subs r1, r1, #64
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+ stmgeia r0!, {r2-r7, ip, lr}
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+ stmgeia r0!, {r2-r7, ip, lr}
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+ bgt 3b
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+ ldmeqfd sp!, {r4-r7, pc}
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+
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+ tst r1, #32
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+ stmneia r0!, {r2-r7, ip, lr}
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+ tst r1, #16
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+ stmneia r0!, {r4-r7}
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+ ldmfd sp!, {r4-r7, lr}
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+
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+#endif
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+
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4: tst r1, #8 @ 1 8 bytes or more?
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stmneia r0!, {r2, r3} @ 2
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tst r1, #4 @ 1 4 bytes or more?
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|
@ -0,0 +1,124 @@
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From: Lennert Buytenhek <buytenh@wantstofly.org>
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Date: Thu, 24 Apr 2008 05:31:46 +0000 (-0400)
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Subject: [ARM] Feroceon: speed up flushing of the entire cache
|
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X-Git-Url: http://git.kernel.org/?p=linux%2Fkernel%2Fgit%2Fnico%2Forion.git;a=commitdiff_plain;h=8c38bce5ed3a5f2c8a1cb070ba41a8889cc69257
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[ARM] Feroceon: speed up flushing of the entire cache
|
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|
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Flushing the L1 D cache with a test/clean/invalidate loop is very
|
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easy in software, but it is not the quickest way of doing it, as
|
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there is a lot of overhead involved in re-scanning the cache from
|
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the beginning every time we hit a dirty line.
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|
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This patch makes proc-feroceon.S use "clean+invalidate by set/way"
|
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loops according to possible cache configuration of Feroceon CPUs
|
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(either direct-mapped or 4-way set associative).
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|
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[nico: optimized the assembly a bit]
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Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
|
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Signed-off-by: Nicolas Pitre <nico@marvell.com>
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---
|
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|
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diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S
|
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index a02c171..968d5ad 100644
|
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--- a/arch/arm/mm/proc-feroceon.S
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+++ b/arch/arm/mm/proc-feroceon.S
|
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@@ -44,11 +44,31 @@
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*/
|
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#define CACHE_DLINESIZE 32
|
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|
||||
+ .bss
|
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+ .align 3
|
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+__cache_params_loc:
|
||||
+ .space 8
|
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+
|
||||
.text
|
||||
+__cache_params:
|
||||
+ .word __cache_params_loc
|
||||
+
|
||||
/*
|
||||
* cpu_feroceon_proc_init()
|
||||
*/
|
||||
ENTRY(cpu_feroceon_proc_init)
|
||||
+ mrc p15, 0, r0, c0, c0, 1 @ read cache type register
|
||||
+ ldr r1, __cache_params
|
||||
+ mov r2, #(16 << 5)
|
||||
+ tst r0, #(1 << 16) @ get way
|
||||
+ mov r0, r0, lsr #18 @ get cache size order
|
||||
+ movne r3, #((4 - 1) << 30) @ 4-way
|
||||
+ and r0, r0, #0xf
|
||||
+ moveq r3, #0 @ 1-way
|
||||
+ mov r2, r2, lsl r0 @ actual cache size
|
||||
+ movne r2, r2, lsr #2 @ turned into # of sets
|
||||
+ sub r2, r2, #(1 << 5)
|
||||
+ stmia r1, {r2, r3}
|
||||
mov pc, lr
|
||||
|
||||
/*
|
||||
@@ -117,11 +137,19 @@ ENTRY(feroceon_flush_user_cache_all)
|
||||
*/
|
||||
ENTRY(feroceon_flush_kern_cache_all)
|
||||
mov r2, #VM_EXEC
|
||||
- mov ip, #0
|
||||
+
|
||||
__flush_whole_cache:
|
||||
-1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
|
||||
- bne 1b
|
||||
+ ldr r1, __cache_params
|
||||
+ ldmia r1, {r1, r3}
|
||||
+1: orr ip, r1, r3
|
||||
+2: mcr p15, 0, ip, c7, c14, 2 @ clean + invalidate D set/way
|
||||
+ subs ip, ip, #(1 << 30) @ next way
|
||||
+ bcs 2b
|
||||
+ subs r1, r1, #(1 << 5) @ next set
|
||||
+ bcs 1b
|
||||
+
|
||||
tst r2, #VM_EXEC
|
||||
+ mov ip, #0
|
||||
mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
|
||||
mcrne p15, 0, ip, c7, c10, 4 @ drain WB
|
||||
mov pc, lr
|
||||
@@ -138,7 +166,6 @@ __flush_whole_cache:
|
||||
*/
|
||||
.align 5
|
||||
ENTRY(feroceon_flush_user_cache_range)
|
||||
- mov ip, #0
|
||||
sub r3, r1, r0 @ calculate total size
|
||||
cmp r3, #CACHE_DLIMIT
|
||||
bgt __flush_whole_cache
|
||||
@@ -152,6 +179,7 @@ ENTRY(feroceon_flush_user_cache_range)
|
||||
cmp r0, r1
|
||||
blo 1b
|
||||
tst r2, #VM_EXEC
|
||||
+ mov ip, #0
|
||||
mcrne p15, 0, ip, c7, c10, 4 @ drain WB
|
||||
mov pc, lr
|
||||
|
||||
@@ -306,16 +334,19 @@ ENTRY(cpu_feroceon_dcache_clean_area)
|
||||
.align 5
|
||||
ENTRY(cpu_feroceon_switch_mm)
|
||||
#ifdef CONFIG_MMU
|
||||
- mov ip, #0
|
||||
-@ && 'Clean & Invalidate whole DCache'
|
||||
-1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
|
||||
- bne 1b
|
||||
- mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
|
||||
- mcr p15, 0, ip, c7, c10, 4 @ drain WB
|
||||
+ mov r2, lr @ abuse r2 to preserve lr
|
||||
+ bl __flush_whole_cache
|
||||
+ @ if r2 contains the VM_EXEC bit then the next 2 ops are done already
|
||||
+ tst r2, #VM_EXEC
|
||||
+ mcreq p15, 0, ip, c7, c5, 0 @ invalidate I cache
|
||||
+ mcreq p15, 0, ip, c7, c10, 4 @ drain WB
|
||||
+
|
||||
mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
|
||||
mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
|
||||
-#endif
|
||||
+ mov pc, r2
|
||||
+#else
|
||||
mov pc, lr
|
||||
+#endif
|
||||
|
||||
/*
|
||||
* cpu_feroceon_set_pte_ext(ptep, pte, ext)
|
||||
|
|
@ -27,6 +27,10 @@
|
|||
+ bugfix/arm/disable-scsi_acard.patch
|
||||
##+ bugfix/arm/disable-ath5k.patch
|
||||
+ bugfix/arm/disable-r6040.patch
|
||||
+ features/arm/cache-align.patch
|
||||
+ features/arm/cache-align2.patch
|
||||
+ features/arm/speed_flush_cache.patch
|
||||
+ features/arm/5281d0.patch
|
||||
+ features/all/at76.patch
|
||||
+ bugfix/fix-hifn_795X-divdi3.patch
|
||||
+ bugfix/all/mtd-prevent-physmap-from-causing-request_module-runaway-loop-modprobe-net-pf-1.patch
|
||||
|
|
|
|||
Loading…
Reference in New Issue