112 lines
3.6 KiB
C
112 lines
3.6 KiB
C
#ifndef MPPTALK_DEFS_H
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#define MPPTALK_DEFS_H
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/*
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* Written by Oron Peled <oron@actcom.co.il>
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* Copyright (C) 2008,2009,2010 Xorcom
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*
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* All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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#include <xtalk_defs.h>
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/*
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* MPP - Managment Processor Protocol definitions
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*/
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/*
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* OP Codes:
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* MSB of op signifies a reply from device
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*/
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#define MPP_RENUM 0x0B /* Trigger USB renumeration */
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#define MPP_EEPROM_SET 0x0D
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/* AB capabilities */
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#define MPP_CAPS_GET 0x0E
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#define MPP_CAPS_GET_REPLY 0x8E
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#define MPP_CAPS_SET 0x0F
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#define MPP_DEV_SEND_START 0x05
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#define MPP_DEV_SEND_SEG 0x07
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#define MPP_DEV_SEND_END 0x09
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/* Astribank Status */
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#define MPP_STATUS_GET 0x11
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#define MPP_STATUS_GET_REPLY 0x91
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#define MPP_STATUS_GET_REPLY_V13 0x91 /* backward compat */
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/* Get extra vendor information */
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#define MPP_EXTRAINFO_GET 0x13
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#define MPP_EXTRAINFO_GET_REPLY 0x93
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#define MPP_EXTRAINFO_SET 0x15 /* Set extra vendor information */
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#define MPP_EEPROM_BLK_RD 0x27
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#define MPP_EEPROM_BLK_RD_REPLY 0xA7
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#define MPP_SER_SEND 0x37
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#define MPP_SER_RECV 0xB7
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#define MPP_RESET 0x45 /* Reset both FPGA and USB firmwares */
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#define MPP_HALF_RESET 0x47 /* Reset only FPGA firmware */
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/* Twinstar */
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#define MPP_TWS_WD_MODE_SET 0x31 /* Set watchdog off/on guard */
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#define MPP_TWS_WD_MODE_GET 0x32 /* Current watchdog mode */
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#define MPP_TWS_WD_MODE_GET_REPLY 0xB2 /* Current watchdog mode */
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#define MPP_TWS_PORT_SET 0x34 /* USB-[0/1] */
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#define MPP_TWS_PORT_GET 0x35 /* USB-[0/1] */
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#define MPP_TWS_PORT_GET_REPLY 0xB5 /* USB-[0/1] */
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#define MPP_TWS_PWR_GET 0x36 /* Power: bits -> USB ports */
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#define MPP_TWS_PWR_GET_REPLY 0xB6 /* Power: bits -> USB ports */
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/*
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* Statuses
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*/
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#define STAT_OK 0x00 /* acknowledges previous command */
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#define STAT_FAIL 0x01 /* Last command failed */
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#define STAT_RESET_FAIL 0x02 /* reset failed */
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#define STAT_NODEST 0x03 /* No destination is selected */
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#define STAT_MISMATCH 0x04 /* Data mismatch */
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#define STAT_NOACCESS 0x05 /* No access */
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#define STAT_BAD_CMD 0x06 /* Bad command */
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#define STAT_TOO_SHORT 0x07 /* Packet is too short */
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#define STAT_ERROFFS 0x08 /* Offset error */
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#define STAT_NOCODE 0x09 /* Source was not burned before */
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#define STAT_NO_LEEPROM 0x0A /* Large EEPROM was not found */
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#define STAT_NO_EEPROM 0x0B /* No EEPROM was found */
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#define STAT_WRITE_FAIL 0x0C /* Writing to device failed */
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#define STAT_FPGA_ERR 0x0D /* FPGA error */
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#define STAT_KEY_ERR 0x0E /* Bad Capabilities Key */
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#define STAT_NOCAPS_ERR 0x0F /* No matching capability */
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#define STAT_NOPWR_ERR 0x10 /* No power on USB connector */
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#define STAT_CAPS_FPGA_ERR 0x11 /* Setting of the capabilities while FPGA is loaded */
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/* EEPROM_QUERY: i2cs(ID1, ID0) */
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enum eeprom_type {
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EEPROM_TYPE_NONE = 0,
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EEPROM_TYPE_SMALL = 1,
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EEPROM_TYPE_LARGE = 2,
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EEPROM_TYPE_UNUSED = 3,
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};
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enum dev_dest {
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DEST_NONE = 0x00,
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DEST_FPGA = 0x01,
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DEST_EEPROM = 0x02,
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};
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#endif /* MPPTALK_DEFS_H */
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