Refs #963.Updated CAN driver in the STM32F2 port and the HAL drivers in all STM32F2 demo programs for compatibility with the latest ST HAL.
git-svn-id: https://svn.code.sf.net/p/openblt/code/trunk@750 5dc33758-31d5-4daf-9ae8-b24bf3d40d73
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@ -16,29 +16,13 @@
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******************************************************************************
|
******************************************************************************
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||||||
* @attention
|
* @attention
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||||||
*
|
*
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||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
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||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
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*/
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@ -97,11 +81,11 @@
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#endif /* USE_HAL_DRIVER */
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#endif /* USE_HAL_DRIVER */
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/**
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/**
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* @brief CMSIS Device version number V2.2.1
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* @brief CMSIS Device version number V2.2.3
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*/
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*/
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#define __STM32F2xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
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#define __STM32F2xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
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#define __STM32F2xx_CMSIS_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */
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#define __STM32F2xx_CMSIS_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */
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#define __STM32F2xx_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
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#define __STM32F2xx_CMSIS_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */
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#define __STM32F2xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
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#define __STM32F2xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
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#define __STM32F2xx_CMSIS_VERSION ((__STM32F2xx_CMSIS_VERSION_MAIN << 24)\
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#define __STM32F2xx_CMSIS_VERSION ((__STM32F2xx_CMSIS_VERSION_MAIN << 24)\
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|(__STM32F2xx_CMSIS_VERSION_SUB1 << 16)\
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|(__STM32F2xx_CMSIS_VERSION_SUB1 << 16)\
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@ -137,21 +121,21 @@
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*/
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*/
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typedef enum
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typedef enum
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{
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{
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RESET = 0,
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RESET = 0U,
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SET = !RESET
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SET = !RESET
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} FlagStatus, ITStatus;
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} FlagStatus, ITStatus;
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typedef enum
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typedef enum
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{
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{
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DISABLE = 0,
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DISABLE = 0U,
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ENABLE = !DISABLE
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ENABLE = !DISABLE
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} FunctionalState;
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} FunctionalState;
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#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
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#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
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typedef enum
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typedef enum
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{
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{
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ERROR = 0,
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SUCCESS = 0U,
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SUCCESS = !ERROR
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ERROR = !SUCCESS
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} ErrorStatus;
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} ErrorStatus;
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/**
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/**
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@ -2,36 +2,20 @@
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******************************************************************************
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******************************************************************************
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* @file system_stm32f2xx.h
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* @file system_stm32f2xx.h
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* @author MCD Application Team
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* @author MCD Application Team
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* @brief CMSIS Cortex-M3 Device System Source File for STM32F2xx devices.
|
* @brief CMSIS Cortex-M3 Device System Source File for STM32F2xx devices.
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******************************************************************************
|
****************************************************************************
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* @attention
|
* @attention
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||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
*
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
******************************************************************************
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
*/
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
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*
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******************************************************************************
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*/
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/** @addtogroup CMSIS
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/** @addtogroup CMSIS
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* @{
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* @{
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@ -1,136 +0,0 @@
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/* ----------------------------------------------------------------------
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* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
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*
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* $Date: 19. October 2015
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* $Revision: V.1.4.5 a
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*
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* Project: CMSIS DSP Library
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* Title: arm_common_tables.h
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*
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* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
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*
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* Target Processor: Cortex-M4/Cortex-M3
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*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions
|
|
||||||
* are met:
|
|
||||||
* - Redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer.
|
|
||||||
* - Redistributions in binary form must reproduce the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer in
|
|
||||||
* the documentation and/or other materials provided with the
|
|
||||||
* distribution.
|
|
||||||
* - Neither the name of ARM LIMITED nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this
|
|
||||||
* software without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
||||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
||||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
|
||||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
|
||||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
|
||||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
|
||||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
|
||||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
|
||||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
|
||||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
||||||
* POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
* -------------------------------------------------------------------- */
|
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||||||
|
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#ifndef _ARM_COMMON_TABLES_H
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#define _ARM_COMMON_TABLES_H
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#include "arm_math.h"
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extern const uint16_t armBitRevTable[1024];
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extern const q15_t armRecipTableQ15[64];
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extern const q31_t armRecipTableQ31[64];
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/* extern const q31_t realCoefAQ31[1024]; */
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/* extern const q31_t realCoefBQ31[1024]; */
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extern const float32_t twiddleCoef_16[32];
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extern const float32_t twiddleCoef_32[64];
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extern const float32_t twiddleCoef_64[128];
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extern const float32_t twiddleCoef_128[256];
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extern const float32_t twiddleCoef_256[512];
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extern const float32_t twiddleCoef_512[1024];
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extern const float32_t twiddleCoef_1024[2048];
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extern const float32_t twiddleCoef_2048[4096];
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extern const float32_t twiddleCoef_4096[8192];
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#define twiddleCoef twiddleCoef_4096
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extern const q31_t twiddleCoef_16_q31[24];
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extern const q31_t twiddleCoef_32_q31[48];
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extern const q31_t twiddleCoef_64_q31[96];
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extern const q31_t twiddleCoef_128_q31[192];
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extern const q31_t twiddleCoef_256_q31[384];
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extern const q31_t twiddleCoef_512_q31[768];
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extern const q31_t twiddleCoef_1024_q31[1536];
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extern const q31_t twiddleCoef_2048_q31[3072];
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extern const q31_t twiddleCoef_4096_q31[6144];
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extern const q15_t twiddleCoef_16_q15[24];
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extern const q15_t twiddleCoef_32_q15[48];
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extern const q15_t twiddleCoef_64_q15[96];
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extern const q15_t twiddleCoef_128_q15[192];
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extern const q15_t twiddleCoef_256_q15[384];
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extern const q15_t twiddleCoef_512_q15[768];
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extern const q15_t twiddleCoef_1024_q15[1536];
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extern const q15_t twiddleCoef_2048_q15[3072];
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extern const q15_t twiddleCoef_4096_q15[6144];
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extern const float32_t twiddleCoef_rfft_32[32];
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extern const float32_t twiddleCoef_rfft_64[64];
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extern const float32_t twiddleCoef_rfft_128[128];
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extern const float32_t twiddleCoef_rfft_256[256];
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extern const float32_t twiddleCoef_rfft_512[512];
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extern const float32_t twiddleCoef_rfft_1024[1024];
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extern const float32_t twiddleCoef_rfft_2048[2048];
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extern const float32_t twiddleCoef_rfft_4096[4096];
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/* floating-point bit reversal tables */
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#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )
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#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )
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#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )
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#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
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#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
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#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
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#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
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#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
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#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
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extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
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extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
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/* fixed-point bit reversal tables */
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|
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#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 )
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#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 )
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#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 )
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#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
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#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
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#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
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#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
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#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
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#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
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|
||||||
|
|
||||||
extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
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|
||||||
extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
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|
||||||
extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
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|
||||||
extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
|
|
||||||
|
|
||||||
/* Tables for Fast Math Sine and Cosine */
|
|
||||||
extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
|
|
||||||
extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
|
|
||||||
extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
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|
||||||
|
|
||||||
#endif /* ARM_COMMON_TABLES_H */
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|
|
@ -1,79 +0,0 @@
|
||||||
/* ----------------------------------------------------------------------
|
|
||||||
* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* $Date: 19. March 2015
|
|
||||||
* $Revision: V.1.4.5
|
|
||||||
*
|
|
||||||
* Project: CMSIS DSP Library
|
|
||||||
* Title: arm_const_structs.h
|
|
||||||
*
|
|
||||||
* Description: This file has constant structs that are initialized for
|
|
||||||
* user convenience. For example, some can be given as
|
|
||||||
* arguments to the arm_cfft_f32() function.
|
|
||||||
*
|
|
||||||
* Target Processor: Cortex-M4/Cortex-M3
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions
|
|
||||||
* are met:
|
|
||||||
* - Redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer.
|
|
||||||
* - Redistributions in binary form must reproduce the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer in
|
|
||||||
* the documentation and/or other materials provided with the
|
|
||||||
* distribution.
|
|
||||||
* - Neither the name of ARM LIMITED nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this
|
|
||||||
* software without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
||||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
||||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
|
||||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
|
||||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
|
||||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
|
||||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
|
||||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
|
||||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
|
||||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
||||||
* POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
* -------------------------------------------------------------------- */
|
|
||||||
|
|
||||||
#ifndef _ARM_CONST_STRUCTS_H
|
|
||||||
#define _ARM_CONST_STRUCTS_H
|
|
||||||
|
|
||||||
#include "arm_math.h"
|
|
||||||
#include "arm_common_tables.h"
|
|
||||||
|
|
||||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
|
|
||||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
|
|
||||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
|
|
||||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
|
|
||||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
|
|
||||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
|
|
||||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
|
|
||||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
|
|
||||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
|
|
||||||
|
|
||||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
|
|
||||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
|
|
||||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
|
|
||||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
|
|
||||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
|
|
||||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
|
|
||||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
|
|
||||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
|
|
||||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
|
|
||||||
|
|
||||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
|
|
||||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
|
|
||||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
|
|
||||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
|
|
||||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
|
|
||||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
|
|
||||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
|
|
||||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
|
|
||||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
|
|
||||||
|
|
||||||
#endif
|
|
File diff suppressed because it is too large
Load Diff
|
@ -1,43 +1,104 @@
|
||||||
/**************************************************************************//**
|
/**************************************************************************//**
|
||||||
* @file cmsis_armcc.h
|
* @file cmsis_armcc.h
|
||||||
* @brief CMSIS Cortex-M Core Function/Instruction Header File
|
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
|
||||||
* @version V4.30
|
* @version V5.0.4
|
||||||
* @date 20. October 2015
|
* @date 10. January 2018
|
||||||
******************************************************************************/
|
******************************************************************************/
|
||||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
/*
|
||||||
|
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||||
All rights reserved.
|
*
|
||||||
Redistribution and use in source and binary forms, with or without
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
modification, are permitted provided that the following conditions are met:
|
*
|
||||||
- Redistributions of source code must retain the above copyright
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
notice, this list of conditions and the following disclaimer.
|
* not use this file except in compliance with the License.
|
||||||
- Redistributions in binary form must reproduce the above copyright
|
* You may obtain a copy of the License at
|
||||||
notice, this list of conditions and the following disclaimer in the
|
*
|
||||||
documentation and/or other materials provided with the distribution.
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
- Neither the name of ARM nor the names of its contributors may be used
|
*
|
||||||
to endorse or promote products derived from this software without
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
specific prior written permission.
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
*
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
* See the License for the specific language governing permissions and
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
* limitations under the License.
|
||||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
*/
|
||||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
|
||||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
|
||||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
||||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
|
||||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
|
||||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
||||||
POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
---------------------------------------------------------------------------*/
|
|
||||||
|
|
||||||
|
|
||||||
#ifndef __CMSIS_ARMCC_H
|
#ifndef __CMSIS_ARMCC_H
|
||||||
#define __CMSIS_ARMCC_H
|
#define __CMSIS_ARMCC_H
|
||||||
|
|
||||||
|
|
||||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
|
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
|
||||||
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
|
#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* CMSIS compiler control architecture macros */
|
||||||
|
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
|
||||||
|
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
|
||||||
|
#define __ARM_ARCH_6M__ 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
|
||||||
|
#define __ARM_ARCH_7M__ 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
|
||||||
|
#define __ARM_ARCH_7EM__ 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* __ARM_ARCH_8M_BASE__ not applicable */
|
||||||
|
/* __ARM_ARCH_8M_MAIN__ not applicable */
|
||||||
|
|
||||||
|
|
||||||
|
/* CMSIS compiler specific defines */
|
||||||
|
#ifndef __ASM
|
||||||
|
#define __ASM __asm
|
||||||
|
#endif
|
||||||
|
#ifndef __INLINE
|
||||||
|
#define __INLINE __inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_INLINE
|
||||||
|
#define __STATIC_INLINE static __inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_FORCEINLINE
|
||||||
|
#define __STATIC_FORCEINLINE static __forceinline
|
||||||
|
#endif
|
||||||
|
#ifndef __NO_RETURN
|
||||||
|
#define __NO_RETURN __declspec(noreturn)
|
||||||
|
#endif
|
||||||
|
#ifndef __USED
|
||||||
|
#define __USED __attribute__((used))
|
||||||
|
#endif
|
||||||
|
#ifndef __WEAK
|
||||||
|
#define __WEAK __attribute__((weak))
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED
|
||||||
|
#define __PACKED __attribute__((packed))
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_STRUCT
|
||||||
|
#define __PACKED_STRUCT __packed struct
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_UNION
|
||||||
|
#define __PACKED_UNION __packed union
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||||
|
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_WRITE
|
||||||
|
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_READ
|
||||||
|
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_WRITE
|
||||||
|
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_READ
|
||||||
|
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
|
||||||
|
#endif
|
||||||
|
#ifndef __ALIGNED
|
||||||
|
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||||
|
#endif
|
||||||
|
#ifndef __RESTRICT
|
||||||
|
#define __RESTRICT __restrict
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* ########################### Core Function Access ########################### */
|
/* ########################### Core Function Access ########################### */
|
||||||
|
@ -46,7 +107,19 @@
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Enable IRQ Interrupts
|
||||||
|
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
|
||||||
|
Can only be executed in Privileged modes.
|
||||||
|
*/
|
||||||
/* intrinsic void __enable_irq(); */
|
/* intrinsic void __enable_irq(); */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Disable IRQ Interrupts
|
||||||
|
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
|
||||||
|
Can only be executed in Privileged modes.
|
||||||
|
*/
|
||||||
/* intrinsic void __disable_irq(); */
|
/* intrinsic void __disable_irq(); */
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -181,7 +254,8 @@ __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
|
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Enable FIQ
|
\brief Enable FIQ
|
||||||
|
@ -256,14 +330,13 @@ __STATIC_INLINE uint32_t __get_FAULTMASK(void)
|
||||||
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||||
{
|
{
|
||||||
register uint32_t __regFaultMask __ASM("faultmask");
|
register uint32_t __regFaultMask __ASM("faultmask");
|
||||||
__regFaultMask = (faultMask & (uint32_t)1);
|
__regFaultMask = (faultMask & (uint32_t)1U);
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
|
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||||
|
|
||||||
|
|
||||||
#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Get FPSCR
|
\brief Get FPSCR
|
||||||
\details Returns the current value of the Floating Point Status/Control register.
|
\details Returns the current value of the Floating Point Status/Control register.
|
||||||
|
@ -271,7 +344,8 @@ __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t __get_FPSCR(void)
|
__STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||||
{
|
{
|
||||||
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
|
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||||
|
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||||
register uint32_t __regfpscr __ASM("fpscr");
|
register uint32_t __regfpscr __ASM("fpscr");
|
||||||
return(__regfpscr);
|
return(__regfpscr);
|
||||||
#else
|
#else
|
||||||
|
@ -287,15 +361,15 @@ __STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||||
{
|
{
|
||||||
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
|
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||||
|
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||||
register uint32_t __regfpscr __ASM("fpscr");
|
register uint32_t __regfpscr __ASM("fpscr");
|
||||||
__regfpscr = (fpscr);
|
__regfpscr = (fpscr);
|
||||||
|
#else
|
||||||
|
(void)fpscr;
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/*@} end of CMSIS_Core_RegAccFunctions */
|
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||||
|
|
||||||
|
@ -369,9 +443,10 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||||
__schedule_barrier();\
|
__schedule_barrier();\
|
||||||
} while (0U)
|
} while (0U)
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Reverse byte order (32 bit)
|
\brief Reverse byte order (32 bit)
|
||||||
\details Reverses the byte order in integer value.
|
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
|
||||||
\param [in] value Value to reverse
|
\param [in] value Value to reverse
|
||||||
\return Reversed value
|
\return Reversed value
|
||||||
*/
|
*/
|
||||||
|
@ -380,7 +455,7 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Reverse byte order (16 bit)
|
\brief Reverse byte order (16 bit)
|
||||||
\details Reverses the byte order in two unsigned short values.
|
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
|
||||||
\param [in] value Value to reverse
|
\param [in] value Value to reverse
|
||||||
\return Reversed value
|
\return Reversed value
|
||||||
*/
|
*/
|
||||||
|
@ -392,14 +467,15 @@ __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(u
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Reverse byte order in signed short value
|
\brief Reverse byte order (16 bit)
|
||||||
\details Reverses the byte order in a signed short value with sign extension to integer.
|
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
|
||||||
\param [in] value Value to reverse
|
\param [in] value Value to reverse
|
||||||
\return Reversed value
|
\return Reversed value
|
||||||
*/
|
*/
|
||||||
#ifndef __NO_EMBEDDED_ASM
|
#ifndef __NO_EMBEDDED_ASM
|
||||||
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
|
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
|
||||||
{
|
{
|
||||||
revsh r0, r0
|
revsh r0, r0
|
||||||
bx lr
|
bx lr
|
||||||
|
@ -410,8 +486,8 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
|
||||||
/**
|
/**
|
||||||
\brief Rotate Right in unsigned value (32 bit)
|
\brief Rotate Right in unsigned value (32 bit)
|
||||||
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||||
\param [in] value Value to rotate
|
\param [in] op1 Value to rotate
|
||||||
\param [in] value Number of Bits to rotate
|
\param [in] op2 Number of Bits to rotate
|
||||||
\return Rotated value
|
\return Rotated value
|
||||||
*/
|
*/
|
||||||
#define __ROR __ror
|
#define __ROR __ror
|
||||||
|
@ -433,23 +509,24 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
|
||||||
\param [in] value Value to reverse
|
\param [in] value Value to reverse
|
||||||
\return Reversed value
|
\return Reversed value
|
||||||
*/
|
*/
|
||||||
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
|
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||||
#define __RBIT __rbit
|
#define __RBIT __rbit
|
||||||
#else
|
#else
|
||||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||||
{
|
{
|
||||||
uint32_t result;
|
uint32_t result;
|
||||||
int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
|
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
|
||||||
|
|
||||||
result = value; /* r will be reversed bits of v; first get LSB of v */
|
result = value; /* r will be reversed bits of v; first get LSB of v */
|
||||||
for (value >>= 1U; value; value >>= 1U)
|
for (value >>= 1U; value != 0U; value >>= 1U)
|
||||||
{
|
{
|
||||||
result <<= 1U;
|
result <<= 1U;
|
||||||
result |= value & 1U;
|
result |= value & 1U;
|
||||||
s--;
|
s--;
|
||||||
}
|
}
|
||||||
result <<= s; /* shift when v's highest bits are zero */
|
result <<= s; /* shift when v's highest bits are zero */
|
||||||
return(result);
|
return result;
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
@ -463,7 +540,8 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||||
#define __CLZ __clz
|
#define __CLZ __clz
|
||||||
|
|
||||||
|
|
||||||
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
|
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief LDR Exclusive (8 bit)
|
\brief LDR Exclusive (8 bit)
|
||||||
|
@ -645,7 +723,60 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
|
||||||
*/
|
*/
|
||||||
#define __STRT(value, ptr) __strt(value, ptr)
|
#define __STRT(value, ptr) __strt(value, ptr)
|
||||||
|
|
||||||
#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
|
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Signed Saturate
|
||||||
|
\details Saturates a signed value.
|
||||||
|
\param [in] value Value to be saturated
|
||||||
|
\param [in] sat Bit position to saturate to (1..32)
|
||||||
|
\return Saturated value
|
||||||
|
*/
|
||||||
|
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
|
||||||
|
{
|
||||||
|
if ((sat >= 1U) && (sat <= 32U))
|
||||||
|
{
|
||||||
|
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
|
||||||
|
const int32_t min = -1 - max ;
|
||||||
|
if (val > max)
|
||||||
|
{
|
||||||
|
return max;
|
||||||
|
}
|
||||||
|
else if (val < min)
|
||||||
|
{
|
||||||
|
return min;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return val;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Unsigned Saturate
|
||||||
|
\details Saturates an unsigned value.
|
||||||
|
\param [in] value Value to be saturated
|
||||||
|
\param [in] sat Bit position to saturate to (0..31)
|
||||||
|
\return Saturated value
|
||||||
|
*/
|
||||||
|
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
|
||||||
|
{
|
||||||
|
if (sat <= 31U)
|
||||||
|
{
|
||||||
|
const uint32_t max = ((1U << sat) - 1U);
|
||||||
|
if (val > (int32_t)max)
|
||||||
|
{
|
||||||
|
return max;
|
||||||
|
}
|
||||||
|
else if (val < 0)
|
||||||
|
{
|
||||||
|
return 0U;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return (uint32_t)val;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||||
|
|
||||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||||
|
|
||||||
|
@ -656,7 +787,7 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */
|
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||||
|
|
||||||
#define __SADD8 __sadd8
|
#define __SADD8 __sadd8
|
||||||
#define __QADD8 __qadd8
|
#define __QADD8 __qadd8
|
||||||
|
@ -727,7 +858,7 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
|
||||||
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
|
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
|
||||||
((int64_t)(ARG3) << 32U) ) >> 32U))
|
((int64_t)(ARG3) << 32U) ) >> 32U))
|
||||||
|
|
||||||
#endif /* (__CORTEX_M >= 0x04) */
|
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||||
/*@} end of group CMSIS_SIMD_intrinsics */
|
/*@} end of group CMSIS_SIMD_intrinsics */
|
||||||
|
|
||||||
|
|
||||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,266 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file cmsis_compiler.h
|
||||||
|
* @brief CMSIS compiler generic header file
|
||||||
|
* @version V5.0.4
|
||||||
|
* @date 10. January 2018
|
||||||
|
******************************************************************************/
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __CMSIS_COMPILER_H
|
||||||
|
#define __CMSIS_COMPILER_H
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Arm Compiler 4/5
|
||||||
|
*/
|
||||||
|
#if defined ( __CC_ARM )
|
||||||
|
#include "cmsis_armcc.h"
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Arm Compiler 6 (armclang)
|
||||||
|
*/
|
||||||
|
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||||
|
#include "cmsis_armclang.h"
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* GNU Compiler
|
||||||
|
*/
|
||||||
|
#elif defined ( __GNUC__ )
|
||||||
|
#include "cmsis_gcc.h"
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* IAR Compiler
|
||||||
|
*/
|
||||||
|
#elif defined ( __ICCARM__ )
|
||||||
|
#include <cmsis_iccarm.h>
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* TI Arm Compiler
|
||||||
|
*/
|
||||||
|
#elif defined ( __TI_ARM__ )
|
||||||
|
#include <cmsis_ccs.h>
|
||||||
|
|
||||||
|
#ifndef __ASM
|
||||||
|
#define __ASM __asm
|
||||||
|
#endif
|
||||||
|
#ifndef __INLINE
|
||||||
|
#define __INLINE inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_INLINE
|
||||||
|
#define __STATIC_INLINE static inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_FORCEINLINE
|
||||||
|
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||||
|
#endif
|
||||||
|
#ifndef __NO_RETURN
|
||||||
|
#define __NO_RETURN __attribute__((noreturn))
|
||||||
|
#endif
|
||||||
|
#ifndef __USED
|
||||||
|
#define __USED __attribute__((used))
|
||||||
|
#endif
|
||||||
|
#ifndef __WEAK
|
||||||
|
#define __WEAK __attribute__((weak))
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED
|
||||||
|
#define __PACKED __attribute__((packed))
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_STRUCT
|
||||||
|
#define __PACKED_STRUCT struct __attribute__((packed))
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_UNION
|
||||||
|
#define __PACKED_UNION union __attribute__((packed))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||||
|
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_WRITE
|
||||||
|
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||||
|
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_READ
|
||||||
|
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||||
|
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_WRITE
|
||||||
|
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_READ
|
||||||
|
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __ALIGNED
|
||||||
|
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||||
|
#endif
|
||||||
|
#ifndef __RESTRICT
|
||||||
|
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||||
|
#define __RESTRICT
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* TASKING Compiler
|
||||||
|
*/
|
||||||
|
#elif defined ( __TASKING__ )
|
||||||
|
/*
|
||||||
|
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||||
|
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||||
|
* Including the CMSIS ones.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __ASM
|
||||||
|
#define __ASM __asm
|
||||||
|
#endif
|
||||||
|
#ifndef __INLINE
|
||||||
|
#define __INLINE inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_INLINE
|
||||||
|
#define __STATIC_INLINE static inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_FORCEINLINE
|
||||||
|
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||||
|
#endif
|
||||||
|
#ifndef __NO_RETURN
|
||||||
|
#define __NO_RETURN __attribute__((noreturn))
|
||||||
|
#endif
|
||||||
|
#ifndef __USED
|
||||||
|
#define __USED __attribute__((used))
|
||||||
|
#endif
|
||||||
|
#ifndef __WEAK
|
||||||
|
#define __WEAK __attribute__((weak))
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED
|
||||||
|
#define __PACKED __packed__
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_STRUCT
|
||||||
|
#define __PACKED_STRUCT struct __packed__
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_UNION
|
||||||
|
#define __PACKED_UNION union __packed__
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||||
|
struct __packed__ T_UINT32 { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_WRITE
|
||||||
|
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||||
|
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_READ
|
||||||
|
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||||
|
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_WRITE
|
||||||
|
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_READ
|
||||||
|
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __ALIGNED
|
||||||
|
#define __ALIGNED(x) __align(x)
|
||||||
|
#endif
|
||||||
|
#ifndef __RESTRICT
|
||||||
|
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||||
|
#define __RESTRICT
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* COSMIC Compiler
|
||||||
|
*/
|
||||||
|
#elif defined ( __CSMC__ )
|
||||||
|
#include <cmsis_csm.h>
|
||||||
|
|
||||||
|
#ifndef __ASM
|
||||||
|
#define __ASM _asm
|
||||||
|
#endif
|
||||||
|
#ifndef __INLINE
|
||||||
|
#define __INLINE inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_INLINE
|
||||||
|
#define __STATIC_INLINE static inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_FORCEINLINE
|
||||||
|
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||||
|
#endif
|
||||||
|
#ifndef __NO_RETURN
|
||||||
|
// NO RETURN is automatically detected hence no warning here
|
||||||
|
#define __NO_RETURN
|
||||||
|
#endif
|
||||||
|
#ifndef __USED
|
||||||
|
#warning No compiler specific solution for __USED. __USED is ignored.
|
||||||
|
#define __USED
|
||||||
|
#endif
|
||||||
|
#ifndef __WEAK
|
||||||
|
#define __WEAK __weak
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED
|
||||||
|
#define __PACKED @packed
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_STRUCT
|
||||||
|
#define __PACKED_STRUCT @packed struct
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_UNION
|
||||||
|
#define __PACKED_UNION @packed union
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||||
|
@packed struct T_UINT32 { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_WRITE
|
||||||
|
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||||
|
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_READ
|
||||||
|
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||||
|
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_WRITE
|
||||||
|
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_READ
|
||||||
|
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __ALIGNED
|
||||||
|
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
|
||||||
|
#define __ALIGNED(x)
|
||||||
|
#endif
|
||||||
|
#ifndef __RESTRICT
|
||||||
|
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||||
|
#define __RESTRICT
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#else
|
||||||
|
#error Unknown compiler.
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* __CMSIS_COMPILER_H */
|
||||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,935 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file cmsis_iccarm.h
|
||||||
|
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
|
||||||
|
* @version V5.0.7
|
||||||
|
* @date 19. June 2018
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
//------------------------------------------------------------------------------
|
||||||
|
//
|
||||||
|
// Copyright (c) 2017-2018 IAR Systems
|
||||||
|
//
|
||||||
|
// Licensed under the Apache License, Version 2.0 (the "License")
|
||||||
|
// you may not use this file except in compliance with the License.
|
||||||
|
// You may obtain a copy of the License at
|
||||||
|
// http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
//
|
||||||
|
// Unless required by applicable law or agreed to in writing, software
|
||||||
|
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
// See the License for the specific language governing permissions and
|
||||||
|
// limitations under the License.
|
||||||
|
//
|
||||||
|
//------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef __CMSIS_ICCARM_H__
|
||||||
|
#define __CMSIS_ICCARM_H__
|
||||||
|
|
||||||
|
#ifndef __ICCARM__
|
||||||
|
#error This file should only be compiled by ICCARM
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#pragma system_include
|
||||||
|
|
||||||
|
#define __IAR_FT _Pragma("inline=forced") __intrinsic
|
||||||
|
|
||||||
|
#if (__VER__ >= 8000000)
|
||||||
|
#define __ICCARM_V8 1
|
||||||
|
#else
|
||||||
|
#define __ICCARM_V8 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __ALIGNED
|
||||||
|
#if __ICCARM_V8
|
||||||
|
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||||
|
#elif (__VER__ >= 7080000)
|
||||||
|
/* Needs IAR language extensions */
|
||||||
|
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||||
|
#else
|
||||||
|
#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
|
||||||
|
#define __ALIGNED(x)
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/* Define compiler macros for CPU architecture, used in CMSIS 5.
|
||||||
|
*/
|
||||||
|
#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
|
||||||
|
/* Macros already defined */
|
||||||
|
#else
|
||||||
|
#if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
|
||||||
|
#define __ARM_ARCH_8M_MAIN__ 1
|
||||||
|
#elif defined(__ARM8M_BASELINE__)
|
||||||
|
#define __ARM_ARCH_8M_BASE__ 1
|
||||||
|
#elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
|
||||||
|
#if __ARM_ARCH == 6
|
||||||
|
#define __ARM_ARCH_6M__ 1
|
||||||
|
#elif __ARM_ARCH == 7
|
||||||
|
#if __ARM_FEATURE_DSP
|
||||||
|
#define __ARM_ARCH_7EM__ 1
|
||||||
|
#else
|
||||||
|
#define __ARM_ARCH_7M__ 1
|
||||||
|
#endif
|
||||||
|
#endif /* __ARM_ARCH */
|
||||||
|
#endif /* __ARM_ARCH_PROFILE == 'M' */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Alternativ core deduction for older ICCARM's */
|
||||||
|
#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
|
||||||
|
!defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
|
||||||
|
#if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
|
||||||
|
#define __ARM_ARCH_6M__ 1
|
||||||
|
#elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
|
||||||
|
#define __ARM_ARCH_7M__ 1
|
||||||
|
#elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
|
||||||
|
#define __ARM_ARCH_7EM__ 1
|
||||||
|
#elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
|
||||||
|
#define __ARM_ARCH_8M_BASE__ 1
|
||||||
|
#elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
|
||||||
|
#define __ARM_ARCH_8M_MAIN__ 1
|
||||||
|
#elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
|
||||||
|
#define __ARM_ARCH_8M_MAIN__ 1
|
||||||
|
#else
|
||||||
|
#error "Unknown target."
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
|
||||||
|
#define __IAR_M0_FAMILY 1
|
||||||
|
#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
|
||||||
|
#define __IAR_M0_FAMILY 1
|
||||||
|
#else
|
||||||
|
#define __IAR_M0_FAMILY 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef __ASM
|
||||||
|
#define __ASM __asm
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __INLINE
|
||||||
|
#define __INLINE inline
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __NO_RETURN
|
||||||
|
#if __ICCARM_V8
|
||||||
|
#define __NO_RETURN __attribute__((__noreturn__))
|
||||||
|
#else
|
||||||
|
#define __NO_RETURN _Pragma("object_attribute=__noreturn")
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __PACKED
|
||||||
|
#if __ICCARM_V8
|
||||||
|
#define __PACKED __attribute__((packed, aligned(1)))
|
||||||
|
#else
|
||||||
|
/* Needs IAR language extensions */
|
||||||
|
#define __PACKED __packed
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __PACKED_STRUCT
|
||||||
|
#if __ICCARM_V8
|
||||||
|
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
|
||||||
|
#else
|
||||||
|
/* Needs IAR language extensions */
|
||||||
|
#define __PACKED_STRUCT __packed struct
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __PACKED_UNION
|
||||||
|
#if __ICCARM_V8
|
||||||
|
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
|
||||||
|
#else
|
||||||
|
/* Needs IAR language extensions */
|
||||||
|
#define __PACKED_UNION __packed union
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __RESTRICT
|
||||||
|
#define __RESTRICT __restrict
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __STATIC_INLINE
|
||||||
|
#define __STATIC_INLINE static inline
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __FORCEINLINE
|
||||||
|
#define __FORCEINLINE _Pragma("inline=forced")
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __STATIC_FORCEINLINE
|
||||||
|
#define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __UNALIGNED_UINT16_READ
|
||||||
|
#pragma language=save
|
||||||
|
#pragma language=extended
|
||||||
|
__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
|
||||||
|
{
|
||||||
|
return *(__packed uint16_t*)(ptr);
|
||||||
|
}
|
||||||
|
#pragma language=restore
|
||||||
|
#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef __UNALIGNED_UINT16_WRITE
|
||||||
|
#pragma language=save
|
||||||
|
#pragma language=extended
|
||||||
|
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
|
||||||
|
{
|
||||||
|
*(__packed uint16_t*)(ptr) = val;;
|
||||||
|
}
|
||||||
|
#pragma language=restore
|
||||||
|
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __UNALIGNED_UINT32_READ
|
||||||
|
#pragma language=save
|
||||||
|
#pragma language=extended
|
||||||
|
__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
|
||||||
|
{
|
||||||
|
return *(__packed uint32_t*)(ptr);
|
||||||
|
}
|
||||||
|
#pragma language=restore
|
||||||
|
#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __UNALIGNED_UINT32_WRITE
|
||||||
|
#pragma language=save
|
||||||
|
#pragma language=extended
|
||||||
|
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
|
||||||
|
{
|
||||||
|
*(__packed uint32_t*)(ptr) = val;;
|
||||||
|
}
|
||||||
|
#pragma language=restore
|
||||||
|
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||||
|
#pragma language=save
|
||||||
|
#pragma language=extended
|
||||||
|
__packed struct __iar_u32 { uint32_t v; };
|
||||||
|
#pragma language=restore
|
||||||
|
#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __USED
|
||||||
|
#if __ICCARM_V8
|
||||||
|
#define __USED __attribute__((used))
|
||||||
|
#else
|
||||||
|
#define __USED _Pragma("__root")
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __WEAK
|
||||||
|
#if __ICCARM_V8
|
||||||
|
#define __WEAK __attribute__((weak))
|
||||||
|
#else
|
||||||
|
#define __WEAK _Pragma("__weak")
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef __ICCARM_INTRINSICS_VERSION__
|
||||||
|
#define __ICCARM_INTRINSICS_VERSION__ 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if __ICCARM_INTRINSICS_VERSION__ == 2
|
||||||
|
|
||||||
|
#if defined(__CLZ)
|
||||||
|
#undef __CLZ
|
||||||
|
#endif
|
||||||
|
#if defined(__REVSH)
|
||||||
|
#undef __REVSH
|
||||||
|
#endif
|
||||||
|
#if defined(__RBIT)
|
||||||
|
#undef __RBIT
|
||||||
|
#endif
|
||||||
|
#if defined(__SSAT)
|
||||||
|
#undef __SSAT
|
||||||
|
#endif
|
||||||
|
#if defined(__USAT)
|
||||||
|
#undef __USAT
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "iccarm_builtin.h"
|
||||||
|
|
||||||
|
#define __disable_fault_irq __iar_builtin_disable_fiq
|
||||||
|
#define __disable_irq __iar_builtin_disable_interrupt
|
||||||
|
#define __enable_fault_irq __iar_builtin_enable_fiq
|
||||||
|
#define __enable_irq __iar_builtin_enable_interrupt
|
||||||
|
#define __arm_rsr __iar_builtin_rsr
|
||||||
|
#define __arm_wsr __iar_builtin_wsr
|
||||||
|
|
||||||
|
|
||||||
|
#define __get_APSR() (__arm_rsr("APSR"))
|
||||||
|
#define __get_BASEPRI() (__arm_rsr("BASEPRI"))
|
||||||
|
#define __get_CONTROL() (__arm_rsr("CONTROL"))
|
||||||
|
#define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
|
||||||
|
|
||||||
|
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||||
|
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||||
|
#define __get_FPSCR() (__arm_rsr("FPSCR"))
|
||||||
|
#define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
|
||||||
|
#else
|
||||||
|
#define __get_FPSCR() ( 0 )
|
||||||
|
#define __set_FPSCR(VALUE) ((void)VALUE)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define __get_IPSR() (__arm_rsr("IPSR"))
|
||||||
|
#define __get_MSP() (__arm_rsr("MSP"))
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||||
|
#define __get_MSPLIM() (0U)
|
||||||
|
#else
|
||||||
|
#define __get_MSPLIM() (__arm_rsr("MSPLIM"))
|
||||||
|
#endif
|
||||||
|
#define __get_PRIMASK() (__arm_rsr("PRIMASK"))
|
||||||
|
#define __get_PSP() (__arm_rsr("PSP"))
|
||||||
|
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||||
|
#define __get_PSPLIM() (0U)
|
||||||
|
#else
|
||||||
|
#define __get_PSPLIM() (__arm_rsr("PSPLIM"))
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define __get_xPSR() (__arm_rsr("xPSR"))
|
||||||
|
|
||||||
|
#define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
|
||||||
|
#define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
|
||||||
|
#define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
|
||||||
|
#define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
|
||||||
|
#define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
|
||||||
|
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||||
|
#define __set_MSPLIM(VALUE) ((void)(VALUE))
|
||||||
|
#else
|
||||||
|
#define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
|
||||||
|
#endif
|
||||||
|
#define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
|
||||||
|
#define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||||
|
#define __set_PSPLIM(VALUE) ((void)(VALUE))
|
||||||
|
#else
|
||||||
|
#define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
|
||||||
|
#define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
|
||||||
|
#define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
|
||||||
|
#define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
|
||||||
|
#define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
|
||||||
|
#define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
|
||||||
|
#define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
|
||||||
|
#define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
|
||||||
|
#define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
|
||||||
|
#define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
|
||||||
|
#define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
|
||||||
|
#define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
|
||||||
|
#define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
|
||||||
|
#define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
|
||||||
|
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||||
|
#define __TZ_get_PSPLIM_NS() (0U)
|
||||||
|
#define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
|
||||||
|
#else
|
||||||
|
#define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
|
||||||
|
#define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
|
||||||
|
#define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
|
||||||
|
|
||||||
|
#define __NOP __iar_builtin_no_operation
|
||||||
|
|
||||||
|
#define __CLZ __iar_builtin_CLZ
|
||||||
|
#define __CLREX __iar_builtin_CLREX
|
||||||
|
|
||||||
|
#define __DMB __iar_builtin_DMB
|
||||||
|
#define __DSB __iar_builtin_DSB
|
||||||
|
#define __ISB __iar_builtin_ISB
|
||||||
|
|
||||||
|
#define __LDREXB __iar_builtin_LDREXB
|
||||||
|
#define __LDREXH __iar_builtin_LDREXH
|
||||||
|
#define __LDREXW __iar_builtin_LDREX
|
||||||
|
|
||||||
|
#define __RBIT __iar_builtin_RBIT
|
||||||
|
#define __REV __iar_builtin_REV
|
||||||
|
#define __REV16 __iar_builtin_REV16
|
||||||
|
|
||||||
|
__IAR_FT int16_t __REVSH(int16_t val)
|
||||||
|
{
|
||||||
|
return (int16_t) __iar_builtin_REVSH(val);
|
||||||
|
}
|
||||||
|
|
||||||
|
#define __ROR __iar_builtin_ROR
|
||||||
|
#define __RRX __iar_builtin_RRX
|
||||||
|
|
||||||
|
#define __SEV __iar_builtin_SEV
|
||||||
|
|
||||||
|
#if !__IAR_M0_FAMILY
|
||||||
|
#define __SSAT __iar_builtin_SSAT
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define __STREXB __iar_builtin_STREXB
|
||||||
|
#define __STREXH __iar_builtin_STREXH
|
||||||
|
#define __STREXW __iar_builtin_STREX
|
||||||
|
|
||||||
|
#if !__IAR_M0_FAMILY
|
||||||
|
#define __USAT __iar_builtin_USAT
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define __WFE __iar_builtin_WFE
|
||||||
|
#define __WFI __iar_builtin_WFI
|
||||||
|
|
||||||
|
#if __ARM_MEDIA__
|
||||||
|
#define __SADD8 __iar_builtin_SADD8
|
||||||
|
#define __QADD8 __iar_builtin_QADD8
|
||||||
|
#define __SHADD8 __iar_builtin_SHADD8
|
||||||
|
#define __UADD8 __iar_builtin_UADD8
|
||||||
|
#define __UQADD8 __iar_builtin_UQADD8
|
||||||
|
#define __UHADD8 __iar_builtin_UHADD8
|
||||||
|
#define __SSUB8 __iar_builtin_SSUB8
|
||||||
|
#define __QSUB8 __iar_builtin_QSUB8
|
||||||
|
#define __SHSUB8 __iar_builtin_SHSUB8
|
||||||
|
#define __USUB8 __iar_builtin_USUB8
|
||||||
|
#define __UQSUB8 __iar_builtin_UQSUB8
|
||||||
|
#define __UHSUB8 __iar_builtin_UHSUB8
|
||||||
|
#define __SADD16 __iar_builtin_SADD16
|
||||||
|
#define __QADD16 __iar_builtin_QADD16
|
||||||
|
#define __SHADD16 __iar_builtin_SHADD16
|
||||||
|
#define __UADD16 __iar_builtin_UADD16
|
||||||
|
#define __UQADD16 __iar_builtin_UQADD16
|
||||||
|
#define __UHADD16 __iar_builtin_UHADD16
|
||||||
|
#define __SSUB16 __iar_builtin_SSUB16
|
||||||
|
#define __QSUB16 __iar_builtin_QSUB16
|
||||||
|
#define __SHSUB16 __iar_builtin_SHSUB16
|
||||||
|
#define __USUB16 __iar_builtin_USUB16
|
||||||
|
#define __UQSUB16 __iar_builtin_UQSUB16
|
||||||
|
#define __UHSUB16 __iar_builtin_UHSUB16
|
||||||
|
#define __SASX __iar_builtin_SASX
|
||||||
|
#define __QASX __iar_builtin_QASX
|
||||||
|
#define __SHASX __iar_builtin_SHASX
|
||||||
|
#define __UASX __iar_builtin_UASX
|
||||||
|
#define __UQASX __iar_builtin_UQASX
|
||||||
|
#define __UHASX __iar_builtin_UHASX
|
||||||
|
#define __SSAX __iar_builtin_SSAX
|
||||||
|
#define __QSAX __iar_builtin_QSAX
|
||||||
|
#define __SHSAX __iar_builtin_SHSAX
|
||||||
|
#define __USAX __iar_builtin_USAX
|
||||||
|
#define __UQSAX __iar_builtin_UQSAX
|
||||||
|
#define __UHSAX __iar_builtin_UHSAX
|
||||||
|
#define __USAD8 __iar_builtin_USAD8
|
||||||
|
#define __USADA8 __iar_builtin_USADA8
|
||||||
|
#define __SSAT16 __iar_builtin_SSAT16
|
||||||
|
#define __USAT16 __iar_builtin_USAT16
|
||||||
|
#define __UXTB16 __iar_builtin_UXTB16
|
||||||
|
#define __UXTAB16 __iar_builtin_UXTAB16
|
||||||
|
#define __SXTB16 __iar_builtin_SXTB16
|
||||||
|
#define __SXTAB16 __iar_builtin_SXTAB16
|
||||||
|
#define __SMUAD __iar_builtin_SMUAD
|
||||||
|
#define __SMUADX __iar_builtin_SMUADX
|
||||||
|
#define __SMMLA __iar_builtin_SMMLA
|
||||||
|
#define __SMLAD __iar_builtin_SMLAD
|
||||||
|
#define __SMLADX __iar_builtin_SMLADX
|
||||||
|
#define __SMLALD __iar_builtin_SMLALD
|
||||||
|
#define __SMLALDX __iar_builtin_SMLALDX
|
||||||
|
#define __SMUSD __iar_builtin_SMUSD
|
||||||
|
#define __SMUSDX __iar_builtin_SMUSDX
|
||||||
|
#define __SMLSD __iar_builtin_SMLSD
|
||||||
|
#define __SMLSDX __iar_builtin_SMLSDX
|
||||||
|
#define __SMLSLD __iar_builtin_SMLSLD
|
||||||
|
#define __SMLSLDX __iar_builtin_SMLSLDX
|
||||||
|
#define __SEL __iar_builtin_SEL
|
||||||
|
#define __QADD __iar_builtin_QADD
|
||||||
|
#define __QSUB __iar_builtin_QSUB
|
||||||
|
#define __PKHBT __iar_builtin_PKHBT
|
||||||
|
#define __PKHTB __iar_builtin_PKHTB
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
|
||||||
|
|
||||||
|
#if __IAR_M0_FAMILY
|
||||||
|
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
|
||||||
|
#define __CLZ __cmsis_iar_clz_not_active
|
||||||
|
#define __SSAT __cmsis_iar_ssat_not_active
|
||||||
|
#define __USAT __cmsis_iar_usat_not_active
|
||||||
|
#define __RBIT __cmsis_iar_rbit_not_active
|
||||||
|
#define __get_APSR __cmsis_iar_get_APSR_not_active
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||||
|
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
|
||||||
|
#define __get_FPSCR __cmsis_iar_get_FPSR_not_active
|
||||||
|
#define __set_FPSCR __cmsis_iar_set_FPSR_not_active
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef __INTRINSICS_INCLUDED
|
||||||
|
#error intrinsics.h is already included previously!
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include <intrinsics.h>
|
||||||
|
|
||||||
|
#if __IAR_M0_FAMILY
|
||||||
|
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
|
||||||
|
#undef __CLZ
|
||||||
|
#undef __SSAT
|
||||||
|
#undef __USAT
|
||||||
|
#undef __RBIT
|
||||||
|
#undef __get_APSR
|
||||||
|
|
||||||
|
__STATIC_INLINE uint8_t __CLZ(uint32_t data)
|
||||||
|
{
|
||||||
|
if (data == 0U) { return 32U; }
|
||||||
|
|
||||||
|
uint32_t count = 0U;
|
||||||
|
uint32_t mask = 0x80000000U;
|
||||||
|
|
||||||
|
while ((data & mask) == 0U)
|
||||||
|
{
|
||||||
|
count += 1U;
|
||||||
|
mask = mask >> 1U;
|
||||||
|
}
|
||||||
|
return count;
|
||||||
|
}
|
||||||
|
|
||||||
|
__STATIC_INLINE uint32_t __RBIT(uint32_t v)
|
||||||
|
{
|
||||||
|
uint8_t sc = 31U;
|
||||||
|
uint32_t r = v;
|
||||||
|
for (v >>= 1U; v; v >>= 1U)
|
||||||
|
{
|
||||||
|
r <<= 1U;
|
||||||
|
r |= v & 1U;
|
||||||
|
sc--;
|
||||||
|
}
|
||||||
|
return (r << sc);
|
||||||
|
}
|
||||||
|
|
||||||
|
__STATIC_INLINE uint32_t __get_APSR(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__asm("MRS %0,APSR" : "=r" (res));
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||||
|
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
|
||||||
|
#undef __get_FPSCR
|
||||||
|
#undef __set_FPSCR
|
||||||
|
#define __get_FPSCR() (0)
|
||||||
|
#define __set_FPSCR(VALUE) ((void)VALUE)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#pragma diag_suppress=Pe940
|
||||||
|
#pragma diag_suppress=Pe177
|
||||||
|
|
||||||
|
#define __enable_irq __enable_interrupt
|
||||||
|
#define __disable_irq __disable_interrupt
|
||||||
|
#define __NOP __no_operation
|
||||||
|
|
||||||
|
#define __get_xPSR __get_PSR
|
||||||
|
|
||||||
|
#if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
|
||||||
|
{
|
||||||
|
return __LDREX((unsigned long *)ptr);
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
|
||||||
|
{
|
||||||
|
return __STREX(value, (unsigned long *)ptr);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
|
||||||
|
#if (__CORTEX_M >= 0x03)
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __RRX(uint32_t value)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
__ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __set_BASEPRI_MAX(uint32_t value)
|
||||||
|
{
|
||||||
|
__asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
#define __enable_fault_irq __enable_fiq
|
||||||
|
#define __disable_fault_irq __disable_fiq
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* (__CORTEX_M >= 0x03) */
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
|
||||||
|
}
|
||||||
|
|
||||||
|
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __get_MSPLIM(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||||
|
res = 0U;
|
||||||
|
#else
|
||||||
|
__asm volatile("MRS %0,MSPLIM" : "=r" (res));
|
||||||
|
#endif
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __set_MSPLIM(uint32_t value)
|
||||||
|
{
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||||
|
(void)value;
|
||||||
|
#else
|
||||||
|
__asm volatile("MSR MSPLIM,%0" :: "r" (value));
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __get_PSPLIM(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||||
|
res = 0U;
|
||||||
|
#else
|
||||||
|
__asm volatile("MRS %0,PSPLIM" : "=r" (res));
|
||||||
|
#endif
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __set_PSPLIM(uint32_t value)
|
||||||
|
{
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||||
|
(void)value;
|
||||||
|
#else
|
||||||
|
__asm volatile("MSR PSPLIM,%0" :: "r" (value));
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
|
||||||
|
{
|
||||||
|
__asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __TZ_get_PSP_NS(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__asm volatile("MRS %0,PSP_NS" : "=r" (res));
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __TZ_set_PSP_NS(uint32_t value)
|
||||||
|
{
|
||||||
|
__asm volatile("MSR PSP_NS,%0" :: "r" (value));
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __TZ_get_MSP_NS(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__asm volatile("MRS %0,MSP_NS" : "=r" (res));
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __TZ_set_MSP_NS(uint32_t value)
|
||||||
|
{
|
||||||
|
__asm volatile("MSR MSP_NS,%0" :: "r" (value));
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __TZ_get_SP_NS(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__asm volatile("MRS %0,SP_NS" : "=r" (res));
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
__IAR_FT void __TZ_set_SP_NS(uint32_t value)
|
||||||
|
{
|
||||||
|
__asm volatile("MSR SP_NS,%0" :: "r" (value));
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
|
||||||
|
{
|
||||||
|
__asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
|
||||||
|
{
|
||||||
|
__asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
|
||||||
|
{
|
||||||
|
__asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||||
|
res = 0U;
|
||||||
|
#else
|
||||||
|
__asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
|
||||||
|
#endif
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
|
||||||
|
{
|
||||||
|
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||||
|
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||||
|
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||||
|
(void)value;
|
||||||
|
#else
|
||||||
|
__asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
|
||||||
|
{
|
||||||
|
__asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
|
||||||
|
|
||||||
|
#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
|
||||||
|
|
||||||
|
#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
|
||||||
|
|
||||||
|
#if __IAR_M0_FAMILY
|
||||||
|
__STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
|
||||||
|
{
|
||||||
|
if ((sat >= 1U) && (sat <= 32U))
|
||||||
|
{
|
||||||
|
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
|
||||||
|
const int32_t min = -1 - max ;
|
||||||
|
if (val > max)
|
||||||
|
{
|
||||||
|
return max;
|
||||||
|
}
|
||||||
|
else if (val < min)
|
||||||
|
{
|
||||||
|
return min;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return val;
|
||||||
|
}
|
||||||
|
|
||||||
|
__STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
|
||||||
|
{
|
||||||
|
if (sat <= 31U)
|
||||||
|
{
|
||||||
|
const uint32_t max = ((1U << sat) - 1U);
|
||||||
|
if (val > (int32_t)max)
|
||||||
|
{
|
||||||
|
return max;
|
||||||
|
}
|
||||||
|
else if (val < 0)
|
||||||
|
{
|
||||||
|
return 0U;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return (uint32_t)val;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
|
||||||
|
|
||||||
|
__IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
|
||||||
|
return ((uint8_t)res);
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
|
||||||
|
return ((uint16_t)res);
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
|
||||||
|
{
|
||||||
|
__ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
|
||||||
|
{
|
||||||
|
__ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
|
||||||
|
{
|
||||||
|
__ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* (__CORTEX_M >= 0x03) */
|
||||||
|
|
||||||
|
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
|
||||||
|
|
||||||
|
|
||||||
|
__IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||||
|
return ((uint8_t)res);
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||||
|
return ((uint16_t)res);
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
|
||||||
|
{
|
||||||
|
__ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
|
||||||
|
{
|
||||||
|
__ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
|
||||||
|
{
|
||||||
|
__ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||||
|
return ((uint8_t)res);
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||||
|
return ((uint16_t)res);
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
__IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
|
||||||
|
{
|
||||||
|
uint32_t res;
|
||||||
|
__ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
|
||||||
|
return res;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
|
||||||
|
|
||||||
|
#undef __IAR_FT
|
||||||
|
#undef __IAR_M0_FAMILY
|
||||||
|
#undef __ICCARM_V8
|
||||||
|
|
||||||
|
#pragma diag_default=Pe940
|
||||||
|
#pragma diag_default=Pe177
|
||||||
|
|
||||||
|
#endif /* __CMSIS_ICCARM_H__ */
|
|
@ -0,0 +1,39 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file cmsis_version.h
|
||||||
|
* @brief CMSIS Core(M) Version definitions
|
||||||
|
* @version V5.0.2
|
||||||
|
* @date 19. April 2017
|
||||||
|
******************************************************************************/
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined ( __ICCARM__ )
|
||||||
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
|
#elif defined (__clang__)
|
||||||
|
#pragma clang system_header /* treat file as system include file */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __CMSIS_VERSION_H
|
||||||
|
#define __CMSIS_VERSION_H
|
||||||
|
|
||||||
|
/* CMSIS Version definitions */
|
||||||
|
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
|
||||||
|
#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
|
||||||
|
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
|
||||||
|
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
|
||||||
|
#endif
|
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
@ -1,40 +1,30 @@
|
||||||
/**************************************************************************//**
|
/**************************************************************************//**
|
||||||
* @file core_cm0.h
|
* @file core_cm0.h
|
||||||
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
|
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
|
||||||
* @version V4.30
|
* @version V5.0.5
|
||||||
* @date 20. October 2015
|
* @date 28. May 2018
|
||||||
******************************************************************************/
|
******************************************************************************/
|
||||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
/*
|
||||||
|
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||||
All rights reserved.
|
*
|
||||||
Redistribution and use in source and binary forms, with or without
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
modification, are permitted provided that the following conditions are met:
|
*
|
||||||
- Redistributions of source code must retain the above copyright
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
notice, this list of conditions and the following disclaimer.
|
* not use this file except in compliance with the License.
|
||||||
- Redistributions in binary form must reproduce the above copyright
|
* You may obtain a copy of the License at
|
||||||
notice, this list of conditions and the following disclaimer in the
|
*
|
||||||
documentation and/or other materials provided with the distribution.
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
- Neither the name of ARM nor the names of its contributors may be used
|
*
|
||||||
to endorse or promote products derived from this software without
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
specific prior written permission.
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
*
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
* See the License for the specific language governing permissions and
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
* limitations under the License.
|
||||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
*/
|
||||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
|
||||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
|
||||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
||||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
|
||||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
|
||||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
||||||
POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
---------------------------------------------------------------------------*/
|
|
||||||
|
|
||||||
|
|
||||||
#if defined ( __ICCARM__ )
|
#if defined ( __ICCARM__ )
|
||||||
#pragma system_include /* treat file as system include file for MISRA check */
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
#elif defined (__clang__)
|
||||||
#pragma clang system_header /* treat file as system include file */
|
#pragma clang system_header /* treat file as system include file */
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
@ -70,53 +60,15 @@
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
#include "cmsis_version.h"
|
||||||
|
|
||||||
/* CMSIS CM0 definitions */
|
/* CMSIS CM0 definitions */
|
||||||
#define __CM0_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
|
#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
|
||||||
#define __CM0_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
|
#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
|
||||||
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
|
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
|
||||||
__CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
|
__CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
|
||||||
|
|
||||||
#define __CORTEX_M (0x00U) /*!< Cortex-M Core */
|
#define __CORTEX_M (0U) /*!< Cortex-M Core */
|
||||||
|
|
||||||
|
|
||||||
#if defined ( __CC_ARM )
|
|
||||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
|
||||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
|
||||||
#define __STATIC_INLINE static __inline
|
|
||||||
|
|
||||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
|
||||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
|
||||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
|
||||||
#define __STATIC_INLINE static __inline
|
|
||||||
|
|
||||||
#elif defined ( __GNUC__ )
|
|
||||||
#define __ASM __asm /*!< asm keyword for GNU Compiler */
|
|
||||||
#define __INLINE inline /*!< inline keyword for GNU Compiler */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#elif defined ( __ICCARM__ )
|
|
||||||
#define __ASM __asm /*!< asm keyword for IAR Compiler */
|
|
||||||
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#elif defined ( __TMS470__ )
|
|
||||||
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#elif defined ( __TASKING__ )
|
|
||||||
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
|
|
||||||
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#elif defined ( __CSMC__ )
|
|
||||||
#define __packed
|
|
||||||
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
|
|
||||||
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#else
|
|
||||||
#error Unknown compiler
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/** __FPU_USED indicates whether an FPU is used or not.
|
/** __FPU_USED indicates whether an FPU is used or not.
|
||||||
This core does not support an FPU at all
|
This core does not support an FPU at all
|
||||||
|
@ -128,7 +80,7 @@
|
||||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||||
#if defined __ARM_PCS_VFP
|
#if defined __ARM_PCS_VFP
|
||||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
#endif
|
#endif
|
||||||
|
@ -143,7 +95,7 @@
|
||||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#elif defined ( __TMS470__ )
|
#elif defined ( __TI_ARM__ )
|
||||||
#if defined __TI_VFP_SUPPORT__
|
#if defined __TI_VFP_SUPPORT__
|
||||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
#endif
|
#endif
|
||||||
|
@ -160,8 +112,8 @@
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#include "core_cmInstr.h" /* Core Instruction Access */
|
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
|
||||||
#include "core_cmFunc.h" /* Core Function Access */
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
}
|
}
|
||||||
|
@ -555,18 +507,18 @@ typedef struct
|
||||||
/**
|
/**
|
||||||
\brief Mask and shift a bit field value for use in a register bit range.
|
\brief Mask and shift a bit field value for use in a register bit range.
|
||||||
\param[in] field Name of the register bit field.
|
\param[in] field Name of the register bit field.
|
||||||
\param[in] value Value of the bit field.
|
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
|
||||||
\return Masked and shifted value.
|
\return Masked and shifted value.
|
||||||
*/
|
*/
|
||||||
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
|
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Mask and shift a register value to extract a bit filed value.
|
\brief Mask and shift a register value to extract a bit filed value.
|
||||||
\param[in] field Name of the register bit field.
|
\param[in] field Name of the register bit field.
|
||||||
\param[in] value Value of register.
|
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
|
||||||
\return Masked and shifted bit field value.
|
\return Masked and shifted bit field value.
|
||||||
*/
|
*/
|
||||||
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
|
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
|
||||||
|
|
||||||
/*@} end of group CMSIS_core_bitfield */
|
/*@} end of group CMSIS_core_bitfield */
|
||||||
|
|
||||||
|
@ -578,7 +530,7 @@ typedef struct
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Memory mapping of Cortex-M0 Hardware */
|
/* Memory mapping of Core Hardware */
|
||||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||||
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||||||
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||||||
|
@ -614,87 +566,177 @@ typedef struct
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Interrupt Priorities are WORD accessible only under ARMv6M */
|
#ifdef CMSIS_NVIC_VIRTUAL
|
||||||
|
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||||
|
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
||||||
|
#endif
|
||||||
|
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||||
|
#else
|
||||||
|
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
|
||||||
|
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
|
||||||
|
#define NVIC_EnableIRQ __NVIC_EnableIRQ
|
||||||
|
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
||||||
|
#define NVIC_DisableIRQ __NVIC_DisableIRQ
|
||||||
|
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
||||||
|
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
||||||
|
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
||||||
|
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
|
||||||
|
#define NVIC_SetPriority __NVIC_SetPriority
|
||||||
|
#define NVIC_GetPriority __NVIC_GetPriority
|
||||||
|
#define NVIC_SystemReset __NVIC_SystemReset
|
||||||
|
#endif /* CMSIS_NVIC_VIRTUAL */
|
||||||
|
|
||||||
|
#ifdef CMSIS_VECTAB_VIRTUAL
|
||||||
|
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||||
|
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
||||||
|
#endif
|
||||||
|
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||||
|
#else
|
||||||
|
#define NVIC_SetVector __NVIC_SetVector
|
||||||
|
#define NVIC_GetVector __NVIC_GetVector
|
||||||
|
#endif /* (CMSIS_VECTAB_VIRTUAL) */
|
||||||
|
|
||||||
|
#define NVIC_USER_IRQ_OFFSET 16
|
||||||
|
|
||||||
|
|
||||||
|
/* The following EXC_RETURN values are saved the LR on exception entry */
|
||||||
|
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
|
||||||
|
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
|
||||||
|
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
|
||||||
|
|
||||||
|
|
||||||
|
/* Interrupt Priorities are WORD accessible only under Armv6-M */
|
||||||
/* The following MACROS handle generation of the register offset and byte masks */
|
/* The following MACROS handle generation of the register offset and byte masks */
|
||||||
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
|
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
|
||||||
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
|
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
|
||||||
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
|
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
|
||||||
|
|
||||||
|
#define __NVIC_SetPriorityGrouping(X) (void)(X)
|
||||||
|
#define __NVIC_GetPriorityGrouping() (0U)
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Enable External Interrupt
|
\brief Enable Interrupt
|
||||||
\details Enables a device-specific interrupt in the NVIC interrupt controller.
|
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
||||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Disable External Interrupt
|
\brief Get Interrupt Enable status
|
||||||
\details Disables a device-specific interrupt in the NVIC interrupt controller.
|
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
|
||||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\return 0 Interrupt is not enabled.
|
||||||
|
\return 1 Interrupt is enabled.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return(0U);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Disable Interrupt
|
||||||
|
\details Disables a device specific interrupt in the NVIC interrupt controller.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Get Pending Interrupt
|
\brief Get Pending Interrupt
|
||||||
\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
|
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
|
||||||
\param [in] IRQn Interrupt number.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
\return 0 Interrupt status is not pending.
|
\return 0 Interrupt status is not pending.
|
||||||
\return 1 Interrupt status is pending.
|
\return 1 Interrupt status is pending.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return(0U);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Set Pending Interrupt
|
\brief Set Pending Interrupt
|
||||||
\details Sets the pending bit of an external interrupt.
|
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
|
||||||
\param [in] IRQn Interrupt number. Value cannot be negative.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Clear Pending Interrupt
|
\brief Clear Pending Interrupt
|
||||||
\details Clears the pending bit of an external interrupt.
|
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
|
||||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Set Interrupt Priority
|
\brief Set Interrupt Priority
|
||||||
\details Sets the priority of an interrupt.
|
\details Sets the priority of a device specific interrupt or a processor exception.
|
||||||
\note The priority cannot be set for every core interrupt.
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
\param [in] IRQn Interrupt number.
|
\param [in] IRQn Interrupt number.
|
||||||
\param [in] priority Priority to set.
|
\param [in] priority Priority to set.
|
||||||
|
\note The priority cannot be set for every processor exception.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||||
{
|
{
|
||||||
if ((int32_t)(IRQn) < 0)
|
if ((int32_t)(IRQn) >= 0)
|
||||||
{
|
{
|
||||||
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -702,24 +744,108 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Get Interrupt Priority
|
\brief Get Interrupt Priority
|
||||||
\details Reads the priority of an interrupt.
|
\details Reads the priority of a device specific interrupt or a processor exception.
|
||||||
The interrupt number can be positive to specify an external (device specific) interrupt,
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
or negative to specify an internal (core) interrupt.
|
or negative to specify a processor exception.
|
||||||
\param [in] IRQn Interrupt number.
|
\param [in] IRQn Interrupt number.
|
||||||
\return Interrupt Priority.
|
\return Interrupt Priority.
|
||||||
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
|
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
|
|
||||||
if ((int32_t)(IRQn) < 0)
|
if ((int32_t)(IRQn) >= 0)
|
||||||
{
|
|
||||||
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
{
|
||||||
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||||
}
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Encode Priority
|
||||||
|
\details Encodes the priority for an interrupt with the given priority group,
|
||||||
|
preemptive priority value, and subpriority value.
|
||||||
|
In case of a conflict between priority grouping and available
|
||||||
|
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
||||||
|
\param [in] PriorityGroup Used priority group.
|
||||||
|
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
||||||
|
\param [in] SubPriority Subpriority value (starting from 0).
|
||||||
|
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
||||||
|
{
|
||||||
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||||
|
uint32_t PreemptPriorityBits;
|
||||||
|
uint32_t SubPriorityBits;
|
||||||
|
|
||||||
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||||||
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||||
|
|
||||||
|
return (
|
||||||
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
||||||
|
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
||||||
|
);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Decode Priority
|
||||||
|
\details Decodes an interrupt priority value with a given priority group to
|
||||||
|
preemptive priority value and subpriority value.
|
||||||
|
In case of a conflict between priority grouping and available
|
||||||
|
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
|
||||||
|
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
|
||||||
|
\param [in] PriorityGroup Used priority group.
|
||||||
|
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
|
||||||
|
\param [out] pSubPriority Subpriority value (starting from 0).
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
|
||||||
|
{
|
||||||
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||||
|
uint32_t PreemptPriorityBits;
|
||||||
|
uint32_t SubPriorityBits;
|
||||||
|
|
||||||
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||||||
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||||
|
|
||||||
|
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
|
||||||
|
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Interrupt Vector
|
||||||
|
\details Sets an interrupt vector in SRAM based interrupt vector table.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
Address 0 must be mapped to SRAM.
|
||||||
|
\param [in] IRQn Interrupt number
|
||||||
|
\param [in] vector Address of interrupt handler function
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
||||||
|
{
|
||||||
|
uint32_t *vectors = (uint32_t *)0x0U;
|
||||||
|
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Interrupt Vector
|
||||||
|
\details Reads an interrupt vector from interrupt vector table.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
\param [in] IRQn Interrupt number.
|
||||||
|
\return Address of interrupt handler function
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
uint32_t *vectors = (uint32_t *)0x0U;
|
||||||
|
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
@ -727,7 +853,7 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
|
||||||
\brief System Reset
|
\brief System Reset
|
||||||
\details Initiates a system reset request to reset the MCU.
|
\details Initiates a system reset request to reset the MCU.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_SystemReset(void)
|
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
|
||||||
{
|
{
|
||||||
__DSB(); /* Ensure all outstanding memory accesses included
|
__DSB(); /* Ensure all outstanding memory accesses included
|
||||||
buffered write are completed before reset */
|
buffered write are completed before reset */
|
||||||
|
@ -744,6 +870,31 @@ __STATIC_INLINE void NVIC_SystemReset(void)
|
||||||
/*@} end of CMSIS_Core_NVICFunctions */
|
/*@} end of CMSIS_Core_NVICFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
/* ########################## FPU functions #################################### */
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_Core_FunctionInterface
|
||||||
|
\defgroup CMSIS_Core_FpuFunctions FPU Functions
|
||||||
|
\brief Function that provides FPU type.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief get FPU type
|
||||||
|
\details returns the FPU type
|
||||||
|
\returns
|
||||||
|
- \b 0: No FPU
|
||||||
|
- \b 1: Single precision FPU
|
||||||
|
- \b 2: Double + Single precision FPU
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
|
||||||
|
{
|
||||||
|
return 0U; /* No FPU */
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*@} end of CMSIS_Core_FpuFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/* ################################## SysTick function ############################################ */
|
/* ################################## SysTick function ############################################ */
|
||||||
/**
|
/**
|
||||||
|
@ -753,7 +904,7 @@ __STATIC_INLINE void NVIC_SystemReset(void)
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#if (__Vendor_SysTickConfig == 0U)
|
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief System Tick Configuration
|
\brief System Tick Configuration
|
||||||
|
|
|
@ -1,40 +1,30 @@
|
||||||
/**************************************************************************//**
|
/**************************************************************************//**
|
||||||
* @file core_cm0plus.h
|
* @file core_cm0plus.h
|
||||||
* @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
|
* @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
|
||||||
* @version V4.30
|
* @version V5.0.6
|
||||||
* @date 20. October 2015
|
* @date 28. May 2018
|
||||||
******************************************************************************/
|
******************************************************************************/
|
||||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
/*
|
||||||
|
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||||
All rights reserved.
|
*
|
||||||
Redistribution and use in source and binary forms, with or without
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
modification, are permitted provided that the following conditions are met:
|
*
|
||||||
- Redistributions of source code must retain the above copyright
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
notice, this list of conditions and the following disclaimer.
|
* not use this file except in compliance with the License.
|
||||||
- Redistributions in binary form must reproduce the above copyright
|
* You may obtain a copy of the License at
|
||||||
notice, this list of conditions and the following disclaimer in the
|
*
|
||||||
documentation and/or other materials provided with the distribution.
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
- Neither the name of ARM nor the names of its contributors may be used
|
*
|
||||||
to endorse or promote products derived from this software without
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
specific prior written permission.
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
*
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
* See the License for the specific language governing permissions and
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
* limitations under the License.
|
||||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
*/
|
||||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
|
||||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
|
||||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
||||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
|
||||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
|
||||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
||||||
POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
---------------------------------------------------------------------------*/
|
|
||||||
|
|
||||||
|
|
||||||
#if defined ( __ICCARM__ )
|
#if defined ( __ICCARM__ )
|
||||||
#pragma system_include /* treat file as system include file for MISRA check */
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
#elif defined (__clang__)
|
||||||
#pragma clang system_header /* treat file as system include file */
|
#pragma clang system_header /* treat file as system include file */
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
@ -70,53 +60,15 @@
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
#include "cmsis_version.h"
|
||||||
|
|
||||||
/* CMSIS CM0+ definitions */
|
/* CMSIS CM0+ definitions */
|
||||||
#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
|
#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
|
||||||
#define __CM0PLUS_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
|
#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
|
||||||
#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
|
#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
|
||||||
__CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
|
__CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
|
||||||
|
|
||||||
#define __CORTEX_M (0x00U) /*!< Cortex-M Core */
|
#define __CORTEX_M (0U) /*!< Cortex-M Core */
|
||||||
|
|
||||||
|
|
||||||
#if defined ( __CC_ARM )
|
|
||||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
|
||||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
|
||||||
#define __STATIC_INLINE static __inline
|
|
||||||
|
|
||||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
|
||||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
|
||||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
|
||||||
#define __STATIC_INLINE static __inline
|
|
||||||
|
|
||||||
#elif defined ( __GNUC__ )
|
|
||||||
#define __ASM __asm /*!< asm keyword for GNU Compiler */
|
|
||||||
#define __INLINE inline /*!< inline keyword for GNU Compiler */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#elif defined ( __ICCARM__ )
|
|
||||||
#define __ASM __asm /*!< asm keyword for IAR Compiler */
|
|
||||||
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#elif defined ( __TMS470__ )
|
|
||||||
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#elif defined ( __TASKING__ )
|
|
||||||
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
|
|
||||||
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#elif defined ( __CSMC__ )
|
|
||||||
#define __packed
|
|
||||||
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
|
|
||||||
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#else
|
|
||||||
#error Unknown compiler
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/** __FPU_USED indicates whether an FPU is used or not.
|
/** __FPU_USED indicates whether an FPU is used or not.
|
||||||
This core does not support an FPU at all
|
This core does not support an FPU at all
|
||||||
|
@ -128,7 +80,7 @@
|
||||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||||
#if defined __ARM_PCS_VFP
|
#if defined __ARM_PCS_VFP
|
||||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
#endif
|
#endif
|
||||||
|
@ -143,7 +95,7 @@
|
||||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#elif defined ( __TMS470__ )
|
#elif defined ( __TI_ARM__ )
|
||||||
#if defined __TI_VFP_SUPPORT__
|
#if defined __TI_VFP_SUPPORT__
|
||||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
#endif
|
#endif
|
||||||
|
@ -160,8 +112,8 @@
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#include "core_cmInstr.h" /* Core Instruction Access */
|
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
|
||||||
#include "core_cmFunc.h" /* Core Function Access */
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
}
|
}
|
||||||
|
@ -404,7 +356,7 @@ typedef struct
|
||||||
{
|
{
|
||||||
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
|
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
|
||||||
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
|
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
|
||||||
#if (__VTOR_PRESENT == 1U)
|
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
|
||||||
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
|
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
|
||||||
#else
|
#else
|
||||||
uint32_t RESERVED0;
|
uint32_t RESERVED0;
|
||||||
|
@ -461,7 +413,7 @@ typedef struct
|
||||||
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
|
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
|
||||||
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
|
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
|
||||||
|
|
||||||
#if (__VTOR_PRESENT == 1U)
|
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
|
||||||
/* SCB Interrupt Control State Register Definitions */
|
/* SCB Interrupt Control State Register Definitions */
|
||||||
#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
|
#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
|
||||||
#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
|
#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
|
||||||
|
@ -558,7 +510,7 @@ typedef struct
|
||||||
|
|
||||||
/*@} end of group CMSIS_SysTick */
|
/*@} end of group CMSIS_SysTick */
|
||||||
|
|
||||||
#if (__MPU_PRESENT == 1U)
|
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
|
||||||
/**
|
/**
|
||||||
\ingroup CMSIS_core_register
|
\ingroup CMSIS_core_register
|
||||||
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
|
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
|
||||||
|
@ -578,6 +530,8 @@ typedef struct
|
||||||
__IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
|
__IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
|
||||||
} MPU_Type;
|
} MPU_Type;
|
||||||
|
|
||||||
|
#define MPU_TYPE_RALIASES 1U
|
||||||
|
|
||||||
/* MPU Type Register Definitions */
|
/* MPU Type Register Definitions */
|
||||||
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
|
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
|
||||||
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
|
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
|
||||||
|
@ -667,18 +621,18 @@ typedef struct
|
||||||
/**
|
/**
|
||||||
\brief Mask and shift a bit field value for use in a register bit range.
|
\brief Mask and shift a bit field value for use in a register bit range.
|
||||||
\param[in] field Name of the register bit field.
|
\param[in] field Name of the register bit field.
|
||||||
\param[in] value Value of the bit field.
|
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
|
||||||
\return Masked and shifted value.
|
\return Masked and shifted value.
|
||||||
*/
|
*/
|
||||||
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
|
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Mask and shift a register value to extract a bit filed value.
|
\brief Mask and shift a register value to extract a bit filed value.
|
||||||
\param[in] field Name of the register bit field.
|
\param[in] field Name of the register bit field.
|
||||||
\param[in] value Value of register.
|
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
|
||||||
\return Masked and shifted bit field value.
|
\return Masked and shifted bit field value.
|
||||||
*/
|
*/
|
||||||
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
|
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
|
||||||
|
|
||||||
/*@} end of group CMSIS_core_bitfield */
|
/*@} end of group CMSIS_core_bitfield */
|
||||||
|
|
||||||
|
@ -690,7 +644,7 @@ typedef struct
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Memory mapping of Cortex-M0+ Hardware */
|
/* Memory mapping of Core Hardware */
|
||||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||||
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||||||
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||||||
|
@ -700,7 +654,7 @@ typedef struct
|
||||||
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
||||||
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
||||||
|
|
||||||
#if (__MPU_PRESENT == 1U)
|
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
|
||||||
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
|
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
|
||||||
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
|
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
|
||||||
#endif
|
#endif
|
||||||
|
@ -730,87 +684,177 @@ typedef struct
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Interrupt Priorities are WORD accessible only under ARMv6M */
|
#ifdef CMSIS_NVIC_VIRTUAL
|
||||||
|
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||||
|
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
||||||
|
#endif
|
||||||
|
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||||
|
#else
|
||||||
|
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
|
||||||
|
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
|
||||||
|
#define NVIC_EnableIRQ __NVIC_EnableIRQ
|
||||||
|
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
||||||
|
#define NVIC_DisableIRQ __NVIC_DisableIRQ
|
||||||
|
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
||||||
|
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
||||||
|
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
||||||
|
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */
|
||||||
|
#define NVIC_SetPriority __NVIC_SetPriority
|
||||||
|
#define NVIC_GetPriority __NVIC_GetPriority
|
||||||
|
#define NVIC_SystemReset __NVIC_SystemReset
|
||||||
|
#endif /* CMSIS_NVIC_VIRTUAL */
|
||||||
|
|
||||||
|
#ifdef CMSIS_VECTAB_VIRTUAL
|
||||||
|
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||||
|
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
||||||
|
#endif
|
||||||
|
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||||
|
#else
|
||||||
|
#define NVIC_SetVector __NVIC_SetVector
|
||||||
|
#define NVIC_GetVector __NVIC_GetVector
|
||||||
|
#endif /* (CMSIS_VECTAB_VIRTUAL) */
|
||||||
|
|
||||||
|
#define NVIC_USER_IRQ_OFFSET 16
|
||||||
|
|
||||||
|
|
||||||
|
/* The following EXC_RETURN values are saved the LR on exception entry */
|
||||||
|
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
|
||||||
|
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
|
||||||
|
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
|
||||||
|
|
||||||
|
|
||||||
|
/* Interrupt Priorities are WORD accessible only under Armv6-M */
|
||||||
/* The following MACROS handle generation of the register offset and byte masks */
|
/* The following MACROS handle generation of the register offset and byte masks */
|
||||||
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
|
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
|
||||||
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
|
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
|
||||||
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
|
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
|
||||||
|
|
||||||
|
#define __NVIC_SetPriorityGrouping(X) (void)(X)
|
||||||
|
#define __NVIC_GetPriorityGrouping() (0U)
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Enable External Interrupt
|
\brief Enable Interrupt
|
||||||
\details Enables a device-specific interrupt in the NVIC interrupt controller.
|
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
||||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Disable External Interrupt
|
\brief Get Interrupt Enable status
|
||||||
\details Disables a device-specific interrupt in the NVIC interrupt controller.
|
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
|
||||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\return 0 Interrupt is not enabled.
|
||||||
|
\return 1 Interrupt is enabled.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return(0U);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Disable Interrupt
|
||||||
|
\details Disables a device specific interrupt in the NVIC interrupt controller.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Get Pending Interrupt
|
\brief Get Pending Interrupt
|
||||||
\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
|
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
|
||||||
\param [in] IRQn Interrupt number.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
\return 0 Interrupt status is not pending.
|
\return 0 Interrupt status is not pending.
|
||||||
\return 1 Interrupt status is pending.
|
\return 1 Interrupt status is pending.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return(0U);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Set Pending Interrupt
|
\brief Set Pending Interrupt
|
||||||
\details Sets the pending bit of an external interrupt.
|
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
|
||||||
\param [in] IRQn Interrupt number. Value cannot be negative.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Clear Pending Interrupt
|
\brief Clear Pending Interrupt
|
||||||
\details Clears the pending bit of an external interrupt.
|
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
|
||||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Set Interrupt Priority
|
\brief Set Interrupt Priority
|
||||||
\details Sets the priority of an interrupt.
|
\details Sets the priority of a device specific interrupt or a processor exception.
|
||||||
\note The priority cannot be set for every core interrupt.
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
\param [in] IRQn Interrupt number.
|
\param [in] IRQn Interrupt number.
|
||||||
\param [in] priority Priority to set.
|
\param [in] priority Priority to set.
|
||||||
|
\note The priority cannot be set for every processor exception.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||||
{
|
{
|
||||||
if ((int32_t)(IRQn) < 0)
|
if ((int32_t)(IRQn) >= 0)
|
||||||
{
|
{
|
||||||
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -818,24 +862,117 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Get Interrupt Priority
|
\brief Get Interrupt Priority
|
||||||
\details Reads the priority of an interrupt.
|
\details Reads the priority of a device specific interrupt or a processor exception.
|
||||||
The interrupt number can be positive to specify an external (device specific) interrupt,
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
or negative to specify an internal (core) interrupt.
|
or negative to specify a processor exception.
|
||||||
\param [in] IRQn Interrupt number.
|
\param [in] IRQn Interrupt number.
|
||||||
\return Interrupt Priority.
|
\return Interrupt Priority.
|
||||||
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
|
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
|
|
||||||
if ((int32_t)(IRQn) < 0)
|
if ((int32_t)(IRQn) >= 0)
|
||||||
{
|
|
||||||
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
{
|
||||||
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||||
}
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Encode Priority
|
||||||
|
\details Encodes the priority for an interrupt with the given priority group,
|
||||||
|
preemptive priority value, and subpriority value.
|
||||||
|
In case of a conflict between priority grouping and available
|
||||||
|
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
||||||
|
\param [in] PriorityGroup Used priority group.
|
||||||
|
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
||||||
|
\param [in] SubPriority Subpriority value (starting from 0).
|
||||||
|
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
||||||
|
{
|
||||||
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||||
|
uint32_t PreemptPriorityBits;
|
||||||
|
uint32_t SubPriorityBits;
|
||||||
|
|
||||||
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||||||
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||||
|
|
||||||
|
return (
|
||||||
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
||||||
|
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
||||||
|
);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Decode Priority
|
||||||
|
\details Decodes an interrupt priority value with a given priority group to
|
||||||
|
preemptive priority value and subpriority value.
|
||||||
|
In case of a conflict between priority grouping and available
|
||||||
|
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
|
||||||
|
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
|
||||||
|
\param [in] PriorityGroup Used priority group.
|
||||||
|
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
|
||||||
|
\param [out] pSubPriority Subpriority value (starting from 0).
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
|
||||||
|
{
|
||||||
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||||
|
uint32_t PreemptPriorityBits;
|
||||||
|
uint32_t SubPriorityBits;
|
||||||
|
|
||||||
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||||||
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||||
|
|
||||||
|
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
|
||||||
|
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Interrupt Vector
|
||||||
|
\details Sets an interrupt vector in SRAM based interrupt vector table.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
VTOR must been relocated to SRAM before.
|
||||||
|
If VTOR is not present address 0 must be mapped to SRAM.
|
||||||
|
\param [in] IRQn Interrupt number
|
||||||
|
\param [in] vector Address of interrupt handler function
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
||||||
|
{
|
||||||
|
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
|
||||||
|
uint32_t *vectors = (uint32_t *)SCB->VTOR;
|
||||||
|
#else
|
||||||
|
uint32_t *vectors = (uint32_t *)0x0U;
|
||||||
|
#endif
|
||||||
|
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Interrupt Vector
|
||||||
|
\details Reads an interrupt vector from interrupt vector table.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
\param [in] IRQn Interrupt number.
|
||||||
|
\return Address of interrupt handler function
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
|
||||||
|
uint32_t *vectors = (uint32_t *)SCB->VTOR;
|
||||||
|
#else
|
||||||
|
uint32_t *vectors = (uint32_t *)0x0U;
|
||||||
|
#endif
|
||||||
|
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
@ -843,7 +980,7 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
|
||||||
\brief System Reset
|
\brief System Reset
|
||||||
\details Initiates a system reset request to reset the MCU.
|
\details Initiates a system reset request to reset the MCU.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_SystemReset(void)
|
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
|
||||||
{
|
{
|
||||||
__DSB(); /* Ensure all outstanding memory accesses included
|
__DSB(); /* Ensure all outstanding memory accesses included
|
||||||
buffered write are completed before reset */
|
buffered write are completed before reset */
|
||||||
|
@ -859,6 +996,38 @@ __STATIC_INLINE void NVIC_SystemReset(void)
|
||||||
|
|
||||||
/*@} end of CMSIS_Core_NVICFunctions */
|
/*@} end of CMSIS_Core_NVICFunctions */
|
||||||
|
|
||||||
|
/* ########################## MPU functions #################################### */
|
||||||
|
|
||||||
|
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
|
||||||
|
|
||||||
|
#include "mpu_armv7.h"
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* ########################## FPU functions #################################### */
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_Core_FunctionInterface
|
||||||
|
\defgroup CMSIS_Core_FpuFunctions FPU Functions
|
||||||
|
\brief Function that provides FPU type.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief get FPU type
|
||||||
|
\details returns the FPU type
|
||||||
|
\returns
|
||||||
|
- \b 0: No FPU
|
||||||
|
- \b 1: Single precision FPU
|
||||||
|
- \b 2: Double + Single precision FPU
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
|
||||||
|
{
|
||||||
|
return 0U; /* No FPU */
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*@} end of CMSIS_Core_FpuFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/* ################################## SysTick function ############################################ */
|
/* ################################## SysTick function ############################################ */
|
||||||
|
@ -869,7 +1038,7 @@ __STATIC_INLINE void NVIC_SystemReset(void)
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#if (__Vendor_SysTickConfig == 0U)
|
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief System Tick Configuration
|
\brief System Tick Configuration
|
||||||
|
|
|
@ -0,0 +1,976 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file core_cm1.h
|
||||||
|
* @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File
|
||||||
|
* @version V1.0.0
|
||||||
|
* @date 23. July 2018
|
||||||
|
******************************************************************************/
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined ( __ICCARM__ )
|
||||||
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
|
#elif defined (__clang__)
|
||||||
|
#pragma clang system_header /* treat file as system include file */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __CORE_CM1_H_GENERIC
|
||||||
|
#define __CORE_CM1_H_GENERIC
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
|
||||||
|
CMSIS violates the following MISRA-C:2004 rules:
|
||||||
|
|
||||||
|
\li Required Rule 8.5, object/function definition in header file.<br>
|
||||||
|
Function definitions in header files are used to allow 'inlining'.
|
||||||
|
|
||||||
|
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
|
||||||
|
Unions are used for effective representation of core registers.
|
||||||
|
|
||||||
|
\li Advisory Rule 19.7, Function-like macro defined.<br>
|
||||||
|
Function-like macros are used to allow more efficient code.
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* CMSIS definitions
|
||||||
|
******************************************************************************/
|
||||||
|
/**
|
||||||
|
\ingroup Cortex_M1
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "cmsis_version.h"
|
||||||
|
|
||||||
|
/* CMSIS CM1 definitions */
|
||||||
|
#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
|
||||||
|
#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
|
||||||
|
#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
|
||||||
|
__CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
|
||||||
|
|
||||||
|
#define __CORTEX_M (1U) /*!< Cortex-M Core */
|
||||||
|
|
||||||
|
/** __FPU_USED indicates whether an FPU is used or not.
|
||||||
|
This core does not support an FPU at all
|
||||||
|
*/
|
||||||
|
#define __FPU_USED 0U
|
||||||
|
|
||||||
|
#if defined ( __CC_ARM )
|
||||||
|
#if defined __TARGET_FPU_VFP
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||||
|
#if defined __ARM_PCS_VFP
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined ( __GNUC__ )
|
||||||
|
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined ( __ICCARM__ )
|
||||||
|
#if defined __ARMVFP__
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined ( __TI_ARM__ )
|
||||||
|
#if defined __TI_VFP_SUPPORT__
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined ( __TASKING__ )
|
||||||
|
#if defined __FPU_VFP__
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#elif defined ( __CSMC__ )
|
||||||
|
#if ( __CSMC__ & 0x400U)
|
||||||
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __CORE_CM1_H_GENERIC */
|
||||||
|
|
||||||
|
#ifndef __CMSIS_GENERIC
|
||||||
|
|
||||||
|
#ifndef __CORE_CM1_H_DEPENDANT
|
||||||
|
#define __CORE_CM1_H_DEPENDANT
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* check device defines and use defaults */
|
||||||
|
#if defined __CHECK_DEVICE_DEFINES
|
||||||
|
#ifndef __CM1_REV
|
||||||
|
#define __CM1_REV 0x0100U
|
||||||
|
#warning "__CM1_REV not defined in device header file; using default!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __NVIC_PRIO_BITS
|
||||||
|
#define __NVIC_PRIO_BITS 2U
|
||||||
|
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __Vendor_SysTickConfig
|
||||||
|
#define __Vendor_SysTickConfig 0U
|
||||||
|
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* IO definitions (access restrictions to peripheral registers) */
|
||||||
|
/**
|
||||||
|
\defgroup CMSIS_glob_defs CMSIS Global Defines
|
||||||
|
|
||||||
|
<strong>IO Type Qualifiers</strong> are used
|
||||||
|
\li to specify the access to peripheral variables.
|
||||||
|
\li for automatic generation of peripheral register debug information.
|
||||||
|
*/
|
||||||
|
#ifdef __cplusplus
|
||||||
|
#define __I volatile /*!< Defines 'read only' permissions */
|
||||||
|
#else
|
||||||
|
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||||
|
#endif
|
||||||
|
#define __O volatile /*!< Defines 'write only' permissions */
|
||||||
|
#define __IO volatile /*!< Defines 'read / write' permissions */
|
||||||
|
|
||||||
|
/* following defines should be used for structure members */
|
||||||
|
#define __IM volatile const /*! Defines 'read only' structure member permissions */
|
||||||
|
#define __OM volatile /*! Defines 'write only' structure member permissions */
|
||||||
|
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
|
||||||
|
|
||||||
|
/*@} end of group Cortex_M1 */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Register Abstraction
|
||||||
|
Core Register contain:
|
||||||
|
- Core Register
|
||||||
|
- Core NVIC Register
|
||||||
|
- Core SCB Register
|
||||||
|
- Core SysTick Register
|
||||||
|
******************************************************************************/
|
||||||
|
/**
|
||||||
|
\defgroup CMSIS_core_register Defines and Type Definitions
|
||||||
|
\brief Type definitions and defines for Cortex-M processor based devices.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_CORE Status and Control Registers
|
||||||
|
\brief Core Register type definitions.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Union type to access the Application Program Status Register (APSR).
|
||||||
|
*/
|
||||||
|
typedef union
|
||||||
|
{
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
|
||||||
|
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||||
|
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||||
|
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||||
|
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||||
|
} b; /*!< Structure used for bit access */
|
||||||
|
uint32_t w; /*!< Type used for word access */
|
||||||
|
} APSR_Type;
|
||||||
|
|
||||||
|
/* APSR Register Definitions */
|
||||||
|
#define APSR_N_Pos 31U /*!< APSR: N Position */
|
||||||
|
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
|
||||||
|
|
||||||
|
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
|
||||||
|
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
|
||||||
|
|
||||||
|
#define APSR_C_Pos 29U /*!< APSR: C Position */
|
||||||
|
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
|
||||||
|
|
||||||
|
#define APSR_V_Pos 28U /*!< APSR: V Position */
|
||||||
|
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Union type to access the Interrupt Program Status Register (IPSR).
|
||||||
|
*/
|
||||||
|
typedef union
|
||||||
|
{
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||||
|
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
|
||||||
|
} b; /*!< Structure used for bit access */
|
||||||
|
uint32_t w; /*!< Type used for word access */
|
||||||
|
} IPSR_Type;
|
||||||
|
|
||||||
|
/* IPSR Register Definitions */
|
||||||
|
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
|
||||||
|
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
|
||||||
|
*/
|
||||||
|
typedef union
|
||||||
|
{
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||||
|
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
|
||||||
|
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
|
||||||
|
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
|
||||||
|
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||||
|
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||||
|
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||||
|
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||||
|
} b; /*!< Structure used for bit access */
|
||||||
|
uint32_t w; /*!< Type used for word access */
|
||||||
|
} xPSR_Type;
|
||||||
|
|
||||||
|
/* xPSR Register Definitions */
|
||||||
|
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
|
||||||
|
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
|
||||||
|
|
||||||
|
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
|
||||||
|
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
|
||||||
|
|
||||||
|
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
|
||||||
|
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
|
||||||
|
|
||||||
|
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
|
||||||
|
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
|
||||||
|
|
||||||
|
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
|
||||||
|
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
|
||||||
|
|
||||||
|
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
|
||||||
|
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Union type to access the Control Registers (CONTROL).
|
||||||
|
*/
|
||||||
|
typedef union
|
||||||
|
{
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
|
||||||
|
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
|
||||||
|
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
|
||||||
|
} b; /*!< Structure used for bit access */
|
||||||
|
uint32_t w; /*!< Type used for word access */
|
||||||
|
} CONTROL_Type;
|
||||||
|
|
||||||
|
/* CONTROL Register Definitions */
|
||||||
|
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
|
||||||
|
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_CORE */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
|
||||||
|
\brief Type definitions for the NVIC Registers
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
|
||||||
|
uint32_t RESERVED0[31U];
|
||||||
|
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
|
||||||
|
uint32_t RSERVED1[31U];
|
||||||
|
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
|
||||||
|
uint32_t RESERVED2[31U];
|
||||||
|
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
|
||||||
|
uint32_t RESERVED3[31U];
|
||||||
|
uint32_t RESERVED4[64U];
|
||||||
|
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
|
||||||
|
} NVIC_Type;
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_NVIC */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_SCB System Control Block (SCB)
|
||||||
|
\brief Type definitions for the System Control Block Registers
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Structure type to access the System Control Block (SCB).
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
|
||||||
|
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
|
||||||
|
uint32_t RESERVED0;
|
||||||
|
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
|
||||||
|
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
|
||||||
|
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
|
||||||
|
uint32_t RESERVED1;
|
||||||
|
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
|
||||||
|
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
|
||||||
|
} SCB_Type;
|
||||||
|
|
||||||
|
/* SCB CPUID Register Definitions */
|
||||||
|
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
|
||||||
|
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
|
||||||
|
|
||||||
|
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
|
||||||
|
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
|
||||||
|
|
||||||
|
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
|
||||||
|
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
|
||||||
|
|
||||||
|
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
|
||||||
|
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
|
||||||
|
|
||||||
|
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
|
||||||
|
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
|
||||||
|
|
||||||
|
/* SCB Interrupt Control State Register Definitions */
|
||||||
|
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
|
||||||
|
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
|
||||||
|
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
|
||||||
|
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
|
||||||
|
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
|
||||||
|
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
|
||||||
|
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
|
||||||
|
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
|
||||||
|
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
|
||||||
|
|
||||||
|
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
|
||||||
|
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
|
||||||
|
|
||||||
|
/* SCB Application Interrupt and Reset Control Register Definitions */
|
||||||
|
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
|
||||||
|
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
|
||||||
|
|
||||||
|
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
|
||||||
|
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
|
||||||
|
|
||||||
|
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
|
||||||
|
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
|
||||||
|
|
||||||
|
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
|
||||||
|
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
|
||||||
|
|
||||||
|
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
|
||||||
|
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
|
||||||
|
|
||||||
|
/* SCB System Control Register Definitions */
|
||||||
|
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
|
||||||
|
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
|
||||||
|
|
||||||
|
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
|
||||||
|
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
|
||||||
|
|
||||||
|
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
|
||||||
|
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
|
||||||
|
|
||||||
|
/* SCB Configuration Control Register Definitions */
|
||||||
|
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
|
||||||
|
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
|
||||||
|
|
||||||
|
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
|
||||||
|
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
|
||||||
|
|
||||||
|
/* SCB System Handler Control and State Register Definitions */
|
||||||
|
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
|
||||||
|
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_SCB */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
|
||||||
|
\brief Type definitions for the System Control and ID Register not in the SCB
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Structure type to access the System Control and ID Register not in the SCB.
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t RESERVED0[2U];
|
||||||
|
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
|
||||||
|
} SCnSCB_Type;
|
||||||
|
|
||||||
|
/* Auxiliary Control Register Definitions */
|
||||||
|
#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
|
||||||
|
#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
|
||||||
|
|
||||||
|
#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
|
||||||
|
#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_SCnotSCB */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
|
||||||
|
\brief Type definitions for the System Timer Registers.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Structure type to access the System Timer (SysTick).
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
|
||||||
|
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
|
||||||
|
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
|
||||||
|
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
||||||
|
} SysTick_Type;
|
||||||
|
|
||||||
|
/* SysTick Control / Status Register Definitions */
|
||||||
|
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
|
||||||
|
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
||||||
|
|
||||||
|
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
|
||||||
|
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
|
||||||
|
|
||||||
|
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
|
||||||
|
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
|
||||||
|
|
||||||
|
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
|
||||||
|
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
|
||||||
|
|
||||||
|
/* SysTick Reload Register Definitions */
|
||||||
|
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
|
||||||
|
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
|
||||||
|
|
||||||
|
/* SysTick Current Register Definitions */
|
||||||
|
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
|
||||||
|
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
|
||||||
|
|
||||||
|
/* SysTick Calibration Register Definitions */
|
||||||
|
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
|
||||||
|
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
||||||
|
|
||||||
|
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
|
||||||
|
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
|
||||||
|
|
||||||
|
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
|
||||||
|
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_SysTick */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
|
||||||
|
\brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
|
||||||
|
Therefore they are not covered by the Cortex-M1 header file.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
/*@} end of group CMSIS_CoreDebug */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_core_bitfield Core register bit field macros
|
||||||
|
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Mask and shift a bit field value for use in a register bit range.
|
||||||
|
\param[in] field Name of the register bit field.
|
||||||
|
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
|
||||||
|
\return Masked and shifted value.
|
||||||
|
*/
|
||||||
|
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Mask and shift a register value to extract a bit filed value.
|
||||||
|
\param[in] field Name of the register bit field.
|
||||||
|
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
|
||||||
|
\return Masked and shifted bit field value.
|
||||||
|
*/
|
||||||
|
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_core_bitfield */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_core_register
|
||||||
|
\defgroup CMSIS_core_base Core Definitions
|
||||||
|
\brief Definitions for base addresses, unions, and structures.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Memory mapping of Core Hardware */
|
||||||
|
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||||
|
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||||||
|
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||||||
|
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
||||||
|
|
||||||
|
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
|
||||||
|
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
||||||
|
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
||||||
|
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
||||||
|
|
||||||
|
|
||||||
|
/*@} */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Hardware Abstraction Layer
|
||||||
|
Core Function Interface contains:
|
||||||
|
- Core NVIC Functions
|
||||||
|
- Core SysTick Functions
|
||||||
|
- Core Register Access Functions
|
||||||
|
******************************************************************************/
|
||||||
|
/**
|
||||||
|
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* ########################## NVIC functions #################################### */
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_Core_FunctionInterface
|
||||||
|
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
|
||||||
|
\brief Functions that manage interrupts and exceptions via the NVIC.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef CMSIS_NVIC_VIRTUAL
|
||||||
|
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||||
|
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
||||||
|
#endif
|
||||||
|
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||||
|
#else
|
||||||
|
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
|
||||||
|
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
|
||||||
|
#define NVIC_EnableIRQ __NVIC_EnableIRQ
|
||||||
|
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
||||||
|
#define NVIC_DisableIRQ __NVIC_DisableIRQ
|
||||||
|
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
||||||
|
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
||||||
|
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
||||||
|
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */
|
||||||
|
#define NVIC_SetPriority __NVIC_SetPriority
|
||||||
|
#define NVIC_GetPriority __NVIC_GetPriority
|
||||||
|
#define NVIC_SystemReset __NVIC_SystemReset
|
||||||
|
#endif /* CMSIS_NVIC_VIRTUAL */
|
||||||
|
|
||||||
|
#ifdef CMSIS_VECTAB_VIRTUAL
|
||||||
|
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||||
|
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
||||||
|
#endif
|
||||||
|
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||||
|
#else
|
||||||
|
#define NVIC_SetVector __NVIC_SetVector
|
||||||
|
#define NVIC_GetVector __NVIC_GetVector
|
||||||
|
#endif /* (CMSIS_VECTAB_VIRTUAL) */
|
||||||
|
|
||||||
|
#define NVIC_USER_IRQ_OFFSET 16
|
||||||
|
|
||||||
|
|
||||||
|
/* The following EXC_RETURN values are saved the LR on exception entry */
|
||||||
|
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
|
||||||
|
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
|
||||||
|
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
|
||||||
|
|
||||||
|
|
||||||
|
/* Interrupt Priorities are WORD accessible only under Armv6-M */
|
||||||
|
/* The following MACROS handle generation of the register offset and byte masks */
|
||||||
|
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
|
||||||
|
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
|
||||||
|
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
|
||||||
|
|
||||||
|
#define __NVIC_SetPriorityGrouping(X) (void)(X)
|
||||||
|
#define __NVIC_GetPriorityGrouping() (0U)
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Enable Interrupt
|
||||||
|
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Interrupt Enable status
|
||||||
|
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\return 0 Interrupt is not enabled.
|
||||||
|
\return 1 Interrupt is enabled.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return(0U);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Disable Interrupt
|
||||||
|
\details Disables a device specific interrupt in the NVIC interrupt controller.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Pending Interrupt
|
||||||
|
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\return 0 Interrupt status is not pending.
|
||||||
|
\return 1 Interrupt status is pending.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return(0U);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Pending Interrupt
|
||||||
|
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Clear Pending Interrupt
|
||||||
|
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Interrupt Priority
|
||||||
|
\details Sets the priority of a device specific interrupt or a processor exception.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
\param [in] IRQn Interrupt number.
|
||||||
|
\param [in] priority Priority to set.
|
||||||
|
\note The priority cannot be set for every processor exception.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||||
|
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||||
|
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Interrupt Priority
|
||||||
|
\details Reads the priority of a device specific interrupt or a processor exception.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
\param [in] IRQn Interrupt number.
|
||||||
|
\return Interrupt Priority.
|
||||||
|
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Encode Priority
|
||||||
|
\details Encodes the priority for an interrupt with the given priority group,
|
||||||
|
preemptive priority value, and subpriority value.
|
||||||
|
In case of a conflict between priority grouping and available
|
||||||
|
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
||||||
|
\param [in] PriorityGroup Used priority group.
|
||||||
|
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
||||||
|
\param [in] SubPriority Subpriority value (starting from 0).
|
||||||
|
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
||||||
|
{
|
||||||
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||||
|
uint32_t PreemptPriorityBits;
|
||||||
|
uint32_t SubPriorityBits;
|
||||||
|
|
||||||
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||||||
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||||
|
|
||||||
|
return (
|
||||||
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
||||||
|
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
||||||
|
);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Decode Priority
|
||||||
|
\details Decodes an interrupt priority value with a given priority group to
|
||||||
|
preemptive priority value and subpriority value.
|
||||||
|
In case of a conflict between priority grouping and available
|
||||||
|
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
|
||||||
|
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
|
||||||
|
\param [in] PriorityGroup Used priority group.
|
||||||
|
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
|
||||||
|
\param [out] pSubPriority Subpriority value (starting from 0).
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
|
||||||
|
{
|
||||||
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||||
|
uint32_t PreemptPriorityBits;
|
||||||
|
uint32_t SubPriorityBits;
|
||||||
|
|
||||||
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||||||
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||||
|
|
||||||
|
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
|
||||||
|
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Interrupt Vector
|
||||||
|
\details Sets an interrupt vector in SRAM based interrupt vector table.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
Address 0 must be mapped to SRAM.
|
||||||
|
\param [in] IRQn Interrupt number
|
||||||
|
\param [in] vector Address of interrupt handler function
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
||||||
|
{
|
||||||
|
uint32_t *vectors = (uint32_t *)0x0U;
|
||||||
|
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Interrupt Vector
|
||||||
|
\details Reads an interrupt vector from interrupt vector table.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
\param [in] IRQn Interrupt number.
|
||||||
|
\return Address of interrupt handler function
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
uint32_t *vectors = (uint32_t *)0x0U;
|
||||||
|
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief System Reset
|
||||||
|
\details Initiates a system reset request to reset the MCU.
|
||||||
|
*/
|
||||||
|
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
|
||||||
|
{
|
||||||
|
__DSB(); /* Ensure all outstanding memory accesses included
|
||||||
|
buffered write are completed before reset */
|
||||||
|
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||||||
|
SCB_AIRCR_SYSRESETREQ_Msk);
|
||||||
|
__DSB(); /* Ensure completion of memory access */
|
||||||
|
|
||||||
|
for(;;) /* wait until reset */
|
||||||
|
{
|
||||||
|
__NOP();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*@} end of CMSIS_Core_NVICFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
/* ########################## FPU functions #################################### */
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_Core_FunctionInterface
|
||||||
|
\defgroup CMSIS_Core_FpuFunctions FPU Functions
|
||||||
|
\brief Function that provides FPU type.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief get FPU type
|
||||||
|
\details returns the FPU type
|
||||||
|
\returns
|
||||||
|
- \b 0: No FPU
|
||||||
|
- \b 1: Single precision FPU
|
||||||
|
- \b 2: Double + Single precision FPU
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
|
||||||
|
{
|
||||||
|
return 0U; /* No FPU */
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*@} end of CMSIS_Core_FpuFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* ################################## SysTick function ############################################ */
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_Core_FunctionInterface
|
||||||
|
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
|
||||||
|
\brief Functions that configure the System.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief System Tick Configuration
|
||||||
|
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
||||||
|
Counter is in free running mode to generate periodic interrupts.
|
||||||
|
\param [in] ticks Number of ticks between two interrupts.
|
||||||
|
\return 0 Function succeeded.
|
||||||
|
\return 1 Function failed.
|
||||||
|
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
||||||
|
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
||||||
|
must contain a vendor-specific implementation of this function.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
||||||
|
{
|
||||||
|
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
||||||
|
{
|
||||||
|
return (1UL); /* Reload value impossible */
|
||||||
|
}
|
||||||
|
|
||||||
|
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
||||||
|
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||||
|
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||||
|
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||||
|
SysTick_CTRL_TICKINT_Msk |
|
||||||
|
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
||||||
|
return (0UL); /* Function successful */
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*@} end of CMSIS_Core_SysTickFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __CORE_CM1_H_DEPENDANT */
|
||||||
|
|
||||||
|
#endif /* __CMSIS_GENERIC */
|
File diff suppressed because it is too large
Load Diff
|
@ -1,40 +1,30 @@
|
||||||
/**************************************************************************//**
|
/**************************************************************************//**
|
||||||
* @file core_cm3.h
|
* @file core_cm3.h
|
||||||
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
|
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
|
||||||
* @version V4.30
|
* @version V5.0.8
|
||||||
* @date 20. October 2015
|
* @date 04. June 2018
|
||||||
******************************************************************************/
|
******************************************************************************/
|
||||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
/*
|
||||||
|
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||||
All rights reserved.
|
*
|
||||||
Redistribution and use in source and binary forms, with or without
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
modification, are permitted provided that the following conditions are met:
|
*
|
||||||
- Redistributions of source code must retain the above copyright
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
notice, this list of conditions and the following disclaimer.
|
* not use this file except in compliance with the License.
|
||||||
- Redistributions in binary form must reproduce the above copyright
|
* You may obtain a copy of the License at
|
||||||
notice, this list of conditions and the following disclaimer in the
|
*
|
||||||
documentation and/or other materials provided with the distribution.
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
- Neither the name of ARM nor the names of its contributors may be used
|
*
|
||||||
to endorse or promote products derived from this software without
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
specific prior written permission.
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
*
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
* See the License for the specific language governing permissions and
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
* limitations under the License.
|
||||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
*/
|
||||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
|
||||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
|
||||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
||||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
|
||||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
|
||||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
||||||
POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
---------------------------------------------------------------------------*/
|
|
||||||
|
|
||||||
|
|
||||||
#if defined ( __ICCARM__ )
|
#if defined ( __ICCARM__ )
|
||||||
#pragma system_include /* treat file as system include file for MISRA check */
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
#elif defined (__clang__)
|
||||||
#pragma clang system_header /* treat file as system include file */
|
#pragma clang system_header /* treat file as system include file */
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
@ -70,53 +60,15 @@
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
#include "cmsis_version.h"
|
||||||
|
|
||||||
/* CMSIS CM3 definitions */
|
/* CMSIS CM3 definitions */
|
||||||
#define __CM3_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
|
#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
|
||||||
#define __CM3_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
|
#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
|
||||||
#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
|
#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
|
||||||
__CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
|
__CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
|
||||||
|
|
||||||
#define __CORTEX_M (0x03U) /*!< Cortex-M Core */
|
#define __CORTEX_M (3U) /*!< Cortex-M Core */
|
||||||
|
|
||||||
|
|
||||||
#if defined ( __CC_ARM )
|
|
||||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
|
||||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
|
||||||
#define __STATIC_INLINE static __inline
|
|
||||||
|
|
||||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
|
||||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
|
||||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
|
||||||
#define __STATIC_INLINE static __inline
|
|
||||||
|
|
||||||
#elif defined ( __GNUC__ )
|
|
||||||
#define __ASM __asm /*!< asm keyword for GNU Compiler */
|
|
||||||
#define __INLINE inline /*!< inline keyword for GNU Compiler */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#elif defined ( __ICCARM__ )
|
|
||||||
#define __ASM __asm /*!< asm keyword for IAR Compiler */
|
|
||||||
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#elif defined ( __TMS470__ )
|
|
||||||
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#elif defined ( __TASKING__ )
|
|
||||||
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
|
|
||||||
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#elif defined ( __CSMC__ )
|
|
||||||
#define __packed
|
|
||||||
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
|
|
||||||
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#else
|
|
||||||
#error Unknown compiler
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/** __FPU_USED indicates whether an FPU is used or not.
|
/** __FPU_USED indicates whether an FPU is used or not.
|
||||||
This core does not support an FPU at all
|
This core does not support an FPU at all
|
||||||
|
@ -128,7 +80,7 @@
|
||||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||||
#if defined __ARM_PCS_VFP
|
#if defined __ARM_PCS_VFP
|
||||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
#endif
|
#endif
|
||||||
|
@ -143,7 +95,7 @@
|
||||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#elif defined ( __TMS470__ )
|
#elif defined ( __TI_ARM__ )
|
||||||
#if defined __TI_VFP_SUPPORT__
|
#if defined __TI_VFP_SUPPORT__
|
||||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
#endif
|
#endif
|
||||||
|
@ -160,8 +112,8 @@
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#include "core_cmInstr.h" /* Core Instruction Access */
|
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
|
||||||
#include "core_cmFunc.h" /* Core Function Access */
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
}
|
}
|
||||||
|
@ -191,7 +143,7 @@
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifndef __NVIC_PRIO_BITS
|
#ifndef __NVIC_PRIO_BITS
|
||||||
#define __NVIC_PRIO_BITS 4U
|
#define __NVIC_PRIO_BITS 3U
|
||||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
@ -308,9 +260,11 @@ typedef union
|
||||||
struct
|
struct
|
||||||
{
|
{
|
||||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||||
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
|
uint32_t _reserved0:1; /*!< bit: 9 Reserved */
|
||||||
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
|
uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
|
||||||
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
|
uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */
|
||||||
|
uint32_t T:1; /*!< bit: 24 Thumb bit */
|
||||||
|
uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
|
||||||
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
|
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
|
||||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||||
|
@ -336,12 +290,15 @@ typedef union
|
||||||
#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
|
#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
|
||||||
#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
|
#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
|
||||||
|
|
||||||
#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
|
#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
|
||||||
#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
|
#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
|
||||||
|
|
||||||
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
|
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
|
||||||
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
|
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
|
||||||
|
|
||||||
|
#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
|
||||||
|
#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
|
||||||
|
|
||||||
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
|
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
|
||||||
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
|
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
|
||||||
|
|
||||||
|
@ -487,7 +444,7 @@ typedef struct
|
||||||
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
|
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
|
||||||
|
|
||||||
/* SCB Vector Table Offset Register Definitions */
|
/* SCB Vector Table Offset Register Definitions */
|
||||||
#if (__CM3_REV < 0x0201U) /* core r2p1 */
|
#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */
|
||||||
#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
|
#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
|
||||||
#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
|
#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
|
||||||
|
|
||||||
|
@ -602,6 +559,60 @@ typedef struct
|
||||||
#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
|
#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
|
||||||
#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
|
#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
|
||||||
|
|
||||||
|
/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
|
||||||
|
#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
|
||||||
|
#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
|
||||||
|
#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
|
||||||
|
#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
|
||||||
|
#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
|
||||||
|
#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
|
||||||
|
|
||||||
|
/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
|
||||||
|
#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
|
||||||
|
#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
|
||||||
|
#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
|
||||||
|
#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
|
||||||
|
#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
|
||||||
|
#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
|
||||||
|
#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
|
||||||
|
|
||||||
|
/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
|
||||||
|
#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
|
||||||
|
#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
|
||||||
|
#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
|
||||||
|
#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
|
||||||
|
#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
|
||||||
|
#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
|
||||||
|
#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
|
||||||
|
|
||||||
/* SCB Hard Fault Status Register Definitions */
|
/* SCB Hard Fault Status Register Definitions */
|
||||||
#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
|
#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
|
||||||
#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
|
#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
|
||||||
|
@ -645,7 +656,7 @@ typedef struct
|
||||||
{
|
{
|
||||||
uint32_t RESERVED0[1U];
|
uint32_t RESERVED0[1U];
|
||||||
__IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
|
__IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
|
||||||
#if ((defined __CM3_REV) && (__CM3_REV >= 0x200U))
|
#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
|
||||||
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
|
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
|
||||||
#else
|
#else
|
||||||
uint32_t RESERVED1[1U];
|
uint32_t RESERVED1[1U];
|
||||||
|
@ -770,7 +781,7 @@ typedef struct
|
||||||
|
|
||||||
/* ITM Trace Privilege Register Definitions */
|
/* ITM Trace Privilege Register Definitions */
|
||||||
#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
|
#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
|
||||||
#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
|
#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
|
||||||
|
|
||||||
/* ITM Trace Control Register Definitions */
|
/* ITM Trace Control Register Definitions */
|
||||||
#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
|
#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
|
||||||
|
@ -984,7 +995,7 @@ typedef struct
|
||||||
*/
|
*/
|
||||||
typedef struct
|
typedef struct
|
||||||
{
|
{
|
||||||
__IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
|
__IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
|
||||||
__IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
|
__IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
|
||||||
uint32_t RESERVED0[2U];
|
uint32_t RESERVED0[2U];
|
||||||
__IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
|
__IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
|
||||||
|
@ -995,7 +1006,7 @@ typedef struct
|
||||||
__IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
|
__IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
|
||||||
__IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
|
__IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
|
||||||
uint32_t RESERVED3[759U];
|
uint32_t RESERVED3[759U];
|
||||||
__IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
|
__IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
|
||||||
__IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
|
__IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
|
||||||
__IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
|
__IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
|
||||||
uint32_t RESERVED4[1U];
|
uint32_t RESERVED4[1U];
|
||||||
|
@ -1065,8 +1076,11 @@ typedef struct
|
||||||
#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
|
#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
|
||||||
|
|
||||||
/* TPI ITATBCTR2 Register Definitions */
|
/* TPI ITATBCTR2 Register Definitions */
|
||||||
#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
|
#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
|
||||||
#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
|
#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
|
||||||
|
|
||||||
|
#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
|
||||||
|
#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
|
||||||
|
|
||||||
/* TPI Integration ITM Data Register Definitions (FIFO1) */
|
/* TPI Integration ITM Data Register Definitions (FIFO1) */
|
||||||
#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
|
#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
|
||||||
|
@ -1091,12 +1105,15 @@ typedef struct
|
||||||
#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
|
#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
|
||||||
|
|
||||||
/* TPI ITATBCTR0 Register Definitions */
|
/* TPI ITATBCTR0 Register Definitions */
|
||||||
#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
|
#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
|
||||||
#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
|
#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
|
||||||
|
|
||||||
|
#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
|
||||||
|
#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
|
||||||
|
|
||||||
/* TPI Integration Mode Control Register Definitions */
|
/* TPI Integration Mode Control Register Definitions */
|
||||||
#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
|
#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
|
||||||
#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
|
#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
|
||||||
|
|
||||||
/* TPI DEVID Register Definitions */
|
/* TPI DEVID Register Definitions */
|
||||||
#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
|
#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
|
||||||
|
@ -1118,16 +1135,16 @@ typedef struct
|
||||||
#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
|
#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
|
||||||
|
|
||||||
/* TPI DEVTYPE Register Definitions */
|
/* TPI DEVTYPE Register Definitions */
|
||||||
#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
|
#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
|
||||||
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
|
|
||||||
|
|
||||||
#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
|
|
||||||
#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
|
#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
|
||||||
|
|
||||||
|
#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
|
||||||
|
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
|
||||||
|
|
||||||
/*@}*/ /* end of group CMSIS_TPI */
|
/*@}*/ /* end of group CMSIS_TPI */
|
||||||
|
|
||||||
|
|
||||||
#if (__MPU_PRESENT == 1U)
|
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
|
||||||
/**
|
/**
|
||||||
\ingroup CMSIS_core_register
|
\ingroup CMSIS_core_register
|
||||||
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
|
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
|
||||||
|
@ -1153,6 +1170,8 @@ typedef struct
|
||||||
__IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
|
__IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
|
||||||
} MPU_Type;
|
} MPU_Type;
|
||||||
|
|
||||||
|
#define MPU_TYPE_RALIASES 4U
|
||||||
|
|
||||||
/* MPU Type Register Definitions */
|
/* MPU Type Register Definitions */
|
||||||
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
|
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
|
||||||
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
|
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
|
||||||
|
@ -1337,18 +1356,18 @@ typedef struct
|
||||||
/**
|
/**
|
||||||
\brief Mask and shift a bit field value for use in a register bit range.
|
\brief Mask and shift a bit field value for use in a register bit range.
|
||||||
\param[in] field Name of the register bit field.
|
\param[in] field Name of the register bit field.
|
||||||
\param[in] value Value of the bit field.
|
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
|
||||||
\return Masked and shifted value.
|
\return Masked and shifted value.
|
||||||
*/
|
*/
|
||||||
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
|
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Mask and shift a register value to extract a bit filed value.
|
\brief Mask and shift a register value to extract a bit filed value.
|
||||||
\param[in] field Name of the register bit field.
|
\param[in] field Name of the register bit field.
|
||||||
\param[in] value Value of register.
|
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
|
||||||
\return Masked and shifted bit field value.
|
\return Masked and shifted bit field value.
|
||||||
*/
|
*/
|
||||||
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
|
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
|
||||||
|
|
||||||
/*@} end of group CMSIS_core_bitfield */
|
/*@} end of group CMSIS_core_bitfield */
|
||||||
|
|
||||||
|
@ -1360,7 +1379,7 @@ typedef struct
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Memory mapping of Cortex-M3 Hardware */
|
/* Memory mapping of Core Hardware */
|
||||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||||
#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
|
#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
|
||||||
#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
|
#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
|
||||||
|
@ -1379,7 +1398,7 @@ typedef struct
|
||||||
#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
|
#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
|
||||||
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
|
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
|
||||||
|
|
||||||
#if (__MPU_PRESENT == 1U)
|
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
|
||||||
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
|
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
|
||||||
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
|
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
|
||||||
#endif
|
#endif
|
||||||
|
@ -1410,6 +1429,45 @@ typedef struct
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
#ifdef CMSIS_NVIC_VIRTUAL
|
||||||
|
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||||
|
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
||||||
|
#endif
|
||||||
|
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||||
|
#else
|
||||||
|
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
|
||||||
|
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
|
||||||
|
#define NVIC_EnableIRQ __NVIC_EnableIRQ
|
||||||
|
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
||||||
|
#define NVIC_DisableIRQ __NVIC_DisableIRQ
|
||||||
|
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
||||||
|
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
||||||
|
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
||||||
|
#define NVIC_GetActive __NVIC_GetActive
|
||||||
|
#define NVIC_SetPriority __NVIC_SetPriority
|
||||||
|
#define NVIC_GetPriority __NVIC_GetPriority
|
||||||
|
#define NVIC_SystemReset __NVIC_SystemReset
|
||||||
|
#endif /* CMSIS_NVIC_VIRTUAL */
|
||||||
|
|
||||||
|
#ifdef CMSIS_VECTAB_VIRTUAL
|
||||||
|
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||||
|
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
||||||
|
#endif
|
||||||
|
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||||
|
#else
|
||||||
|
#define NVIC_SetVector __NVIC_SetVector
|
||||||
|
#define NVIC_GetVector __NVIC_GetVector
|
||||||
|
#endif /* (CMSIS_VECTAB_VIRTUAL) */
|
||||||
|
|
||||||
|
#define NVIC_USER_IRQ_OFFSET 16
|
||||||
|
|
||||||
|
|
||||||
|
/* The following EXC_RETURN values are saved the LR on exception entry */
|
||||||
|
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
|
||||||
|
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
|
||||||
|
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Set Priority Grouping
|
\brief Set Priority Grouping
|
||||||
\details Sets the priority grouping field using the required unlock sequence.
|
\details Sets the priority grouping field using the required unlock sequence.
|
||||||
|
@ -1419,7 +1477,7 @@ typedef struct
|
||||||
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
||||||
\param [in] PriorityGroup Priority grouping field.
|
\param [in] PriorityGroup Priority grouping field.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
||||||
{
|
{
|
||||||
uint32_t reg_value;
|
uint32_t reg_value;
|
||||||
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||||
|
@ -1428,7 +1486,7 @@ __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
||||||
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
|
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
|
||||||
reg_value = (reg_value |
|
reg_value = (reg_value |
|
||||||
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||||||
(PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
|
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
|
||||||
SCB->AIRCR = reg_value;
|
SCB->AIRCR = reg_value;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -1438,121 +1496,178 @@ __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
||||||
\details Reads the priority grouping field from the NVIC Interrupt Controller.
|
\details Reads the priority grouping field from the NVIC Interrupt Controller.
|
||||||
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
|
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
|
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
|
||||||
{
|
{
|
||||||
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
|
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Enable External Interrupt
|
\brief Enable Interrupt
|
||||||
\details Enables a device-specific interrupt in the NVIC interrupt controller.
|
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
||||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Disable External Interrupt
|
\brief Get Interrupt Enable status
|
||||||
\details Disables a device-specific interrupt in the NVIC interrupt controller.
|
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
|
||||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\return 0 Interrupt is not enabled.
|
||||||
|
\return 1 Interrupt is enabled.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return(0U);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Disable Interrupt
|
||||||
|
\details Disables a device specific interrupt in the NVIC interrupt controller.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Get Pending Interrupt
|
\brief Get Pending Interrupt
|
||||||
\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
|
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
|
||||||
\param [in] IRQn Interrupt number.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
\return 0 Interrupt status is not pending.
|
\return 0 Interrupt status is not pending.
|
||||||
\return 1 Interrupt status is pending.
|
\return 1 Interrupt status is pending.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return(0U);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Set Pending Interrupt
|
\brief Set Pending Interrupt
|
||||||
\details Sets the pending bit of an external interrupt.
|
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
|
||||||
\param [in] IRQn Interrupt number. Value cannot be negative.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Clear Pending Interrupt
|
\brief Clear Pending Interrupt
|
||||||
\details Clears the pending bit of an external interrupt.
|
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
|
||||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Get Active Interrupt
|
\brief Get Active Interrupt
|
||||||
\details Reads the active register in NVIC and returns the active bit.
|
\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
|
||||||
\param [in] IRQn Interrupt number.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
\return 0 Interrupt status is not active.
|
\return 0 Interrupt status is not active.
|
||||||
\return 1 Interrupt status is active.
|
\return 1 Interrupt status is active.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
|
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return(0U);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Set Interrupt Priority
|
\brief Set Interrupt Priority
|
||||||
\details Sets the priority of an interrupt.
|
\details Sets the priority of a device specific interrupt or a processor exception.
|
||||||
\note The priority cannot be set for every core interrupt.
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
\param [in] IRQn Interrupt number.
|
\param [in] IRQn Interrupt number.
|
||||||
\param [in] priority Priority to set.
|
\param [in] priority Priority to set.
|
||||||
|
\note The priority cannot be set for every processor exception.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||||
{
|
{
|
||||||
if ((int32_t)(IRQn) < 0)
|
if ((int32_t)(IRQn) >= 0)
|
||||||
{
|
{
|
||||||
SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Get Interrupt Priority
|
\brief Get Interrupt Priority
|
||||||
\details Reads the priority of an interrupt.
|
\details Reads the priority of a device specific interrupt or a processor exception.
|
||||||
The interrupt number can be positive to specify an external (device specific) interrupt,
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
or negative to specify an internal (core) interrupt.
|
or negative to specify a processor exception.
|
||||||
\param [in] IRQn Interrupt number.
|
\param [in] IRQn Interrupt number.
|
||||||
\return Interrupt Priority.
|
\return Interrupt Priority.
|
||||||
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
|
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
|
|
||||||
if ((int32_t)(IRQn) < 0)
|
if ((int32_t)(IRQn) >= 0)
|
||||||
{
|
{
|
||||||
return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
|
return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
|
return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -1609,11 +1724,42 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Interrupt Vector
|
||||||
|
\details Sets an interrupt vector in SRAM based interrupt vector table.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
VTOR must been relocated to SRAM before.
|
||||||
|
\param [in] IRQn Interrupt number
|
||||||
|
\param [in] vector Address of interrupt handler function
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
||||||
|
{
|
||||||
|
uint32_t *vectors = (uint32_t *)SCB->VTOR;
|
||||||
|
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Interrupt Vector
|
||||||
|
\details Reads an interrupt vector from interrupt vector table.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
\param [in] IRQn Interrupt number.
|
||||||
|
\return Address of interrupt handler function
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
uint32_t *vectors = (uint32_t *)SCB->VTOR;
|
||||||
|
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief System Reset
|
\brief System Reset
|
||||||
\details Initiates a system reset request to reset the MCU.
|
\details Initiates a system reset request to reset the MCU.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_SystemReset(void)
|
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
|
||||||
{
|
{
|
||||||
__DSB(); /* Ensure all outstanding memory accesses included
|
__DSB(); /* Ensure all outstanding memory accesses included
|
||||||
buffered write are completed before reset */
|
buffered write are completed before reset */
|
||||||
|
@ -1630,6 +1776,38 @@ __STATIC_INLINE void NVIC_SystemReset(void)
|
||||||
|
|
||||||
/*@} end of CMSIS_Core_NVICFunctions */
|
/*@} end of CMSIS_Core_NVICFunctions */
|
||||||
|
|
||||||
|
/* ########################## MPU functions #################################### */
|
||||||
|
|
||||||
|
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
|
||||||
|
|
||||||
|
#include "mpu_armv7.h"
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* ########################## FPU functions #################################### */
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_Core_FunctionInterface
|
||||||
|
\defgroup CMSIS_Core_FpuFunctions FPU Functions
|
||||||
|
\brief Function that provides FPU type.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief get FPU type
|
||||||
|
\details returns the FPU type
|
||||||
|
\returns
|
||||||
|
- \b 0: No FPU
|
||||||
|
- \b 1: Single precision FPU
|
||||||
|
- \b 2: Double + Single precision FPU
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
|
||||||
|
{
|
||||||
|
return 0U; /* No FPU */
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*@} end of CMSIS_Core_FpuFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/* ################################## SysTick function ############################################ */
|
/* ################################## SysTick function ############################################ */
|
||||||
|
@ -1640,7 +1818,7 @@ __STATIC_INLINE void NVIC_SystemReset(void)
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#if (__Vendor_SysTickConfig == 0U)
|
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief System Tick Configuration
|
\brief System Tick Configuration
|
||||||
|
@ -1683,8 +1861,8 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
|
extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
|
||||||
#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
|
#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -1,40 +1,30 @@
|
||||||
/**************************************************************************//**
|
/**************************************************************************//**
|
||||||
* @file core_cm4.h
|
* @file core_cm4.h
|
||||||
* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
|
* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
|
||||||
* @version V4.30
|
* @version V5.0.8
|
||||||
* @date 20. October 2015
|
* @date 04. June 2018
|
||||||
******************************************************************************/
|
******************************************************************************/
|
||||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
/*
|
||||||
|
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||||
All rights reserved.
|
*
|
||||||
Redistribution and use in source and binary forms, with or without
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
modification, are permitted provided that the following conditions are met:
|
*
|
||||||
- Redistributions of source code must retain the above copyright
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
notice, this list of conditions and the following disclaimer.
|
* not use this file except in compliance with the License.
|
||||||
- Redistributions in binary form must reproduce the above copyright
|
* You may obtain a copy of the License at
|
||||||
notice, this list of conditions and the following disclaimer in the
|
*
|
||||||
documentation and/or other materials provided with the distribution.
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
- Neither the name of ARM nor the names of its contributors may be used
|
*
|
||||||
to endorse or promote products derived from this software without
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
specific prior written permission.
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
*
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
* See the License for the specific language governing permissions and
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
* limitations under the License.
|
||||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
*/
|
||||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
|
||||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
|
||||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
||||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
|
||||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
|
||||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
||||||
POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
---------------------------------------------------------------------------*/
|
|
||||||
|
|
||||||
|
|
||||||
#if defined ( __ICCARM__ )
|
#if defined ( __ICCARM__ )
|
||||||
#pragma system_include /* treat file as system include file for MISRA check */
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
#elif defined (__clang__)
|
||||||
#pragma clang system_header /* treat file as system include file */
|
#pragma clang system_header /* treat file as system include file */
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
@ -70,60 +60,22 @@
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* CMSIS CM4 definitions */
|
#include "cmsis_version.h"
|
||||||
#define __CM4_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
|
|
||||||
#define __CM4_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
|
/* CMSIS CM4 definitions */
|
||||||
|
#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
|
||||||
|
#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
|
||||||
#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
|
#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
|
||||||
__CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
|
__CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
|
||||||
|
|
||||||
#define __CORTEX_M (0x04U) /*!< Cortex-M Core */
|
#define __CORTEX_M (4U) /*!< Cortex-M Core */
|
||||||
|
|
||||||
|
|
||||||
#if defined ( __CC_ARM )
|
|
||||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
|
||||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
|
||||||
#define __STATIC_INLINE static __inline
|
|
||||||
|
|
||||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
|
||||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
|
||||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
|
||||||
#define __STATIC_INLINE static __inline
|
|
||||||
|
|
||||||
#elif defined ( __GNUC__ )
|
|
||||||
#define __ASM __asm /*!< asm keyword for GNU Compiler */
|
|
||||||
#define __INLINE inline /*!< inline keyword for GNU Compiler */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#elif defined ( __ICCARM__ )
|
|
||||||
#define __ASM __asm /*!< asm keyword for IAR Compiler */
|
|
||||||
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#elif defined ( __TMS470__ )
|
|
||||||
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#elif defined ( __TASKING__ )
|
|
||||||
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
|
|
||||||
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#elif defined ( __CSMC__ )
|
|
||||||
#define __packed
|
|
||||||
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
|
|
||||||
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#else
|
|
||||||
#error Unknown compiler
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/** __FPU_USED indicates whether an FPU is used or not.
|
/** __FPU_USED indicates whether an FPU is used or not.
|
||||||
For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
|
For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
|
||||||
*/
|
*/
|
||||||
#if defined ( __CC_ARM )
|
#if defined ( __CC_ARM )
|
||||||
#if defined __TARGET_FPU_VFP
|
#if defined __TARGET_FPU_VFP
|
||||||
#if (__FPU_PRESENT == 1U)
|
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||||
#define __FPU_USED 1U
|
#define __FPU_USED 1U
|
||||||
#else
|
#else
|
||||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
@ -133,9 +85,9 @@
|
||||||
#define __FPU_USED 0U
|
#define __FPU_USED 0U
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||||
#if defined __ARM_PCS_VFP
|
#if defined __ARM_PCS_VFP
|
||||||
#if (__FPU_PRESENT == 1)
|
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||||
#define __FPU_USED 1U
|
#define __FPU_USED 1U
|
||||||
#else
|
#else
|
||||||
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
@ -147,7 +99,7 @@
|
||||||
|
|
||||||
#elif defined ( __GNUC__ )
|
#elif defined ( __GNUC__ )
|
||||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||||
#if (__FPU_PRESENT == 1U)
|
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||||
#define __FPU_USED 1U
|
#define __FPU_USED 1U
|
||||||
#else
|
#else
|
||||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
@ -159,7 +111,7 @@
|
||||||
|
|
||||||
#elif defined ( __ICCARM__ )
|
#elif defined ( __ICCARM__ )
|
||||||
#if defined __ARMVFP__
|
#if defined __ARMVFP__
|
||||||
#if (__FPU_PRESENT == 1U)
|
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||||
#define __FPU_USED 1U
|
#define __FPU_USED 1U
|
||||||
#else
|
#else
|
||||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
@ -169,9 +121,9 @@
|
||||||
#define __FPU_USED 0U
|
#define __FPU_USED 0U
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#elif defined ( __TMS470__ )
|
#elif defined ( __TI_ARM__ )
|
||||||
#if defined __TI_VFP_SUPPORT__
|
#if defined __TI_VFP_SUPPORT__
|
||||||
#if (__FPU_PRESENT == 1U)
|
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||||
#define __FPU_USED 1U
|
#define __FPU_USED 1U
|
||||||
#else
|
#else
|
||||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
@ -183,7 +135,7 @@
|
||||||
|
|
||||||
#elif defined ( __TASKING__ )
|
#elif defined ( __TASKING__ )
|
||||||
#if defined __FPU_VFP__
|
#if defined __FPU_VFP__
|
||||||
#if (__FPU_PRESENT == 1U)
|
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||||
#define __FPU_USED 1U
|
#define __FPU_USED 1U
|
||||||
#else
|
#else
|
||||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
@ -195,7 +147,7 @@
|
||||||
|
|
||||||
#elif defined ( __CSMC__ )
|
#elif defined ( __CSMC__ )
|
||||||
#if ( __CSMC__ & 0x400U)
|
#if ( __CSMC__ & 0x400U)
|
||||||
#if (__FPU_PRESENT == 1U)
|
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
|
||||||
#define __FPU_USED 1U
|
#define __FPU_USED 1U
|
||||||
#else
|
#else
|
||||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
|
@ -207,9 +159,8 @@
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#include "core_cmInstr.h" /* Core Instruction Access */
|
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
|
||||||
#include "core_cmFunc.h" /* Core Function Access */
|
|
||||||
#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
}
|
}
|
||||||
|
@ -244,7 +195,7 @@
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifndef __NVIC_PRIO_BITS
|
#ifndef __NVIC_PRIO_BITS
|
||||||
#define __NVIC_PRIO_BITS 4U
|
#define __NVIC_PRIO_BITS 3U
|
||||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
@ -367,11 +318,12 @@ typedef union
|
||||||
struct
|
struct
|
||||||
{
|
{
|
||||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||||
uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
|
uint32_t _reserved0:1; /*!< bit: 9 Reserved */
|
||||||
|
uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
|
||||||
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
|
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
|
||||||
uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
|
uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
|
||||||
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
|
uint32_t T:1; /*!< bit: 24 Thumb bit */
|
||||||
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
|
uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
|
||||||
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
|
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
|
||||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||||
|
@ -397,8 +349,8 @@ typedef union
|
||||||
#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
|
#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
|
||||||
#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
|
#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
|
||||||
|
|
||||||
#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
|
#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
|
||||||
#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
|
#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
|
||||||
|
|
||||||
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
|
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
|
||||||
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
|
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
|
||||||
|
@ -406,6 +358,9 @@ typedef union
|
||||||
#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
|
#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
|
||||||
#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
|
#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
|
||||||
|
|
||||||
|
#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
|
||||||
|
#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
|
||||||
|
|
||||||
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
|
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
|
||||||
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
|
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
|
||||||
|
|
||||||
|
@ -662,6 +617,66 @@ typedef struct
|
||||||
#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
|
#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
|
||||||
#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
|
#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
|
||||||
|
|
||||||
|
/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
|
||||||
|
#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
|
||||||
|
#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
|
||||||
|
#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
|
||||||
|
#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
|
||||||
|
#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
|
||||||
|
#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
|
||||||
|
#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
|
||||||
|
|
||||||
|
/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
|
||||||
|
#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
|
||||||
|
#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
|
||||||
|
#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
|
||||||
|
#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
|
||||||
|
#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
|
||||||
|
#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
|
||||||
|
#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
|
||||||
|
#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
|
||||||
|
|
||||||
|
/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
|
||||||
|
#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
|
||||||
|
#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
|
||||||
|
#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
|
||||||
|
#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
|
||||||
|
#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
|
||||||
|
#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
|
||||||
|
#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
|
||||||
|
|
||||||
/* SCB Hard Fault Status Register Definitions */
|
/* SCB Hard Fault Status Register Definitions */
|
||||||
#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
|
#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
|
||||||
#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
|
#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
|
||||||
|
@ -831,7 +846,7 @@ typedef struct
|
||||||
|
|
||||||
/* ITM Trace Privilege Register Definitions */
|
/* ITM Trace Privilege Register Definitions */
|
||||||
#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
|
#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
|
||||||
#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
|
#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
|
||||||
|
|
||||||
/* ITM Trace Control Register Definitions */
|
/* ITM Trace Control Register Definitions */
|
||||||
#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
|
#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
|
||||||
|
@ -1045,7 +1060,7 @@ typedef struct
|
||||||
*/
|
*/
|
||||||
typedef struct
|
typedef struct
|
||||||
{
|
{
|
||||||
__IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
|
__IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
|
||||||
__IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
|
__IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
|
||||||
uint32_t RESERVED0[2U];
|
uint32_t RESERVED0[2U];
|
||||||
__IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
|
__IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
|
||||||
|
@ -1056,7 +1071,7 @@ typedef struct
|
||||||
__IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
|
__IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
|
||||||
__IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
|
__IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
|
||||||
uint32_t RESERVED3[759U];
|
uint32_t RESERVED3[759U];
|
||||||
__IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
|
__IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
|
||||||
__IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
|
__IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
|
||||||
__IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
|
__IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
|
||||||
uint32_t RESERVED4[1U];
|
uint32_t RESERVED4[1U];
|
||||||
|
@ -1126,8 +1141,11 @@ typedef struct
|
||||||
#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
|
#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
|
||||||
|
|
||||||
/* TPI ITATBCTR2 Register Definitions */
|
/* TPI ITATBCTR2 Register Definitions */
|
||||||
#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
|
#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
|
||||||
#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
|
#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
|
||||||
|
|
||||||
|
#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
|
||||||
|
#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
|
||||||
|
|
||||||
/* TPI Integration ITM Data Register Definitions (FIFO1) */
|
/* TPI Integration ITM Data Register Definitions (FIFO1) */
|
||||||
#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
|
#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
|
||||||
|
@ -1152,12 +1170,15 @@ typedef struct
|
||||||
#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
|
#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
|
||||||
|
|
||||||
/* TPI ITATBCTR0 Register Definitions */
|
/* TPI ITATBCTR0 Register Definitions */
|
||||||
#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
|
#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
|
||||||
#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
|
#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
|
||||||
|
|
||||||
|
#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
|
||||||
|
#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
|
||||||
|
|
||||||
/* TPI Integration Mode Control Register Definitions */
|
/* TPI Integration Mode Control Register Definitions */
|
||||||
#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
|
#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
|
||||||
#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
|
#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
|
||||||
|
|
||||||
/* TPI DEVID Register Definitions */
|
/* TPI DEVID Register Definitions */
|
||||||
#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
|
#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
|
||||||
|
@ -1179,16 +1200,16 @@ typedef struct
|
||||||
#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
|
#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
|
||||||
|
|
||||||
/* TPI DEVTYPE Register Definitions */
|
/* TPI DEVTYPE Register Definitions */
|
||||||
#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
|
#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
|
||||||
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
|
|
||||||
|
|
||||||
#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
|
|
||||||
#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
|
#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
|
||||||
|
|
||||||
|
#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
|
||||||
|
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
|
||||||
|
|
||||||
/*@}*/ /* end of group CMSIS_TPI */
|
/*@}*/ /* end of group CMSIS_TPI */
|
||||||
|
|
||||||
|
|
||||||
#if (__MPU_PRESENT == 1U)
|
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
|
||||||
/**
|
/**
|
||||||
\ingroup CMSIS_core_register
|
\ingroup CMSIS_core_register
|
||||||
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
|
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
|
||||||
|
@ -1214,6 +1235,8 @@ typedef struct
|
||||||
__IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
|
__IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
|
||||||
} MPU_Type;
|
} MPU_Type;
|
||||||
|
|
||||||
|
#define MPU_TYPE_RALIASES 4U
|
||||||
|
|
||||||
/* MPU Type Register Definitions */
|
/* MPU Type Register Definitions */
|
||||||
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
|
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
|
||||||
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
|
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
|
||||||
|
@ -1280,10 +1303,9 @@ typedef struct
|
||||||
#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
|
#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
|
||||||
|
|
||||||
/*@} end of group CMSIS_MPU */
|
/*@} end of group CMSIS_MPU */
|
||||||
#endif
|
#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
|
||||||
|
|
||||||
|
|
||||||
#if (__FPU_PRESENT == 1U)
|
|
||||||
/**
|
/**
|
||||||
\ingroup CMSIS_core_register
|
\ingroup CMSIS_core_register
|
||||||
\defgroup CMSIS_FPU Floating Point Unit (FPU)
|
\defgroup CMSIS_FPU Floating Point Unit (FPU)
|
||||||
|
@ -1388,7 +1410,6 @@ typedef struct
|
||||||
#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
|
#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
|
||||||
|
|
||||||
/*@} end of group CMSIS_FPU */
|
/*@} end of group CMSIS_FPU */
|
||||||
#endif
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -1506,18 +1527,18 @@ typedef struct
|
||||||
/**
|
/**
|
||||||
\brief Mask and shift a bit field value for use in a register bit range.
|
\brief Mask and shift a bit field value for use in a register bit range.
|
||||||
\param[in] field Name of the register bit field.
|
\param[in] field Name of the register bit field.
|
||||||
\param[in] value Value of the bit field.
|
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
|
||||||
\return Masked and shifted value.
|
\return Masked and shifted value.
|
||||||
*/
|
*/
|
||||||
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
|
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Mask and shift a register value to extract a bit filed value.
|
\brief Mask and shift a register value to extract a bit filed value.
|
||||||
\param[in] field Name of the register bit field.
|
\param[in] field Name of the register bit field.
|
||||||
\param[in] value Value of register.
|
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
|
||||||
\return Masked and shifted bit field value.
|
\return Masked and shifted bit field value.
|
||||||
*/
|
*/
|
||||||
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
|
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
|
||||||
|
|
||||||
/*@} end of group CMSIS_core_bitfield */
|
/*@} end of group CMSIS_core_bitfield */
|
||||||
|
|
||||||
|
@ -1529,7 +1550,7 @@ typedef struct
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Memory mapping of Cortex-M4 Hardware */
|
/* Memory mapping of Core Hardware */
|
||||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||||
#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
|
#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
|
||||||
#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
|
#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
|
||||||
|
@ -1548,15 +1569,13 @@ typedef struct
|
||||||
#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
|
#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
|
||||||
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
|
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
|
||||||
|
|
||||||
#if (__MPU_PRESENT == 1U)
|
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
|
||||||
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
|
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
|
||||||
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
|
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if (__FPU_PRESENT == 1U)
|
#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
|
||||||
#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
|
#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
|
||||||
#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*@} */
|
/*@} */
|
||||||
|
|
||||||
|
@ -1584,6 +1603,48 @@ typedef struct
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
#ifdef CMSIS_NVIC_VIRTUAL
|
||||||
|
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||||
|
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
||||||
|
#endif
|
||||||
|
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||||
|
#else
|
||||||
|
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
|
||||||
|
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
|
||||||
|
#define NVIC_EnableIRQ __NVIC_EnableIRQ
|
||||||
|
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
||||||
|
#define NVIC_DisableIRQ __NVIC_DisableIRQ
|
||||||
|
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
||||||
|
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
||||||
|
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
||||||
|
#define NVIC_GetActive __NVIC_GetActive
|
||||||
|
#define NVIC_SetPriority __NVIC_SetPriority
|
||||||
|
#define NVIC_GetPriority __NVIC_GetPriority
|
||||||
|
#define NVIC_SystemReset __NVIC_SystemReset
|
||||||
|
#endif /* CMSIS_NVIC_VIRTUAL */
|
||||||
|
|
||||||
|
#ifdef CMSIS_VECTAB_VIRTUAL
|
||||||
|
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||||
|
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
||||||
|
#endif
|
||||||
|
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||||
|
#else
|
||||||
|
#define NVIC_SetVector __NVIC_SetVector
|
||||||
|
#define NVIC_GetVector __NVIC_GetVector
|
||||||
|
#endif /* (CMSIS_VECTAB_VIRTUAL) */
|
||||||
|
|
||||||
|
#define NVIC_USER_IRQ_OFFSET 16
|
||||||
|
|
||||||
|
|
||||||
|
/* The following EXC_RETURN values are saved the LR on exception entry */
|
||||||
|
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
|
||||||
|
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
|
||||||
|
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
|
||||||
|
#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */
|
||||||
|
#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */
|
||||||
|
#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Set Priority Grouping
|
\brief Set Priority Grouping
|
||||||
\details Sets the priority grouping field using the required unlock sequence.
|
\details Sets the priority grouping field using the required unlock sequence.
|
||||||
|
@ -1593,7 +1654,7 @@ typedef struct
|
||||||
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
||||||
\param [in] PriorityGroup Priority grouping field.
|
\param [in] PriorityGroup Priority grouping field.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
||||||
{
|
{
|
||||||
uint32_t reg_value;
|
uint32_t reg_value;
|
||||||
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||||
|
@ -1602,7 +1663,7 @@ __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
||||||
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
|
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
|
||||||
reg_value = (reg_value |
|
reg_value = (reg_value |
|
||||||
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||||||
(PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
|
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
|
||||||
SCB->AIRCR = reg_value;
|
SCB->AIRCR = reg_value;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -1612,121 +1673,178 @@ __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
||||||
\details Reads the priority grouping field from the NVIC Interrupt Controller.
|
\details Reads the priority grouping field from the NVIC Interrupt Controller.
|
||||||
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
|
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
|
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
|
||||||
{
|
{
|
||||||
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
|
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Enable External Interrupt
|
\brief Enable Interrupt
|
||||||
\details Enables a device-specific interrupt in the NVIC interrupt controller.
|
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
||||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Disable External Interrupt
|
\brief Get Interrupt Enable status
|
||||||
\details Disables a device-specific interrupt in the NVIC interrupt controller.
|
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
|
||||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\return 0 Interrupt is not enabled.
|
||||||
|
\return 1 Interrupt is enabled.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return(0U);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Disable Interrupt
|
||||||
|
\details Disables a device specific interrupt in the NVIC interrupt controller.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Get Pending Interrupt
|
\brief Get Pending Interrupt
|
||||||
\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
|
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
|
||||||
\param [in] IRQn Interrupt number.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
\return 0 Interrupt status is not pending.
|
\return 0 Interrupt status is not pending.
|
||||||
\return 1 Interrupt status is pending.
|
\return 1 Interrupt status is pending.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return(0U);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Set Pending Interrupt
|
\brief Set Pending Interrupt
|
||||||
\details Sets the pending bit of an external interrupt.
|
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
|
||||||
\param [in] IRQn Interrupt number. Value cannot be negative.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Clear Pending Interrupt
|
\brief Clear Pending Interrupt
|
||||||
\details Clears the pending bit of an external interrupt.
|
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
|
||||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Get Active Interrupt
|
\brief Get Active Interrupt
|
||||||
\details Reads the active register in NVIC and returns the active bit.
|
\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
|
||||||
\param [in] IRQn Interrupt number.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
\return 0 Interrupt status is not active.
|
\return 0 Interrupt status is not active.
|
||||||
\return 1 Interrupt status is active.
|
\return 1 Interrupt status is active.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
|
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return(0U);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Set Interrupt Priority
|
\brief Set Interrupt Priority
|
||||||
\details Sets the priority of an interrupt.
|
\details Sets the priority of a device specific interrupt or a processor exception.
|
||||||
\note The priority cannot be set for every core interrupt.
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
\param [in] IRQn Interrupt number.
|
\param [in] IRQn Interrupt number.
|
||||||
\param [in] priority Priority to set.
|
\param [in] priority Priority to set.
|
||||||
|
\note The priority cannot be set for every processor exception.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||||
{
|
{
|
||||||
if ((int32_t)(IRQn) < 0)
|
if ((int32_t)(IRQn) >= 0)
|
||||||
{
|
{
|
||||||
SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Get Interrupt Priority
|
\brief Get Interrupt Priority
|
||||||
\details Reads the priority of an interrupt.
|
\details Reads the priority of a device specific interrupt or a processor exception.
|
||||||
The interrupt number can be positive to specify an external (device specific) interrupt,
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
or negative to specify an internal (core) interrupt.
|
or negative to specify a processor exception.
|
||||||
\param [in] IRQn Interrupt number.
|
\param [in] IRQn Interrupt number.
|
||||||
\return Interrupt Priority.
|
\return Interrupt Priority.
|
||||||
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
|
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
|
|
||||||
if ((int32_t)(IRQn) < 0)
|
if ((int32_t)(IRQn) >= 0)
|
||||||
{
|
{
|
||||||
return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
|
return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
|
return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -1783,11 +1901,42 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Interrupt Vector
|
||||||
|
\details Sets an interrupt vector in SRAM based interrupt vector table.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
VTOR must been relocated to SRAM before.
|
||||||
|
\param [in] IRQn Interrupt number
|
||||||
|
\param [in] vector Address of interrupt handler function
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
||||||
|
{
|
||||||
|
uint32_t *vectors = (uint32_t *)SCB->VTOR;
|
||||||
|
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Interrupt Vector
|
||||||
|
\details Reads an interrupt vector from interrupt vector table.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
\param [in] IRQn Interrupt number.
|
||||||
|
\return Address of interrupt handler function
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
uint32_t *vectors = (uint32_t *)SCB->VTOR;
|
||||||
|
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief System Reset
|
\brief System Reset
|
||||||
\details Initiates a system reset request to reset the MCU.
|
\details Initiates a system reset request to reset the MCU.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_SystemReset(void)
|
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
|
||||||
{
|
{
|
||||||
__DSB(); /* Ensure all outstanding memory accesses included
|
__DSB(); /* Ensure all outstanding memory accesses included
|
||||||
buffered write are completed before reset */
|
buffered write are completed before reset */
|
||||||
|
@ -1804,6 +1953,49 @@ __STATIC_INLINE void NVIC_SystemReset(void)
|
||||||
|
|
||||||
/*@} end of CMSIS_Core_NVICFunctions */
|
/*@} end of CMSIS_Core_NVICFunctions */
|
||||||
|
|
||||||
|
/* ########################## MPU functions #################################### */
|
||||||
|
|
||||||
|
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
|
||||||
|
|
||||||
|
#include "mpu_armv7.h"
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/* ########################## FPU functions #################################### */
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_Core_FunctionInterface
|
||||||
|
\defgroup CMSIS_Core_FpuFunctions FPU Functions
|
||||||
|
\brief Function that provides FPU type.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief get FPU type
|
||||||
|
\details returns the FPU type
|
||||||
|
\returns
|
||||||
|
- \b 0: No FPU
|
||||||
|
- \b 1: Single precision FPU
|
||||||
|
- \b 2: Double + Single precision FPU
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
|
||||||
|
{
|
||||||
|
uint32_t mvfr0;
|
||||||
|
|
||||||
|
mvfr0 = FPU->MVFR0;
|
||||||
|
if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
|
||||||
|
{
|
||||||
|
return 1U; /* Single precision FPU */
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return 0U; /* No FPU */
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*@} end of CMSIS_Core_FpuFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/* ################################## SysTick function ############################################ */
|
/* ################################## SysTick function ############################################ */
|
||||||
|
@ -1814,7 +2006,7 @@ __STATIC_INLINE void NVIC_SystemReset(void)
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#if (__Vendor_SysTickConfig == 0U)
|
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief System Tick Configuration
|
\brief System Tick Configuration
|
||||||
|
@ -1857,8 +2049,8 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
|
extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
|
||||||
#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
|
#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -1,87 +0,0 @@
|
||||||
/**************************************************************************//**
|
|
||||||
* @file core_cmFunc.h
|
|
||||||
* @brief CMSIS Cortex-M Core Function Access Header File
|
|
||||||
* @version V4.30
|
|
||||||
* @date 20. October 2015
|
|
||||||
******************************************************************************/
|
|
||||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
|
||||||
|
|
||||||
All rights reserved.
|
|
||||||
Redistribution and use in source and binary forms, with or without
|
|
||||||
modification, are permitted provided that the following conditions are met:
|
|
||||||
- Redistributions of source code must retain the above copyright
|
|
||||||
notice, this list of conditions and the following disclaimer.
|
|
||||||
- Redistributions in binary form must reproduce the above copyright
|
|
||||||
notice, this list of conditions and the following disclaimer in the
|
|
||||||
documentation and/or other materials provided with the distribution.
|
|
||||||
- Neither the name of ARM nor the names of its contributors may be used
|
|
||||||
to endorse or promote products derived from this software without
|
|
||||||
specific prior written permission.
|
|
||||||
*
|
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
|
||||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
|
||||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
|
||||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
||||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
|
||||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
|
||||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
||||||
POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
---------------------------------------------------------------------------*/
|
|
||||||
|
|
||||||
|
|
||||||
#if defined ( __ICCARM__ )
|
|
||||||
#pragma system_include /* treat file as system include file for MISRA check */
|
|
||||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
|
||||||
#pragma clang system_header /* treat file as system include file */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifndef __CORE_CMFUNC_H
|
|
||||||
#define __CORE_CMFUNC_H
|
|
||||||
|
|
||||||
|
|
||||||
/* ########################### Core Function Access ########################### */
|
|
||||||
/** \ingroup CMSIS_Core_FunctionInterface
|
|
||||||
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
|
||||||
@{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*------------------ RealView Compiler -----------------*/
|
|
||||||
#if defined ( __CC_ARM )
|
|
||||||
#include "cmsis_armcc.h"
|
|
||||||
|
|
||||||
/*------------------ ARM Compiler V6 -------------------*/
|
|
||||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
|
||||||
#include "cmsis_armcc_V6.h"
|
|
||||||
|
|
||||||
/*------------------ GNU Compiler ----------------------*/
|
|
||||||
#elif defined ( __GNUC__ )
|
|
||||||
#include "cmsis_gcc.h"
|
|
||||||
|
|
||||||
/*------------------ ICC Compiler ----------------------*/
|
|
||||||
#elif defined ( __ICCARM__ )
|
|
||||||
#include <cmsis_iar.h>
|
|
||||||
|
|
||||||
/*------------------ TI CCS Compiler -------------------*/
|
|
||||||
#elif defined ( __TMS470__ )
|
|
||||||
#include <cmsis_ccs.h>
|
|
||||||
|
|
||||||
/*------------------ TASKING Compiler ------------------*/
|
|
||||||
#elif defined ( __TASKING__ )
|
|
||||||
/*
|
|
||||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
|
||||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
|
||||||
* Including the CMSIS ones.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*------------------ COSMIC Compiler -------------------*/
|
|
||||||
#elif defined ( __CSMC__ )
|
|
||||||
#include <cmsis_csm.h>
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*@} end of CMSIS_Core_RegAccFunctions */
|
|
||||||
|
|
||||||
#endif /* __CORE_CMFUNC_H */
|
|
|
@ -1,87 +0,0 @@
|
||||||
/**************************************************************************//**
|
|
||||||
* @file core_cmInstr.h
|
|
||||||
* @brief CMSIS Cortex-M Core Instruction Access Header File
|
|
||||||
* @version V4.30
|
|
||||||
* @date 20. October 2015
|
|
||||||
******************************************************************************/
|
|
||||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
|
||||||
|
|
||||||
All rights reserved.
|
|
||||||
Redistribution and use in source and binary forms, with or without
|
|
||||||
modification, are permitted provided that the following conditions are met:
|
|
||||||
- Redistributions of source code must retain the above copyright
|
|
||||||
notice, this list of conditions and the following disclaimer.
|
|
||||||
- Redistributions in binary form must reproduce the above copyright
|
|
||||||
notice, this list of conditions and the following disclaimer in the
|
|
||||||
documentation and/or other materials provided with the distribution.
|
|
||||||
- Neither the name of ARM nor the names of its contributors may be used
|
|
||||||
to endorse or promote products derived from this software without
|
|
||||||
specific prior written permission.
|
|
||||||
*
|
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
|
||||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
|
||||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
|
||||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
||||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
|
||||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
|
||||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
||||||
POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
---------------------------------------------------------------------------*/
|
|
||||||
|
|
||||||
|
|
||||||
#if defined ( __ICCARM__ )
|
|
||||||
#pragma system_include /* treat file as system include file for MISRA check */
|
|
||||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
|
||||||
#pragma clang system_header /* treat file as system include file */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifndef __CORE_CMINSTR_H
|
|
||||||
#define __CORE_CMINSTR_H
|
|
||||||
|
|
||||||
|
|
||||||
/* ########################## Core Instruction Access ######################### */
|
|
||||||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
|
||||||
Access to dedicated instructions
|
|
||||||
@{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*------------------ RealView Compiler -----------------*/
|
|
||||||
#if defined ( __CC_ARM )
|
|
||||||
#include "cmsis_armcc.h"
|
|
||||||
|
|
||||||
/*------------------ ARM Compiler V6 -------------------*/
|
|
||||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
|
||||||
#include "cmsis_armcc_V6.h"
|
|
||||||
|
|
||||||
/*------------------ GNU Compiler ----------------------*/
|
|
||||||
#elif defined ( __GNUC__ )
|
|
||||||
#include "cmsis_gcc.h"
|
|
||||||
|
|
||||||
/*------------------ ICC Compiler ----------------------*/
|
|
||||||
#elif defined ( __ICCARM__ )
|
|
||||||
#include <cmsis_iar.h>
|
|
||||||
|
|
||||||
/*------------------ TI CCS Compiler -------------------*/
|
|
||||||
#elif defined ( __TMS470__ )
|
|
||||||
#include <cmsis_ccs.h>
|
|
||||||
|
|
||||||
/*------------------ TASKING Compiler ------------------*/
|
|
||||||
#elif defined ( __TASKING__ )
|
|
||||||
/*
|
|
||||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
|
||||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
|
||||||
* Including the CMSIS ones.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*------------------ COSMIC Compiler -------------------*/
|
|
||||||
#elif defined ( __CSMC__ )
|
|
||||||
#include <cmsis_csm.h>
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
|
||||||
|
|
||||||
#endif /* __CORE_CMINSTR_H */
|
|
|
@ -1,96 +0,0 @@
|
||||||
/**************************************************************************//**
|
|
||||||
* @file core_cmSimd.h
|
|
||||||
* @brief CMSIS Cortex-M SIMD Header File
|
|
||||||
* @version V4.30
|
|
||||||
* @date 20. October 2015
|
|
||||||
******************************************************************************/
|
|
||||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
|
||||||
|
|
||||||
All rights reserved.
|
|
||||||
Redistribution and use in source and binary forms, with or without
|
|
||||||
modification, are permitted provided that the following conditions are met:
|
|
||||||
- Redistributions of source code must retain the above copyright
|
|
||||||
notice, this list of conditions and the following disclaimer.
|
|
||||||
- Redistributions in binary form must reproduce the above copyright
|
|
||||||
notice, this list of conditions and the following disclaimer in the
|
|
||||||
documentation and/or other materials provided with the distribution.
|
|
||||||
- Neither the name of ARM nor the names of its contributors may be used
|
|
||||||
to endorse or promote products derived from this software without
|
|
||||||
specific prior written permission.
|
|
||||||
*
|
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
|
||||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
|
||||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
|
||||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
||||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
|
||||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
|
||||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
||||||
POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
---------------------------------------------------------------------------*/
|
|
||||||
|
|
||||||
|
|
||||||
#if defined ( __ICCARM__ )
|
|
||||||
#pragma system_include /* treat file as system include file for MISRA check */
|
|
||||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
|
||||||
#pragma clang system_header /* treat file as system include file */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifndef __CORE_CMSIMD_H
|
|
||||||
#define __CORE_CMSIMD_H
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
|
|
||||||
/* ################### Compiler specific Intrinsics ########################### */
|
|
||||||
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
|
||||||
Access to dedicated SIMD instructions
|
|
||||||
@{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*------------------ RealView Compiler -----------------*/
|
|
||||||
#if defined ( __CC_ARM )
|
|
||||||
#include "cmsis_armcc.h"
|
|
||||||
|
|
||||||
/*------------------ ARM Compiler V6 -------------------*/
|
|
||||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
|
||||||
#include "cmsis_armcc_V6.h"
|
|
||||||
|
|
||||||
/*------------------ GNU Compiler ----------------------*/
|
|
||||||
#elif defined ( __GNUC__ )
|
|
||||||
#include "cmsis_gcc.h"
|
|
||||||
|
|
||||||
/*------------------ ICC Compiler ----------------------*/
|
|
||||||
#elif defined ( __ICCARM__ )
|
|
||||||
#include <cmsis_iar.h>
|
|
||||||
|
|
||||||
/*------------------ TI CCS Compiler -------------------*/
|
|
||||||
#elif defined ( __TMS470__ )
|
|
||||||
#include <cmsis_ccs.h>
|
|
||||||
|
|
||||||
/*------------------ TASKING Compiler ------------------*/
|
|
||||||
#elif defined ( __TASKING__ )
|
|
||||||
/*
|
|
||||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
|
||||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
|
||||||
* Including the CMSIS ones.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*------------------ COSMIC Compiler -------------------*/
|
|
||||||
#elif defined ( __CSMC__ )
|
|
||||||
#include <cmsis_csm.h>
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*@} end of group CMSIS_SIMD_intrinsics */
|
|
||||||
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* __CORE_CMSIMD_H */
|
|
|
@ -1,40 +1,30 @@
|
||||||
/**************************************************************************//**
|
/**************************************************************************//**
|
||||||
* @file core_sc000.h
|
* @file core_sc000.h
|
||||||
* @brief CMSIS SC000 Core Peripheral Access Layer Header File
|
* @brief CMSIS SC000 Core Peripheral Access Layer Header File
|
||||||
* @version V4.30
|
* @version V5.0.5
|
||||||
* @date 20. October 2015
|
* @date 28. May 2018
|
||||||
******************************************************************************/
|
******************************************************************************/
|
||||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
/*
|
||||||
|
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||||
All rights reserved.
|
*
|
||||||
Redistribution and use in source and binary forms, with or without
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
modification, are permitted provided that the following conditions are met:
|
*
|
||||||
- Redistributions of source code must retain the above copyright
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
notice, this list of conditions and the following disclaimer.
|
* not use this file except in compliance with the License.
|
||||||
- Redistributions in binary form must reproduce the above copyright
|
* You may obtain a copy of the License at
|
||||||
notice, this list of conditions and the following disclaimer in the
|
*
|
||||||
documentation and/or other materials provided with the distribution.
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
- Neither the name of ARM nor the names of its contributors may be used
|
*
|
||||||
to endorse or promote products derived from this software without
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
specific prior written permission.
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
*
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
* See the License for the specific language governing permissions and
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
* limitations under the License.
|
||||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
*/
|
||||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
|
||||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
|
||||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
||||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
|
||||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
|
||||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
||||||
POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
---------------------------------------------------------------------------*/
|
|
||||||
|
|
||||||
|
|
||||||
#if defined ( __ICCARM__ )
|
#if defined ( __ICCARM__ )
|
||||||
#pragma system_include /* treat file as system include file for MISRA check */
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
#elif defined (__clang__)
|
||||||
#pragma clang system_header /* treat file as system include file */
|
#pragma clang system_header /* treat file as system include file */
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
@ -70,53 +60,15 @@
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
#include "cmsis_version.h"
|
||||||
|
|
||||||
/* CMSIS SC000 definitions */
|
/* CMSIS SC000 definitions */
|
||||||
#define __SC000_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
|
#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
|
||||||
#define __SC000_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
|
#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
|
||||||
#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
|
#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
|
||||||
__SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
|
__SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
|
||||||
|
|
||||||
#define __CORTEX_SC (000U) /*!< Cortex secure core */
|
#define __CORTEX_SC (000U) /*!< Cortex secure core */
|
||||||
|
|
||||||
|
|
||||||
#if defined ( __CC_ARM )
|
|
||||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
|
||||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
|
||||||
#define __STATIC_INLINE static __inline
|
|
||||||
|
|
||||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
|
||||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
|
||||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
|
||||||
#define __STATIC_INLINE static __inline
|
|
||||||
|
|
||||||
#elif defined ( __GNUC__ )
|
|
||||||
#define __ASM __asm /*!< asm keyword for GNU Compiler */
|
|
||||||
#define __INLINE inline /*!< inline keyword for GNU Compiler */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#elif defined ( __ICCARM__ )
|
|
||||||
#define __ASM __asm /*!< asm keyword for IAR Compiler */
|
|
||||||
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#elif defined ( __TMS470__ )
|
|
||||||
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#elif defined ( __TASKING__ )
|
|
||||||
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
|
|
||||||
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#elif defined ( __CSMC__ )
|
|
||||||
#define __packed
|
|
||||||
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
|
|
||||||
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#else
|
|
||||||
#error Unknown compiler
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/** __FPU_USED indicates whether an FPU is used or not.
|
/** __FPU_USED indicates whether an FPU is used or not.
|
||||||
This core does not support an FPU at all
|
This core does not support an FPU at all
|
||||||
|
@ -128,7 +80,7 @@
|
||||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||||
#if defined __ARM_PCS_VFP
|
#if defined __ARM_PCS_VFP
|
||||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
#endif
|
#endif
|
||||||
|
@ -143,7 +95,7 @@
|
||||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#elif defined ( __TMS470__ )
|
#elif defined ( __TI_ARM__ )
|
||||||
#if defined __TI_VFP_SUPPORT__
|
#if defined __TI_VFP_SUPPORT__
|
||||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
#endif
|
#endif
|
||||||
|
@ -160,8 +112,8 @@
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#include "core_cmInstr.h" /* Core Instruction Access */
|
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
|
||||||
#include "core_cmFunc.h" /* Core Function Access */
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
}
|
}
|
||||||
|
@ -569,7 +521,7 @@ typedef struct
|
||||||
|
|
||||||
/*@} end of group CMSIS_SysTick */
|
/*@} end of group CMSIS_SysTick */
|
||||||
|
|
||||||
#if (__MPU_PRESENT == 1U)
|
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
|
||||||
/**
|
/**
|
||||||
\ingroup CMSIS_core_register
|
\ingroup CMSIS_core_register
|
||||||
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
|
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
|
||||||
|
@ -678,18 +630,18 @@ typedef struct
|
||||||
/**
|
/**
|
||||||
\brief Mask and shift a bit field value for use in a register bit range.
|
\brief Mask and shift a bit field value for use in a register bit range.
|
||||||
\param[in] field Name of the register bit field.
|
\param[in] field Name of the register bit field.
|
||||||
\param[in] value Value of the bit field.
|
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
|
||||||
\return Masked and shifted value.
|
\return Masked and shifted value.
|
||||||
*/
|
*/
|
||||||
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
|
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Mask and shift a register value to extract a bit filed value.
|
\brief Mask and shift a register value to extract a bit filed value.
|
||||||
\param[in] field Name of the register bit field.
|
\param[in] field Name of the register bit field.
|
||||||
\param[in] value Value of register.
|
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
|
||||||
\return Masked and shifted bit field value.
|
\return Masked and shifted bit field value.
|
||||||
*/
|
*/
|
||||||
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
|
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
|
||||||
|
|
||||||
/*@} end of group CMSIS_core_bitfield */
|
/*@} end of group CMSIS_core_bitfield */
|
||||||
|
|
||||||
|
@ -701,7 +653,7 @@ typedef struct
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Memory mapping of SC000 Hardware */
|
/* Memory mapping of Core Hardware */
|
||||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||||
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||||||
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||||||
|
@ -712,7 +664,7 @@ typedef struct
|
||||||
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
||||||
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
||||||
|
|
||||||
#if (__MPU_PRESENT == 1U)
|
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
|
||||||
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
|
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
|
||||||
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
|
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
|
||||||
#endif
|
#endif
|
||||||
|
@ -742,7 +694,46 @@ typedef struct
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Interrupt Priorities are WORD accessible only under ARMv6M */
|
#ifdef CMSIS_NVIC_VIRTUAL
|
||||||
|
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||||
|
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
||||||
|
#endif
|
||||||
|
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||||
|
#else
|
||||||
|
/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */
|
||||||
|
/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */
|
||||||
|
#define NVIC_EnableIRQ __NVIC_EnableIRQ
|
||||||
|
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
||||||
|
#define NVIC_DisableIRQ __NVIC_DisableIRQ
|
||||||
|
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
||||||
|
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
||||||
|
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
||||||
|
/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */
|
||||||
|
#define NVIC_SetPriority __NVIC_SetPriority
|
||||||
|
#define NVIC_GetPriority __NVIC_GetPriority
|
||||||
|
#define NVIC_SystemReset __NVIC_SystemReset
|
||||||
|
#endif /* CMSIS_NVIC_VIRTUAL */
|
||||||
|
|
||||||
|
#ifdef CMSIS_VECTAB_VIRTUAL
|
||||||
|
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||||
|
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
||||||
|
#endif
|
||||||
|
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||||
|
#else
|
||||||
|
#define NVIC_SetVector __NVIC_SetVector
|
||||||
|
#define NVIC_GetVector __NVIC_GetVector
|
||||||
|
#endif /* (CMSIS_VECTAB_VIRTUAL) */
|
||||||
|
|
||||||
|
#define NVIC_USER_IRQ_OFFSET 16
|
||||||
|
|
||||||
|
|
||||||
|
/* The following EXC_RETURN values are saved the LR on exception entry */
|
||||||
|
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
|
||||||
|
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
|
||||||
|
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
|
||||||
|
|
||||||
|
|
||||||
|
/* Interrupt Priorities are WORD accessible only under Armv6-M */
|
||||||
/* The following MACROS handle generation of the register offset and byte masks */
|
/* The following MACROS handle generation of the register offset and byte masks */
|
||||||
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
|
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
|
||||||
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
|
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
|
||||||
|
@ -750,79 +741,128 @@ typedef struct
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Enable External Interrupt
|
\brief Enable Interrupt
|
||||||
\details Enables a device-specific interrupt in the NVIC interrupt controller.
|
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
||||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Disable External Interrupt
|
\brief Get Interrupt Enable status
|
||||||
\details Disables a device-specific interrupt in the NVIC interrupt controller.
|
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
|
||||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\return 0 Interrupt is not enabled.
|
||||||
|
\return 1 Interrupt is enabled.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return(0U);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Disable Interrupt
|
||||||
|
\details Disables a device specific interrupt in the NVIC interrupt controller.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Get Pending Interrupt
|
\brief Get Pending Interrupt
|
||||||
\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
|
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
|
||||||
\param [in] IRQn Interrupt number.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
\return 0 Interrupt status is not pending.
|
\return 0 Interrupt status is not pending.
|
||||||
\return 1 Interrupt status is pending.
|
\return 1 Interrupt status is pending.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return(0U);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Set Pending Interrupt
|
\brief Set Pending Interrupt
|
||||||
\details Sets the pending bit of an external interrupt.
|
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
|
||||||
\param [in] IRQn Interrupt number. Value cannot be negative.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Clear Pending Interrupt
|
\brief Clear Pending Interrupt
|
||||||
\details Clears the pending bit of an external interrupt.
|
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
|
||||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Set Interrupt Priority
|
\brief Set Interrupt Priority
|
||||||
\details Sets the priority of an interrupt.
|
\details Sets the priority of a device specific interrupt or a processor exception.
|
||||||
\note The priority cannot be set for every core interrupt.
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
\param [in] IRQn Interrupt number.
|
\param [in] IRQn Interrupt number.
|
||||||
\param [in] priority Priority to set.
|
\param [in] priority Priority to set.
|
||||||
|
\note The priority cannot be set for every processor exception.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||||
{
|
{
|
||||||
if ((int32_t)(IRQn) < 0)
|
if ((int32_t)(IRQn) >= 0)
|
||||||
{
|
{
|
||||||
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -830,24 +870,55 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Get Interrupt Priority
|
\brief Get Interrupt Priority
|
||||||
\details Reads the priority of an interrupt.
|
\details Reads the priority of a device specific interrupt or a processor exception.
|
||||||
The interrupt number can be positive to specify an external (device specific) interrupt,
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
or negative to specify an internal (core) interrupt.
|
or negative to specify a processor exception.
|
||||||
\param [in] IRQn Interrupt number.
|
\param [in] IRQn Interrupt number.
|
||||||
\return Interrupt Priority.
|
\return Interrupt Priority.
|
||||||
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
|
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
|
|
||||||
if ((int32_t)(IRQn) < 0)
|
if ((int32_t)(IRQn) >= 0)
|
||||||
{
|
|
||||||
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
{
|
||||||
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||||
}
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Interrupt Vector
|
||||||
|
\details Sets an interrupt vector in SRAM based interrupt vector table.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
VTOR must been relocated to SRAM before.
|
||||||
|
\param [in] IRQn Interrupt number
|
||||||
|
\param [in] vector Address of interrupt handler function
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
||||||
|
{
|
||||||
|
uint32_t *vectors = (uint32_t *)SCB->VTOR;
|
||||||
|
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Interrupt Vector
|
||||||
|
\details Reads an interrupt vector from interrupt vector table.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
\param [in] IRQn Interrupt number.
|
||||||
|
\return Address of interrupt handler function
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
uint32_t *vectors = (uint32_t *)SCB->VTOR;
|
||||||
|
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
@ -855,7 +926,7 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
|
||||||
\brief System Reset
|
\brief System Reset
|
||||||
\details Initiates a system reset request to reset the MCU.
|
\details Initiates a system reset request to reset the MCU.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_SystemReset(void)
|
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
|
||||||
{
|
{
|
||||||
__DSB(); /* Ensure all outstanding memory accesses included
|
__DSB(); /* Ensure all outstanding memory accesses included
|
||||||
buffered write are completed before reset */
|
buffered write are completed before reset */
|
||||||
|
@ -872,6 +943,31 @@ __STATIC_INLINE void NVIC_SystemReset(void)
|
||||||
/*@} end of CMSIS_Core_NVICFunctions */
|
/*@} end of CMSIS_Core_NVICFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
/* ########################## FPU functions #################################### */
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_Core_FunctionInterface
|
||||||
|
\defgroup CMSIS_Core_FpuFunctions FPU Functions
|
||||||
|
\brief Function that provides FPU type.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief get FPU type
|
||||||
|
\details returns the FPU type
|
||||||
|
\returns
|
||||||
|
- \b 0: No FPU
|
||||||
|
- \b 1: Single precision FPU
|
||||||
|
- \b 2: Double + Single precision FPU
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
|
||||||
|
{
|
||||||
|
return 0U; /* No FPU */
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*@} end of CMSIS_Core_FpuFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/* ################################## SysTick function ############################################ */
|
/* ################################## SysTick function ############################################ */
|
||||||
/**
|
/**
|
||||||
|
@ -881,7 +977,7 @@ __STATIC_INLINE void NVIC_SystemReset(void)
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#if (__Vendor_SysTickConfig == 0U)
|
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief System Tick Configuration
|
\brief System Tick Configuration
|
||||||
|
|
|
@ -1,40 +1,30 @@
|
||||||
/**************************************************************************//**
|
/**************************************************************************//**
|
||||||
* @file core_sc300.h
|
* @file core_sc300.h
|
||||||
* @brief CMSIS SC300 Core Peripheral Access Layer Header File
|
* @brief CMSIS SC300 Core Peripheral Access Layer Header File
|
||||||
* @version V4.30
|
* @version V5.0.6
|
||||||
* @date 20. October 2015
|
* @date 04. June 2018
|
||||||
******************************************************************************/
|
******************************************************************************/
|
||||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
/*
|
||||||
|
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||||
All rights reserved.
|
*
|
||||||
Redistribution and use in source and binary forms, with or without
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
modification, are permitted provided that the following conditions are met:
|
*
|
||||||
- Redistributions of source code must retain the above copyright
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
notice, this list of conditions and the following disclaimer.
|
* not use this file except in compliance with the License.
|
||||||
- Redistributions in binary form must reproduce the above copyright
|
* You may obtain a copy of the License at
|
||||||
notice, this list of conditions and the following disclaimer in the
|
*
|
||||||
documentation and/or other materials provided with the distribution.
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
- Neither the name of ARM nor the names of its contributors may be used
|
*
|
||||||
to endorse or promote products derived from this software without
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
specific prior written permission.
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
*
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
* See the License for the specific language governing permissions and
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
* limitations under the License.
|
||||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
*/
|
||||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
|
||||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
|
||||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
||||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
|
||||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
|
||||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
||||||
POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
---------------------------------------------------------------------------*/
|
|
||||||
|
|
||||||
|
|
||||||
#if defined ( __ICCARM__ )
|
#if defined ( __ICCARM__ )
|
||||||
#pragma system_include /* treat file as system include file for MISRA check */
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
#elif defined (__clang__)
|
||||||
#pragma clang system_header /* treat file as system include file */
|
#pragma clang system_header /* treat file as system include file */
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
@ -70,53 +60,15 @@
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
#include "cmsis_version.h"
|
||||||
|
|
||||||
/* CMSIS SC300 definitions */
|
/* CMSIS SC300 definitions */
|
||||||
#define __SC300_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
|
#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
|
||||||
#define __SC300_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
|
#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
|
||||||
#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
|
#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
|
||||||
__SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
|
__SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
|
||||||
|
|
||||||
#define __CORTEX_SC (300U) /*!< Cortex secure core */
|
#define __CORTEX_SC (300U) /*!< Cortex secure core */
|
||||||
|
|
||||||
|
|
||||||
#if defined ( __CC_ARM )
|
|
||||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
|
||||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
|
||||||
#define __STATIC_INLINE static __inline
|
|
||||||
|
|
||||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
|
||||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
|
||||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
|
||||||
#define __STATIC_INLINE static __inline
|
|
||||||
|
|
||||||
#elif defined ( __GNUC__ )
|
|
||||||
#define __ASM __asm /*!< asm keyword for GNU Compiler */
|
|
||||||
#define __INLINE inline /*!< inline keyword for GNU Compiler */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#elif defined ( __ICCARM__ )
|
|
||||||
#define __ASM __asm /*!< asm keyword for IAR Compiler */
|
|
||||||
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#elif defined ( __TMS470__ )
|
|
||||||
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#elif defined ( __TASKING__ )
|
|
||||||
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
|
|
||||||
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#elif defined ( __CSMC__ )
|
|
||||||
#define __packed
|
|
||||||
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
|
|
||||||
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
|
|
||||||
#define __STATIC_INLINE static inline
|
|
||||||
|
|
||||||
#else
|
|
||||||
#error Unknown compiler
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/** __FPU_USED indicates whether an FPU is used or not.
|
/** __FPU_USED indicates whether an FPU is used or not.
|
||||||
This core does not support an FPU at all
|
This core does not support an FPU at all
|
||||||
|
@ -128,7 +80,7 @@
|
||||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||||
#if defined __ARM_PCS_VFP
|
#if defined __ARM_PCS_VFP
|
||||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
#endif
|
#endif
|
||||||
|
@ -143,7 +95,7 @@
|
||||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#elif defined ( __TMS470__ )
|
#elif defined ( __TI_ARM__ )
|
||||||
#if defined __TI_VFP_SUPPORT__
|
#if defined __TI_VFP_SUPPORT__
|
||||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||||
#endif
|
#endif
|
||||||
|
@ -160,8 +112,8 @@
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#include "core_cmInstr.h" /* Core Instruction Access */
|
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
|
||||||
#include "core_cmFunc.h" /* Core Function Access */
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
}
|
}
|
||||||
|
@ -191,7 +143,7 @@
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifndef __NVIC_PRIO_BITS
|
#ifndef __NVIC_PRIO_BITS
|
||||||
#define __NVIC_PRIO_BITS 4U
|
#define __NVIC_PRIO_BITS 3U
|
||||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
@ -308,9 +260,11 @@ typedef union
|
||||||
struct
|
struct
|
||||||
{
|
{
|
||||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||||
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
|
uint32_t _reserved0:1; /*!< bit: 9 Reserved */
|
||||||
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
|
uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
|
||||||
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
|
uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */
|
||||||
|
uint32_t T:1; /*!< bit: 24 Thumb bit */
|
||||||
|
uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
|
||||||
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
|
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
|
||||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||||
|
@ -336,12 +290,15 @@ typedef union
|
||||||
#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
|
#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
|
||||||
#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
|
#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
|
||||||
|
|
||||||
#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
|
#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
|
||||||
#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
|
#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
|
||||||
|
|
||||||
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
|
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
|
||||||
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
|
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
|
||||||
|
|
||||||
|
#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
|
||||||
|
#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
|
||||||
|
|
||||||
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
|
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
|
||||||
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
|
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
|
||||||
|
|
||||||
|
@ -599,6 +556,60 @@ typedef struct
|
||||||
#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
|
#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
|
||||||
#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
|
#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
|
||||||
|
|
||||||
|
/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
|
||||||
|
#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
|
||||||
|
#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
|
||||||
|
#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
|
||||||
|
#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
|
||||||
|
#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
|
||||||
|
#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
|
||||||
|
|
||||||
|
/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
|
||||||
|
#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
|
||||||
|
#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
|
||||||
|
#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
|
||||||
|
#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
|
||||||
|
#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
|
||||||
|
#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
|
||||||
|
#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
|
||||||
|
|
||||||
|
/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
|
||||||
|
#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
|
||||||
|
#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
|
||||||
|
#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
|
||||||
|
#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
|
||||||
|
#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
|
||||||
|
#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
|
||||||
|
|
||||||
|
#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
|
||||||
|
#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
|
||||||
|
|
||||||
/* SCB Hard Fault Status Register Definitions */
|
/* SCB Hard Fault Status Register Definitions */
|
||||||
#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
|
#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
|
||||||
#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
|
#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
|
||||||
|
@ -966,7 +977,7 @@ typedef struct
|
||||||
*/
|
*/
|
||||||
typedef struct
|
typedef struct
|
||||||
{
|
{
|
||||||
__IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
|
__IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
|
||||||
__IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
|
__IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
|
||||||
uint32_t RESERVED0[2U];
|
uint32_t RESERVED0[2U];
|
||||||
__IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
|
__IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
|
||||||
|
@ -977,7 +988,7 @@ typedef struct
|
||||||
__IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
|
__IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
|
||||||
__IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
|
__IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
|
||||||
uint32_t RESERVED3[759U];
|
uint32_t RESERVED3[759U];
|
||||||
__IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
|
__IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
|
||||||
__IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
|
__IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
|
||||||
__IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
|
__IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
|
||||||
uint32_t RESERVED4[1U];
|
uint32_t RESERVED4[1U];
|
||||||
|
@ -1047,8 +1058,11 @@ typedef struct
|
||||||
#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
|
#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
|
||||||
|
|
||||||
/* TPI ITATBCTR2 Register Definitions */
|
/* TPI ITATBCTR2 Register Definitions */
|
||||||
#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
|
#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
|
||||||
#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
|
#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
|
||||||
|
|
||||||
|
#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
|
||||||
|
#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
|
||||||
|
|
||||||
/* TPI Integration ITM Data Register Definitions (FIFO1) */
|
/* TPI Integration ITM Data Register Definitions (FIFO1) */
|
||||||
#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
|
#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
|
||||||
|
@ -1073,12 +1087,15 @@ typedef struct
|
||||||
#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
|
#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
|
||||||
|
|
||||||
/* TPI ITATBCTR0 Register Definitions */
|
/* TPI ITATBCTR0 Register Definitions */
|
||||||
#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
|
#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
|
||||||
#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
|
#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
|
||||||
|
|
||||||
|
#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
|
||||||
|
#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
|
||||||
|
|
||||||
/* TPI Integration Mode Control Register Definitions */
|
/* TPI Integration Mode Control Register Definitions */
|
||||||
#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
|
#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
|
||||||
#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
|
#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
|
||||||
|
|
||||||
/* TPI DEVID Register Definitions */
|
/* TPI DEVID Register Definitions */
|
||||||
#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
|
#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
|
||||||
|
@ -1100,16 +1117,16 @@ typedef struct
|
||||||
#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
|
#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
|
||||||
|
|
||||||
/* TPI DEVTYPE Register Definitions */
|
/* TPI DEVTYPE Register Definitions */
|
||||||
#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
|
#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
|
||||||
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
|
|
||||||
|
|
||||||
#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
|
|
||||||
#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
|
#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
|
||||||
|
|
||||||
|
#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
|
||||||
|
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
|
||||||
|
|
||||||
/*@}*/ /* end of group CMSIS_TPI */
|
/*@}*/ /* end of group CMSIS_TPI */
|
||||||
|
|
||||||
|
|
||||||
#if (__MPU_PRESENT == 1U)
|
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
|
||||||
/**
|
/**
|
||||||
\ingroup CMSIS_core_register
|
\ingroup CMSIS_core_register
|
||||||
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
|
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
|
||||||
|
@ -1319,18 +1336,18 @@ typedef struct
|
||||||
/**
|
/**
|
||||||
\brief Mask and shift a bit field value for use in a register bit range.
|
\brief Mask and shift a bit field value for use in a register bit range.
|
||||||
\param[in] field Name of the register bit field.
|
\param[in] field Name of the register bit field.
|
||||||
\param[in] value Value of the bit field.
|
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
|
||||||
\return Masked and shifted value.
|
\return Masked and shifted value.
|
||||||
*/
|
*/
|
||||||
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
|
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Mask and shift a register value to extract a bit filed value.
|
\brief Mask and shift a register value to extract a bit filed value.
|
||||||
\param[in] field Name of the register bit field.
|
\param[in] field Name of the register bit field.
|
||||||
\param[in] value Value of register.
|
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
|
||||||
\return Masked and shifted bit field value.
|
\return Masked and shifted bit field value.
|
||||||
*/
|
*/
|
||||||
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
|
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
|
||||||
|
|
||||||
/*@} end of group CMSIS_core_bitfield */
|
/*@} end of group CMSIS_core_bitfield */
|
||||||
|
|
||||||
|
@ -1342,7 +1359,7 @@ typedef struct
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Memory mapping of Cortex-M3 Hardware */
|
/* Memory mapping of Core Hardware */
|
||||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||||
#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
|
#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
|
||||||
#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
|
#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
|
||||||
|
@ -1361,7 +1378,7 @@ typedef struct
|
||||||
#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
|
#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
|
||||||
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
|
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
|
||||||
|
|
||||||
#if (__MPU_PRESENT == 1U)
|
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
|
||||||
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
|
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
|
||||||
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
|
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
|
||||||
#endif
|
#endif
|
||||||
|
@ -1392,6 +1409,46 @@ typedef struct
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
#ifdef CMSIS_NVIC_VIRTUAL
|
||||||
|
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||||
|
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
||||||
|
#endif
|
||||||
|
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||||
|
#else
|
||||||
|
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
|
||||||
|
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
|
||||||
|
#define NVIC_EnableIRQ __NVIC_EnableIRQ
|
||||||
|
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
||||||
|
#define NVIC_DisableIRQ __NVIC_DisableIRQ
|
||||||
|
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
||||||
|
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
||||||
|
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
||||||
|
#define NVIC_GetActive __NVIC_GetActive
|
||||||
|
#define NVIC_SetPriority __NVIC_SetPriority
|
||||||
|
#define NVIC_GetPriority __NVIC_GetPriority
|
||||||
|
#define NVIC_SystemReset __NVIC_SystemReset
|
||||||
|
#endif /* CMSIS_NVIC_VIRTUAL */
|
||||||
|
|
||||||
|
#ifdef CMSIS_VECTAB_VIRTUAL
|
||||||
|
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||||
|
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
||||||
|
#endif
|
||||||
|
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||||
|
#else
|
||||||
|
#define NVIC_SetVector __NVIC_SetVector
|
||||||
|
#define NVIC_GetVector __NVIC_GetVector
|
||||||
|
#endif /* (CMSIS_VECTAB_VIRTUAL) */
|
||||||
|
|
||||||
|
#define NVIC_USER_IRQ_OFFSET 16
|
||||||
|
|
||||||
|
|
||||||
|
/* The following EXC_RETURN values are saved the LR on exception entry */
|
||||||
|
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
|
||||||
|
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
|
||||||
|
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Set Priority Grouping
|
\brief Set Priority Grouping
|
||||||
\details Sets the priority grouping field using the required unlock sequence.
|
\details Sets the priority grouping field using the required unlock sequence.
|
||||||
|
@ -1401,7 +1458,7 @@ typedef struct
|
||||||
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
||||||
\param [in] PriorityGroup Priority grouping field.
|
\param [in] PriorityGroup Priority grouping field.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
||||||
{
|
{
|
||||||
uint32_t reg_value;
|
uint32_t reg_value;
|
||||||
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||||
|
@ -1420,121 +1477,178 @@ __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
||||||
\details Reads the priority grouping field from the NVIC Interrupt Controller.
|
\details Reads the priority grouping field from the NVIC Interrupt Controller.
|
||||||
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
|
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
|
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
|
||||||
{
|
{
|
||||||
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
|
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Enable External Interrupt
|
\brief Enable Interrupt
|
||||||
\details Enables a device-specific interrupt in the NVIC interrupt controller.
|
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
||||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Disable External Interrupt
|
\brief Get Interrupt Enable status
|
||||||
\details Disables a device-specific interrupt in the NVIC interrupt controller.
|
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
|
||||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\return 0 Interrupt is not enabled.
|
||||||
|
\return 1 Interrupt is enabled.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return(0U);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Disable Interrupt
|
||||||
|
\details Disables a device specific interrupt in the NVIC interrupt controller.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Get Pending Interrupt
|
\brief Get Pending Interrupt
|
||||||
\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
|
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
|
||||||
\param [in] IRQn Interrupt number.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
\return 0 Interrupt status is not pending.
|
\return 0 Interrupt status is not pending.
|
||||||
\return 1 Interrupt status is pending.
|
\return 1 Interrupt status is pending.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return(0U);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Set Pending Interrupt
|
\brief Set Pending Interrupt
|
||||||
\details Sets the pending bit of an external interrupt.
|
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
|
||||||
\param [in] IRQn Interrupt number. Value cannot be negative.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Clear Pending Interrupt
|
\brief Clear Pending Interrupt
|
||||||
\details Clears the pending bit of an external interrupt.
|
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
|
||||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Get Active Interrupt
|
\brief Get Active Interrupt
|
||||||
\details Reads the active register in NVIC and returns the active bit.
|
\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
|
||||||
\param [in] IRQn Interrupt number.
|
\param [in] IRQn Device specific interrupt number.
|
||||||
\return 0 Interrupt status is not active.
|
\return 0 Interrupt status is not active.
|
||||||
\return 1 Interrupt status is active.
|
\return 1 Interrupt status is active.
|
||||||
|
\note IRQn must not be negative.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
|
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return(0U);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Set Interrupt Priority
|
\brief Set Interrupt Priority
|
||||||
\details Sets the priority of an interrupt.
|
\details Sets the priority of a device specific interrupt or a processor exception.
|
||||||
\note The priority cannot be set for every core interrupt.
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
\param [in] IRQn Interrupt number.
|
\param [in] IRQn Interrupt number.
|
||||||
\param [in] priority Priority to set.
|
\param [in] priority Priority to set.
|
||||||
|
\note The priority cannot be set for every processor exception.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||||
{
|
{
|
||||||
if ((int32_t)(IRQn) < 0)
|
if ((int32_t)(IRQn) >= 0)
|
||||||
{
|
{
|
||||||
SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Get Interrupt Priority
|
\brief Get Interrupt Priority
|
||||||
\details Reads the priority of an interrupt.
|
\details Reads the priority of a device specific interrupt or a processor exception.
|
||||||
The interrupt number can be positive to specify an external (device specific) interrupt,
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
or negative to specify an internal (core) interrupt.
|
or negative to specify a processor exception.
|
||||||
\param [in] IRQn Interrupt number.
|
\param [in] IRQn Interrupt number.
|
||||||
\return Interrupt Priority.
|
\return Interrupt Priority.
|
||||||
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
|
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
||||||
{
|
{
|
||||||
|
|
||||||
if ((int32_t)(IRQn) < 0)
|
if ((int32_t)(IRQn) >= 0)
|
||||||
{
|
{
|
||||||
return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
|
return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
|
return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -1591,11 +1705,42 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Interrupt Vector
|
||||||
|
\details Sets an interrupt vector in SRAM based interrupt vector table.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
VTOR must been relocated to SRAM before.
|
||||||
|
\param [in] IRQn Interrupt number
|
||||||
|
\param [in] vector Address of interrupt handler function
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
||||||
|
{
|
||||||
|
uint32_t *vectors = (uint32_t *)SCB->VTOR;
|
||||||
|
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Interrupt Vector
|
||||||
|
\details Reads an interrupt vector from interrupt vector table.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
\param [in] IRQn Interrupt number.
|
||||||
|
\return Address of interrupt handler function
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
uint32_t *vectors = (uint32_t *)SCB->VTOR;
|
||||||
|
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief System Reset
|
\brief System Reset
|
||||||
\details Initiates a system reset request to reset the MCU.
|
\details Initiates a system reset request to reset the MCU.
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void NVIC_SystemReset(void)
|
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
|
||||||
{
|
{
|
||||||
__DSB(); /* Ensure all outstanding memory accesses included
|
__DSB(); /* Ensure all outstanding memory accesses included
|
||||||
buffered write are completed before reset */
|
buffered write are completed before reset */
|
||||||
|
@ -1613,6 +1758,31 @@ __STATIC_INLINE void NVIC_SystemReset(void)
|
||||||
/*@} end of CMSIS_Core_NVICFunctions */
|
/*@} end of CMSIS_Core_NVICFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
/* ########################## FPU functions #################################### */
|
||||||
|
/**
|
||||||
|
\ingroup CMSIS_Core_FunctionInterface
|
||||||
|
\defgroup CMSIS_Core_FpuFunctions FPU Functions
|
||||||
|
\brief Function that provides FPU type.
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief get FPU type
|
||||||
|
\details returns the FPU type
|
||||||
|
\returns
|
||||||
|
- \b 0: No FPU
|
||||||
|
- \b 1: Single precision FPU
|
||||||
|
- \b 2: Double + Single precision FPU
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
|
||||||
|
{
|
||||||
|
return 0U; /* No FPU */
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*@} end of CMSIS_Core_FpuFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/* ################################## SysTick function ############################################ */
|
/* ################################## SysTick function ############################################ */
|
||||||
/**
|
/**
|
||||||
|
@ -1622,7 +1792,7 @@ __STATIC_INLINE void NVIC_SystemReset(void)
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#if (__Vendor_SysTickConfig == 0U)
|
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief System Tick Configuration
|
\brief System Tick Configuration
|
||||||
|
@ -1665,8 +1835,8 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
|
extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
|
||||||
#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
|
#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
|
@ -0,0 +1,270 @@
|
||||||
|
/******************************************************************************
|
||||||
|
* @file mpu_armv7.h
|
||||||
|
* @brief CMSIS MPU API for Armv7-M MPU
|
||||||
|
* @version V5.0.4
|
||||||
|
* @date 10. January 2018
|
||||||
|
******************************************************************************/
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined ( __ICCARM__ )
|
||||||
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
|
#elif defined (__clang__)
|
||||||
|
#pragma clang system_header /* treat file as system include file */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef ARM_MPU_ARMV7_H
|
||||||
|
#define ARM_MPU_ARMV7_H
|
||||||
|
|
||||||
|
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
|
||||||
|
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
|
||||||
|
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
|
||||||
|
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
|
||||||
|
|
||||||
|
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
|
||||||
|
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
|
||||||
|
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
|
||||||
|
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
|
||||||
|
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
|
||||||
|
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
|
||||||
|
|
||||||
|
/** MPU Region Base Address Register Value
|
||||||
|
*
|
||||||
|
* \param Region The region to be configured, number 0 to 15.
|
||||||
|
* \param BaseAddress The base address for the region.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_RBAR(Region, BaseAddress) \
|
||||||
|
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
|
||||||
|
((Region) & MPU_RBAR_REGION_Msk) | \
|
||||||
|
(MPU_RBAR_VALID_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attributes
|
||||||
|
*
|
||||||
|
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||||
|
* \param IsShareable Region is shareable between multiple bus masters.
|
||||||
|
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||||
|
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
|
||||||
|
((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
|
||||||
|
(((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
|
||||||
|
(((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
|
||||||
|
(((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Region Attribute and Size Register Value
|
||||||
|
*
|
||||||
|
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||||
|
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||||
|
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
|
||||||
|
* \param SubRegionDisable Sub-region disable field.
|
||||||
|
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
|
||||||
|
((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
|
||||||
|
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
|
||||||
|
(((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Region Attribute and Size Register Value
|
||||||
|
*
|
||||||
|
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||||
|
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||||
|
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||||
|
* \param IsShareable Region is shareable between multiple bus masters.
|
||||||
|
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||||
|
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||||
|
* \param SubRegionDisable Sub-region disable field.
|
||||||
|
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
|
||||||
|
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attribute for strongly ordered memory.
|
||||||
|
* - TEX: 000b
|
||||||
|
* - Shareable
|
||||||
|
* - Non-cacheable
|
||||||
|
* - Non-bufferable
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attribute for device memory.
|
||||||
|
* - TEX: 000b (if non-shareable) or 010b (if shareable)
|
||||||
|
* - Shareable or non-shareable
|
||||||
|
* - Non-cacheable
|
||||||
|
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
|
||||||
|
*
|
||||||
|
* \param IsShareable Configures the device memory as shareable or non-shareable.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attribute for normal memory.
|
||||||
|
* - TEX: 1BBb (reflecting outer cacheability rules)
|
||||||
|
* - Shareable or non-shareable
|
||||||
|
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
|
||||||
|
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
|
||||||
|
*
|
||||||
|
* \param OuterCp Configures the outer cache policy.
|
||||||
|
* \param InnerCp Configures the inner cache policy.
|
||||||
|
* \param IsShareable Configures the memory as shareable or non-shareable.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attribute non-cacheable policy.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_CACHEP_NOCACHE 0U
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attribute write-back, write and read allocate policy.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_CACHEP_WB_WRA 1U
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attribute write-through, no write allocate policy.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_CACHEP_WT_NWA 2U
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attribute write-back, no write allocate policy.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_CACHEP_WB_NWA 3U
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Struct for a single MPU Region
|
||||||
|
*/
|
||||||
|
typedef struct {
|
||||||
|
uint32_t RBAR; //!< The region base address register value (RBAR)
|
||||||
|
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
|
||||||
|
} ARM_MPU_Region_t;
|
||||||
|
|
||||||
|
/** Enable the MPU.
|
||||||
|
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||||
|
{
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||||
|
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||||
|
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Disable the MPU.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||||
|
{
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||||
|
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||||
|
#endif
|
||||||
|
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Clear and disable the given MPU region.
|
||||||
|
* \param rnr Region number to be cleared.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||||
|
{
|
||||||
|
MPU->RNR = rnr;
|
||||||
|
MPU->RASR = 0U;
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Configure an MPU region.
|
||||||
|
* \param rbar Value for RBAR register.
|
||||||
|
* \param rsar Value for RSAR register.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
|
||||||
|
{
|
||||||
|
MPU->RBAR = rbar;
|
||||||
|
MPU->RASR = rasr;
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Configure the given MPU region.
|
||||||
|
* \param rnr Region number to be configured.
|
||||||
|
* \param rbar Value for RBAR register.
|
||||||
|
* \param rsar Value for RSAR register.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
|
||||||
|
{
|
||||||
|
MPU->RNR = rnr;
|
||||||
|
MPU->RBAR = rbar;
|
||||||
|
MPU->RASR = rasr;
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Memcopy with strictly ordered memory access, e.g. for register targets.
|
||||||
|
* \param dst Destination data is copied to.
|
||||||
|
* \param src Source data is copied from.
|
||||||
|
* \param len Amount of data words to be copied.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||||
|
{
|
||||||
|
uint32_t i;
|
||||||
|
for (i = 0U; i < len; ++i)
|
||||||
|
{
|
||||||
|
dst[i] = src[i];
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Load the given number of MPU regions from a table.
|
||||||
|
* \param table Pointer to the MPU configuration table.
|
||||||
|
* \param cnt Amount of regions to be configured.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||||
|
{
|
||||||
|
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||||
|
while (cnt > MPU_TYPE_RALIASES) {
|
||||||
|
orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
|
||||||
|
table += MPU_TYPE_RALIASES;
|
||||||
|
cnt -= MPU_TYPE_RALIASES;
|
||||||
|
}
|
||||||
|
orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
|
@ -0,0 +1,333 @@
|
||||||
|
/******************************************************************************
|
||||||
|
* @file mpu_armv8.h
|
||||||
|
* @brief CMSIS MPU API for Armv8-M MPU
|
||||||
|
* @version V5.0.4
|
||||||
|
* @date 10. January 2018
|
||||||
|
******************************************************************************/
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined ( __ICCARM__ )
|
||||||
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
|
#elif defined (__clang__)
|
||||||
|
#pragma clang system_header /* treat file as system include file */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef ARM_MPU_ARMV8_H
|
||||||
|
#define ARM_MPU_ARMV8_H
|
||||||
|
|
||||||
|
/** \brief Attribute for device memory (outer only) */
|
||||||
|
#define ARM_MPU_ATTR_DEVICE ( 0U )
|
||||||
|
|
||||||
|
/** \brief Attribute for non-cacheable, normal memory */
|
||||||
|
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
|
||||||
|
|
||||||
|
/** \brief Attribute for normal memory (outer and inner)
|
||||||
|
* \param NT Non-Transient: Set to 1 for non-transient data.
|
||||||
|
* \param WB Write-Back: Set to 1 to use write-back update policy.
|
||||||
|
* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
|
||||||
|
* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
|
||||||
|
(((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
|
||||||
|
|
||||||
|
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
|
||||||
|
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
|
||||||
|
|
||||||
|
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
|
||||||
|
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
|
||||||
|
|
||||||
|
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
|
||||||
|
#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
|
||||||
|
|
||||||
|
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
|
||||||
|
#define ARM_MPU_ATTR_DEVICE_GRE (3U)
|
||||||
|
|
||||||
|
/** \brief Memory Attribute
|
||||||
|
* \param O Outer memory attributes
|
||||||
|
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
|
||||||
|
|
||||||
|
/** \brief Normal memory non-shareable */
|
||||||
|
#define ARM_MPU_SH_NON (0U)
|
||||||
|
|
||||||
|
/** \brief Normal memory outer shareable */
|
||||||
|
#define ARM_MPU_SH_OUTER (2U)
|
||||||
|
|
||||||
|
/** \brief Normal memory inner shareable */
|
||||||
|
#define ARM_MPU_SH_INNER (3U)
|
||||||
|
|
||||||
|
/** \brief Memory access permissions
|
||||||
|
* \param RO Read-Only: Set to 1 for read-only memory.
|
||||||
|
* \param NP Non-Privileged: Set to 1 for non-privileged memory.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
|
||||||
|
|
||||||
|
/** \brief Region Base Address Register value
|
||||||
|
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
|
||||||
|
* \param SH Defines the Shareability domain for this memory region.
|
||||||
|
* \param RO Read-Only: Set to 1 for a read-only memory region.
|
||||||
|
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
|
||||||
|
* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
|
||||||
|
((BASE & MPU_RBAR_BASE_Msk) | \
|
||||||
|
((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
|
||||||
|
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
|
||||||
|
((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
|
||||||
|
|
||||||
|
/** \brief Region Limit Address Register value
|
||||||
|
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
|
||||||
|
* \param IDX The attribute index to be associated with this memory region.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_RLAR(LIMIT, IDX) \
|
||||||
|
((LIMIT & MPU_RLAR_LIMIT_Msk) | \
|
||||||
|
((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
|
||||||
|
(MPU_RLAR_EN_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Struct for a single MPU Region
|
||||||
|
*/
|
||||||
|
typedef struct {
|
||||||
|
uint32_t RBAR; /*!< Region Base Address Register value */
|
||||||
|
uint32_t RLAR; /*!< Region Limit Address Register value */
|
||||||
|
} ARM_MPU_Region_t;
|
||||||
|
|
||||||
|
/** Enable the MPU.
|
||||||
|
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||||
|
{
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||||
|
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||||
|
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Disable the MPU.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||||
|
{
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||||
|
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||||
|
#endif
|
||||||
|
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef MPU_NS
|
||||||
|
/** Enable the Non-secure MPU.
|
||||||
|
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
|
||||||
|
{
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||||
|
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||||
|
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Disable the Non-secure MPU.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
|
||||||
|
{
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||||
|
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||||
|
#endif
|
||||||
|
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** Set the memory attribute encoding to the given MPU.
|
||||||
|
* \param mpu Pointer to the MPU to be configured.
|
||||||
|
* \param idx The attribute index to be set [0-7]
|
||||||
|
* \param attr The attribute value to be set.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
|
||||||
|
{
|
||||||
|
const uint8_t reg = idx / 4U;
|
||||||
|
const uint32_t pos = ((idx % 4U) * 8U);
|
||||||
|
const uint32_t mask = 0xFFU << pos;
|
||||||
|
|
||||||
|
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
|
||||||
|
return; // invalid index
|
||||||
|
}
|
||||||
|
|
||||||
|
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Set the memory attribute encoding.
|
||||||
|
* \param idx The attribute index to be set [0-7]
|
||||||
|
* \param attr The attribute value to be set.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
|
||||||
|
{
|
||||||
|
ARM_MPU_SetMemAttrEx(MPU, idx, attr);
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef MPU_NS
|
||||||
|
/** Set the memory attribute encoding to the Non-secure MPU.
|
||||||
|
* \param idx The attribute index to be set [0-7]
|
||||||
|
* \param attr The attribute value to be set.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
|
||||||
|
{
|
||||||
|
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** Clear and disable the given MPU region of the given MPU.
|
||||||
|
* \param mpu Pointer to MPU to be used.
|
||||||
|
* \param rnr Region number to be cleared.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
|
||||||
|
{
|
||||||
|
mpu->RNR = rnr;
|
||||||
|
mpu->RLAR = 0U;
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Clear and disable the given MPU region.
|
||||||
|
* \param rnr Region number to be cleared.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||||
|
{
|
||||||
|
ARM_MPU_ClrRegionEx(MPU, rnr);
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef MPU_NS
|
||||||
|
/** Clear and disable the given Non-secure MPU region.
|
||||||
|
* \param rnr Region number to be cleared.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
|
||||||
|
{
|
||||||
|
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** Configure the given MPU region of the given MPU.
|
||||||
|
* \param mpu Pointer to MPU to be used.
|
||||||
|
* \param rnr Region number to be configured.
|
||||||
|
* \param rbar Value for RBAR register.
|
||||||
|
* \param rlar Value for RLAR register.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||||
|
{
|
||||||
|
mpu->RNR = rnr;
|
||||||
|
mpu->RBAR = rbar;
|
||||||
|
mpu->RLAR = rlar;
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Configure the given MPU region.
|
||||||
|
* \param rnr Region number to be configured.
|
||||||
|
* \param rbar Value for RBAR register.
|
||||||
|
* \param rlar Value for RLAR register.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||||
|
{
|
||||||
|
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef MPU_NS
|
||||||
|
/** Configure the given Non-secure MPU region.
|
||||||
|
* \param rnr Region number to be configured.
|
||||||
|
* \param rbar Value for RBAR register.
|
||||||
|
* \param rlar Value for RLAR register.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||||
|
{
|
||||||
|
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** Memcopy with strictly ordered memory access, e.g. for register targets.
|
||||||
|
* \param dst Destination data is copied to.
|
||||||
|
* \param src Source data is copied from.
|
||||||
|
* \param len Amount of data words to be copied.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||||
|
{
|
||||||
|
uint32_t i;
|
||||||
|
for (i = 0U; i < len; ++i)
|
||||||
|
{
|
||||||
|
dst[i] = src[i];
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Load the given number of MPU regions from a table to the given MPU.
|
||||||
|
* \param mpu Pointer to the MPU registers to be used.
|
||||||
|
* \param rnr First region number to be configured.
|
||||||
|
* \param table Pointer to the MPU configuration table.
|
||||||
|
* \param cnt Amount of regions to be configured.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||||
|
{
|
||||||
|
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||||
|
if (cnt == 1U) {
|
||||||
|
mpu->RNR = rnr;
|
||||||
|
orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
|
||||||
|
} else {
|
||||||
|
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
|
||||||
|
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
|
||||||
|
|
||||||
|
mpu->RNR = rnrBase;
|
||||||
|
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
|
||||||
|
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
|
||||||
|
orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
|
||||||
|
table += c;
|
||||||
|
cnt -= c;
|
||||||
|
rnrOffset = 0U;
|
||||||
|
rnrBase += MPU_TYPE_RALIASES;
|
||||||
|
mpu->RNR = rnrBase;
|
||||||
|
}
|
||||||
|
|
||||||
|
orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Load the given number of MPU regions from a table.
|
||||||
|
* \param rnr First region number to be configured.
|
||||||
|
* \param table Pointer to the MPU configuration table.
|
||||||
|
* \param cnt Amount of regions to be configured.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||||
|
{
|
||||||
|
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef MPU_NS
|
||||||
|
/** Load the given number of MPU regions from a table to the Non-secure MPU.
|
||||||
|
* \param rnr First region number to be configured.
|
||||||
|
* \param table Pointer to the MPU configuration table.
|
||||||
|
* \param cnt Amount of regions to be configured.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||||
|
{
|
||||||
|
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
|
@ -0,0 +1,70 @@
|
||||||
|
/******************************************************************************
|
||||||
|
* @file tz_context.h
|
||||||
|
* @brief Context Management for Armv8-M TrustZone
|
||||||
|
* @version V1.0.1
|
||||||
|
* @date 10. January 2018
|
||||||
|
******************************************************************************/
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined ( __ICCARM__ )
|
||||||
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
|
#elif defined (__clang__)
|
||||||
|
#pragma clang system_header /* treat file as system include file */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef TZ_CONTEXT_H
|
||||||
|
#define TZ_CONTEXT_H
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
#ifndef TZ_MODULEID_T
|
||||||
|
#define TZ_MODULEID_T
|
||||||
|
/// \details Data type that identifies secure software modules called by a process.
|
||||||
|
typedef uint32_t TZ_ModuleId_t;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/// \details TZ Memory ID identifies an allocated memory slot.
|
||||||
|
typedef uint32_t TZ_MemoryId_t;
|
||||||
|
|
||||||
|
/// Initialize secure context memory system
|
||||||
|
/// \return execution status (1: success, 0: error)
|
||||||
|
uint32_t TZ_InitContextSystem_S (void);
|
||||||
|
|
||||||
|
/// Allocate context memory for calling secure software modules in TrustZone
|
||||||
|
/// \param[in] module identifies software modules called from non-secure mode
|
||||||
|
/// \return value != 0 id TrustZone memory slot identifier
|
||||||
|
/// \return value 0 no memory available or internal error
|
||||||
|
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
|
||||||
|
|
||||||
|
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
|
||||||
|
/// \param[in] id TrustZone memory slot identifier
|
||||||
|
/// \return execution status (1: success, 0: error)
|
||||||
|
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
|
||||||
|
|
||||||
|
/// Load secure context (called on RTOS thread context switch)
|
||||||
|
/// \param[in] id TrustZone memory slot identifier
|
||||||
|
/// \return execution status (1: success, 0: error)
|
||||||
|
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
|
||||||
|
|
||||||
|
/// Store secure context (called on RTOS thread context switch)
|
||||||
|
/// \param[in] id TrustZone memory slot identifier
|
||||||
|
/// \return execution status (1: success, 0: error)
|
||||||
|
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
|
||||||
|
|
||||||
|
#endif // TZ_CONTEXT_H
|
|
@ -7,36 +7,20 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
#ifndef __STM32_HAL_LEGACY
|
#ifndef STM32_HAL_LEGACY
|
||||||
#define __STM32_HAL_LEGACY
|
#define STM32_HAL_LEGACY
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
extern "C" {
|
extern "C" {
|
||||||
|
@ -110,6 +94,10 @@
|
||||||
#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL
|
#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL
|
||||||
#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL
|
#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL
|
||||||
#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1
|
#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1
|
||||||
|
|
||||||
|
#if defined(STM32H7)
|
||||||
|
#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT
|
||||||
|
#endif /* STM32H7 */
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
@ -248,6 +236,16 @@
|
||||||
#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
|
#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
|
||||||
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
|
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
|
||||||
|
|
||||||
|
#if defined(STM32G4) || defined(STM32H7)
|
||||||
|
#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
|
||||||
|
#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4)
|
||||||
|
#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
|
||||||
|
#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
|
||||||
|
#endif
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
@ -274,7 +272,112 @@
|
||||||
#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
|
#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
|
||||||
#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
|
#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
|
||||||
|
|
||||||
|
#if defined(STM32L4)
|
||||||
|
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT
|
||||||
|
|
||||||
|
#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
|
||||||
|
#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
|
||||||
|
#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
|
||||||
|
#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
|
||||||
|
|
||||||
|
#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
|
||||||
|
#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* STM32L4 */
|
||||||
|
|
||||||
|
#if defined(STM32G0)
|
||||||
|
#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1
|
||||||
|
#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(STM32H7)
|
||||||
|
|
||||||
|
#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
|
||||||
|
#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2
|
||||||
|
|
||||||
|
#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX
|
||||||
|
#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX
|
||||||
|
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
|
||||||
|
#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO
|
||||||
|
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
|
||||||
|
#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
|
||||||
|
|
||||||
|
#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
|
||||||
|
#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
|
||||||
|
#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
|
||||||
|
#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
|
||||||
|
|
||||||
|
#define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT
|
||||||
|
#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT
|
||||||
|
#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT
|
||||||
|
|
||||||
|
#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT
|
||||||
|
#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT
|
||||||
|
|
||||||
|
#endif /* STM32H7 */
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
|
@ -355,6 +458,40 @@
|
||||||
#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
|
#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
|
||||||
#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
|
#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
|
||||||
#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
|
#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
|
||||||
|
#if defined(STM32G0)
|
||||||
|
#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE
|
||||||
|
#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH
|
||||||
|
#else
|
||||||
|
#define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE
|
||||||
|
#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE
|
||||||
|
#endif
|
||||||
|
#if defined(STM32H7)
|
||||||
|
#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1
|
||||||
|
#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1
|
||||||
|
#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1
|
||||||
|
#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
|
||||||
|
#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
|
||||||
|
#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2
|
||||||
|
#define FLASH_FLAG_WDW FLASH_FLAG_WBNE
|
||||||
|
#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL
|
||||||
|
#endif /* STM32H7 */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined(STM32H7)
|
||||||
|
#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE
|
||||||
|
#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE
|
||||||
|
#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET
|
||||||
|
#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET
|
||||||
|
#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
|
||||||
|
#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
|
||||||
|
#endif /* STM32H7 */
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
|
@ -373,6 +510,13 @@
|
||||||
#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
|
#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
|
||||||
#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
|
#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
|
||||||
#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
|
#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
|
||||||
|
#if defined(STM32G4)
|
||||||
|
|
||||||
|
#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster
|
||||||
|
#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster
|
||||||
|
#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD
|
||||||
|
#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
|
||||||
|
#endif /* STM32G4 */
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
@ -386,7 +530,7 @@
|
||||||
#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
|
#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
|
||||||
#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
|
#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
|
||||||
#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16
|
#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16
|
||||||
#else
|
#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4)
|
||||||
#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE
|
#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE
|
||||||
#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE
|
#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE
|
||||||
#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8
|
#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8
|
||||||
|
@ -427,16 +571,32 @@
|
||||||
#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
|
#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#if defined(STM32H7)
|
||||||
|
#define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1
|
||||||
|
#define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1
|
||||||
|
#define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1
|
||||||
|
#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2
|
||||||
|
#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2
|
||||||
|
#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2
|
||||||
|
|
||||||
|
#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \
|
||||||
|
defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx)
|
||||||
|
#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS
|
||||||
|
#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS
|
||||||
|
#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS
|
||||||
|
#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */
|
||||||
|
#endif /* STM32H7 */
|
||||||
|
|
||||||
#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
|
#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
|
||||||
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
|
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
|
||||||
#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
|
#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
|
||||||
|
|
||||||
#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7)
|
#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7)
|
||||||
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
|
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
|
||||||
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
|
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
|
||||||
#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
|
#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
|
||||||
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
|
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
|
||||||
#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */
|
#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/
|
||||||
|
|
||||||
#if defined(STM32L1)
|
#if defined(STM32L1)
|
||||||
#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
|
#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
|
||||||
|
@ -456,78 +616,6 @@
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
#if defined(STM32H7)
|
|
||||||
#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE
|
|
||||||
#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE
|
|
||||||
#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET
|
|
||||||
#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET
|
|
||||||
#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
|
|
||||||
#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
|
|
||||||
|
|
||||||
#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
|
|
||||||
#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2
|
|
||||||
|
|
||||||
#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX
|
|
||||||
#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX
|
|
||||||
|
|
||||||
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
|
|
||||||
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
|
|
||||||
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
|
|
||||||
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
|
|
||||||
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
|
|
||||||
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
|
|
||||||
#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
|
|
||||||
#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO
|
|
||||||
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
|
|
||||||
#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
|
|
||||||
|
|
||||||
#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
|
|
||||||
#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
|
|
||||||
#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
|
|
||||||
#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
|
|
||||||
|
|
||||||
|
|
||||||
#endif /* STM32H7 */
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
|
/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
|
@ -549,6 +637,185 @@
|
||||||
#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
|
#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
|
||||||
#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
|
#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
|
||||||
#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
|
#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
|
||||||
|
|
||||||
|
#if defined(STM32G4)
|
||||||
|
#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig
|
||||||
|
#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable
|
||||||
|
#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable
|
||||||
|
#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset
|
||||||
|
#endif /* STM32G4 */
|
||||||
|
|
||||||
|
#if defined(STM32H7)
|
||||||
|
#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
|
||||||
|
#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
|
||||||
|
#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
|
||||||
|
#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
|
||||||
|
#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
|
||||||
|
#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
|
||||||
|
#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
|
||||||
|
#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
|
||||||
|
#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
|
||||||
|
#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
|
||||||
|
#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
|
||||||
|
#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
|
||||||
|
#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
|
||||||
|
#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
|
||||||
|
#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
|
||||||
|
#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
|
||||||
|
#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
|
||||||
|
#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
|
||||||
|
#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
|
||||||
|
#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
|
||||||
|
#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
|
||||||
|
#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
|
||||||
|
#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
|
||||||
|
#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
|
||||||
|
#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
|
||||||
|
#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
|
||||||
|
#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
|
||||||
|
#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
|
||||||
|
#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
|
||||||
|
#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
|
||||||
|
#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
|
||||||
|
#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
|
||||||
|
#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
|
||||||
|
#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
|
||||||
|
#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
|
||||||
|
#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
|
||||||
|
#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
|
||||||
|
#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
|
||||||
|
#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
|
||||||
|
#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
|
||||||
|
#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
|
||||||
|
#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
|
||||||
|
#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
|
||||||
|
#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
|
||||||
|
#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
|
||||||
|
#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
|
||||||
|
#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
|
||||||
|
#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
|
||||||
|
#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
|
||||||
|
#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
|
||||||
|
#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
|
||||||
|
#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
|
||||||
|
#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
|
||||||
|
#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
|
||||||
|
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
|
||||||
|
#endif /* STM32H7 */
|
||||||
|
|
||||||
|
#if defined(STM32F3)
|
||||||
|
/** @brief Constants defining available sources associated to external events.
|
||||||
|
*/
|
||||||
|
#define HRTIM_EVENTSRC_1 (0x00000000U)
|
||||||
|
#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0)
|
||||||
|
#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1)
|
||||||
|
#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
|
||||||
|
|
||||||
|
/** @brief Constants defining the events that can be selected to configure the
|
||||||
|
* set/reset crossbar of a timer output
|
||||||
|
*/
|
||||||
|
#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1)
|
||||||
|
#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2)
|
||||||
|
#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3)
|
||||||
|
#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4)
|
||||||
|
#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5)
|
||||||
|
#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6)
|
||||||
|
#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7)
|
||||||
|
#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8)
|
||||||
|
#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9)
|
||||||
|
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1)
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2)
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3)
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4)
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5)
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6)
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7)
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8)
|
||||||
|
#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9)
|
||||||
|
|
||||||
|
/** @brief Constants defining the event filtering applied to external events
|
||||||
|
* by a timer
|
||||||
|
*/
|
||||||
|
#define HRTIM_TIMEVENTFILTER_NONE (0x00000000U)
|
||||||
|
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0)
|
||||||
|
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1)
|
||||||
|
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
|
||||||
|
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2)
|
||||||
|
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
|
||||||
|
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
|
||||||
|
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
|
||||||
|
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3)
|
||||||
|
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)
|
||||||
|
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)
|
||||||
|
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
|
||||||
|
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)
|
||||||
|
#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
|
||||||
|
#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
|
||||||
|
#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
|
||||||
|
|
||||||
|
/** @brief Constants defining the DLL calibration periods (in micro seconds)
|
||||||
|
*/
|
||||||
|
#define HRTIM_CALIBRATIONRATE_7300 0x00000000U
|
||||||
|
#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0)
|
||||||
|
#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1)
|
||||||
|
#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
|
||||||
|
|
||||||
|
#endif /* STM32F3 */
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
@ -688,6 +955,12 @@
|
||||||
#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
|
#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
|
||||||
#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
|
#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
|
||||||
|
|
||||||
|
#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7)
|
||||||
|
#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID
|
||||||
|
#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
@ -696,6 +969,15 @@
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
|
#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
|
||||||
|
|
||||||
|
#if defined(STM32H7)
|
||||||
|
#define I2S_IT_TXE I2S_IT_TXP
|
||||||
|
#define I2S_IT_RXNE I2S_IT_RXP
|
||||||
|
|
||||||
|
#define I2S_FLAG_TXE I2S_FLAG_TXP
|
||||||
|
#define I2S_FLAG_RXNE I2S_FLAG_RXP
|
||||||
|
#endif
|
||||||
|
|
||||||
#if defined(STM32F7)
|
#if defined(STM32F7)
|
||||||
#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
|
#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
|
||||||
#endif
|
#endif
|
||||||
|
@ -764,6 +1046,16 @@
|
||||||
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
|
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
|
||||||
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
|
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
|
||||||
|
|
||||||
|
#if defined(STM32H7)
|
||||||
|
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X
|
||||||
|
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
|
||||||
|
|
||||||
|
#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
|
||||||
|
#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
|
||||||
|
#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
|
||||||
|
#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL
|
||||||
|
#endif /* STM32H7 */
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
@ -820,6 +1112,21 @@
|
||||||
#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
|
#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
|
||||||
#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
|
#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
|
||||||
|
|
||||||
|
#if defined(STM32H7)
|
||||||
|
|
||||||
|
#define SPI_FLAG_TXE SPI_FLAG_TXP
|
||||||
|
#define SPI_FLAG_RXNE SPI_FLAG_RXP
|
||||||
|
|
||||||
|
#define SPI_IT_TXE SPI_IT_TXP
|
||||||
|
#define SPI_IT_RXNE SPI_IT_RXP
|
||||||
|
|
||||||
|
#define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET
|
||||||
|
#define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET
|
||||||
|
#define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET
|
||||||
|
#define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET
|
||||||
|
|
||||||
|
#endif /* STM32H7 */
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
@ -887,6 +1194,33 @@
|
||||||
#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
|
#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
|
||||||
#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
|
#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
|
||||||
|
|
||||||
|
#if defined(STM32L0)
|
||||||
|
#define TIM22_TI1_GPIO1 TIM22_TI1_GPIO
|
||||||
|
#define TIM22_TI1_GPIO2 TIM22_TI1_GPIO
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(STM32F3)
|
||||||
|
#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(STM32H7)
|
||||||
|
#define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1
|
||||||
|
#define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2
|
||||||
|
#define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1
|
||||||
|
#define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2
|
||||||
|
#define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1
|
||||||
|
#define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2
|
||||||
|
#define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1
|
||||||
|
#define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1
|
||||||
|
#define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2
|
||||||
|
#define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1
|
||||||
|
#define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2
|
||||||
|
#define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2
|
||||||
|
#define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1
|
||||||
|
#define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2
|
||||||
|
#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2
|
||||||
|
#endif
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
@ -1047,8 +1381,9 @@
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\
|
#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
|
||||||
defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
|
|| defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
|
||||||
|
|| defined(STM32H7)
|
||||||
/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
|
/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
|
@ -1072,7 +1407,7 @@
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
#endif /* STM32L4 || STM32F7*/
|
#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */
|
||||||
|
|
||||||
/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
|
/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
|
||||||
* @{
|
* @{
|
||||||
|
@ -1114,6 +1449,30 @@
|
||||||
|
|
||||||
#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
|
#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
|
||||||
#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
|
#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
|
||||||
|
|
||||||
|
#if defined(STM32L4) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
|
||||||
|
|
||||||
|
#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt
|
||||||
|
#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End
|
||||||
|
#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT
|
||||||
|
#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT
|
||||||
|
|
||||||
|
#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt
|
||||||
|
#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End
|
||||||
|
#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT
|
||||||
|
#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT
|
||||||
|
|
||||||
|
#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt
|
||||||
|
#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End
|
||||||
|
#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT
|
||||||
|
#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT
|
||||||
|
|
||||||
|
#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt
|
||||||
|
#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End
|
||||||
|
#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT
|
||||||
|
#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT
|
||||||
|
|
||||||
|
#endif /* STM32L4 || STM32F4 || STM32F7 || STM32H7 */
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
@ -1136,6 +1495,13 @@
|
||||||
#endif
|
#endif
|
||||||
#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
|
#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
|
||||||
#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
|
#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
|
||||||
|
#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
|
||||||
|
#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode
|
||||||
|
#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode
|
||||||
|
#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode
|
||||||
|
#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode
|
||||||
|
#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
@ -1164,6 +1530,30 @@
|
||||||
#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
|
#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
|
||||||
|
|
||||||
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
|
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
|
||||||
|
|
||||||
|
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)
|
||||||
|
#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
|
||||||
|
#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
|
||||||
|
#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
|
||||||
|
#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
|
||||||
|
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */
|
||||||
|
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)
|
||||||
|
#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
|
||||||
|
#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
|
||||||
|
#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
|
||||||
|
#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA
|
||||||
|
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */
|
||||||
|
|
||||||
|
#if defined(STM32F4)
|
||||||
|
#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT
|
||||||
|
#define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT
|
||||||
|
#define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT
|
||||||
|
#define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT
|
||||||
|
#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA
|
||||||
|
#define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA
|
||||||
|
#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA
|
||||||
|
#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA
|
||||||
|
#endif /* STM32F4 */
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
@ -1171,6 +1561,13 @@
|
||||||
/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
|
/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
#if defined(STM32G0)
|
||||||
|
#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD
|
||||||
|
#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD
|
||||||
|
#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD
|
||||||
|
#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler
|
||||||
|
#endif
|
||||||
#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
|
#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
|
||||||
#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
|
#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
|
||||||
#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
|
#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
|
||||||
|
@ -1243,6 +1640,14 @@
|
||||||
#define HAL_TIM_DMAError TIM_DMAError
|
#define HAL_TIM_DMAError TIM_DMAError
|
||||||
#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
|
#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
|
||||||
#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
|
#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
|
||||||
|
#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
|
||||||
|
#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro
|
||||||
|
#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT
|
||||||
|
#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback
|
||||||
|
#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent
|
||||||
|
#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT
|
||||||
|
#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA
|
||||||
|
#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
@ -1456,10 +1861,17 @@
|
||||||
#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
|
#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
|
||||||
#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
|
#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
|
||||||
#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
|
#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
|
||||||
#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
|
#if defined(STM32H7)
|
||||||
#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
|
#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
|
||||||
#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
|
#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
|
||||||
#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
|
#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
|
||||||
|
#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
|
||||||
|
#else
|
||||||
|
#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
|
||||||
|
#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
|
||||||
|
#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
|
||||||
|
#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
|
||||||
|
#endif /* STM32H7 */
|
||||||
#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
|
#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
|
||||||
#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
|
#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
|
||||||
#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
|
#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
|
||||||
|
@ -1725,6 +2137,10 @@
|
||||||
#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
|
#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
|
||||||
#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
|
#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
|
||||||
|
|
||||||
|
#if defined(STM32H7)
|
||||||
|
#define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG
|
||||||
|
#endif
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
@ -2119,6 +2535,21 @@
|
||||||
#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
|
#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
|
||||||
#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
|
#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
|
||||||
#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
|
#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
|
||||||
|
|
||||||
|
#if defined(STM32WB)
|
||||||
|
#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE
|
||||||
|
#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE
|
||||||
|
#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE
|
||||||
|
#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE
|
||||||
|
#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET
|
||||||
|
#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET
|
||||||
|
#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED
|
||||||
|
#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED
|
||||||
|
#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED
|
||||||
|
#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED
|
||||||
|
#define QSPI_IRQHandler QUADSPI_IRQHandler
|
||||||
|
#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */
|
||||||
|
|
||||||
#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
|
#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
|
||||||
#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
|
#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
|
||||||
#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
|
#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
|
||||||
|
@ -2335,12 +2766,28 @@
|
||||||
#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
|
#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
|
||||||
#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
|
#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
|
||||||
#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
|
#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
|
||||||
|
|
||||||
|
#if defined(STM32H7)
|
||||||
|
#define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE
|
||||||
|
#define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE
|
||||||
|
#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE
|
||||||
|
#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE
|
||||||
|
|
||||||
|
#define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/
|
||||||
|
#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/
|
||||||
|
|
||||||
|
|
||||||
|
#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED
|
||||||
|
#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED
|
||||||
|
#endif
|
||||||
|
|
||||||
#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
|
#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
|
||||||
#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
|
#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
|
||||||
#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
|
#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
|
||||||
#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
|
#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
|
||||||
#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
|
#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
|
||||||
#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
|
#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
|
||||||
|
|
||||||
#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
|
#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
|
||||||
#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
|
#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
|
||||||
#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
|
#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
|
||||||
|
@ -2673,6 +3120,15 @@
|
||||||
#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED
|
#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED
|
||||||
#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED
|
#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED
|
||||||
|
|
||||||
|
#if defined(STM32L1)
|
||||||
|
#define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
|
||||||
|
#define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
|
||||||
|
#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
|
||||||
|
#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
|
||||||
|
#define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
|
||||||
|
#define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
|
||||||
|
#endif /* STM32L1 */
|
||||||
|
|
||||||
#if defined(STM32F4)
|
#if defined(STM32F4)
|
||||||
#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
|
#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
|
||||||
#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
|
#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
|
||||||
|
@ -2787,7 +3243,9 @@
|
||||||
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
|
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
|
||||||
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
|
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
|
||||||
|
|
||||||
#if defined(STM32WB) || defined(STM32G0)
|
#if defined(STM32L4)
|
||||||
|
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
|
||||||
|
#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5)
|
||||||
#else
|
#else
|
||||||
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
|
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
|
||||||
#endif
|
#endif
|
||||||
|
@ -2915,7 +3373,7 @@
|
||||||
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
|
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
#if defined (STM32G0)
|
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4)
|
||||||
#else
|
#else
|
||||||
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
|
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
|
||||||
#endif
|
#endif
|
||||||
|
@ -3031,13 +3489,24 @@
|
||||||
#define SDIO_IRQHandler SDMMC1_IRQHandler
|
#define SDIO_IRQHandler SDMMC1_IRQHandler
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2)
|
#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7)
|
||||||
#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef
|
#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef
|
||||||
#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef
|
#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef
|
||||||
#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef
|
#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef
|
||||||
#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef
|
#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#if defined(STM32H7) || defined(STM32L5)
|
||||||
|
#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback
|
||||||
|
#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback
|
||||||
|
#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
|
||||||
|
#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback
|
||||||
|
#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback
|
||||||
|
#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback
|
||||||
|
#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback
|
||||||
|
#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback
|
||||||
|
#define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback
|
||||||
|
#endif
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
@ -3252,6 +3721,42 @@
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#if defined(STM32H7)
|
||||||
|
#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow
|
||||||
|
#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT
|
||||||
|
#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA
|
||||||
|
#endif
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3)
|
||||||
|
#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT
|
||||||
|
#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA
|
||||||
|
#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart
|
||||||
|
#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT
|
||||||
|
#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA
|
||||||
|
#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop
|
||||||
|
#endif
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7)
|
||||||
|
#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
|
||||||
|
#endif /* STM32L4 || STM32F4 || STM32F7 */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
|
/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
|
||||||
* @{
|
* @{
|
||||||
|
@ -3265,7 +3770,7 @@
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#endif /* ___STM32_HAL_LEGACY */
|
#endif /* STM32_HAL_LEGACY */
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
|
|
||||||
|
|
|
@ -7,32 +7,16 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
#ifndef __STM32F2xx_HAL_H
|
#ifndef __STM32F2xx_HAL_H
|
||||||
|
@ -55,6 +39,29 @@
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
/* Exported types ------------------------------------------------------------*/
|
||||||
/* Exported constants --------------------------------------------------------*/
|
/* Exported constants --------------------------------------------------------*/
|
||||||
|
|
||||||
|
/** @defgroup HAL_Exported_Constants HAL Exported Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup HAL_TICK_FREQ Tick Frequency
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
HAL_TICK_FREQ_10HZ = 100U,
|
||||||
|
HAL_TICK_FREQ_100HZ = 10U,
|
||||||
|
HAL_TICK_FREQ_1KHZ = 1U,
|
||||||
|
HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
|
||||||
|
} HAL_TickFreqTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
/* Exported macro ------------------------------------------------------------*/
|
/* Exported macro ------------------------------------------------------------*/
|
||||||
/** @defgroup HAL_Exported_Macros HAL Exported Macros
|
/** @defgroup HAL_Exported_Macros HAL Exported Macros
|
||||||
* @{
|
* @{
|
||||||
|
@ -135,6 +142,16 @@
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
/** @defgroup HAL_Private_Macros HAL Private Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \
|
||||||
|
((FREQ) == HAL_TICK_FREQ_100HZ) || \
|
||||||
|
((FREQ) == HAL_TICK_FREQ_1KHZ))
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
/* Exported functions --------------------------------------------------------*/
|
/* Exported functions --------------------------------------------------------*/
|
||||||
/** @addtogroup HAL_Exported_Functions
|
/** @addtogroup HAL_Exported_Functions
|
||||||
* @{
|
* @{
|
||||||
|
@ -148,6 +165,17 @@ HAL_StatusTypeDef HAL_DeInit(void);
|
||||||
void HAL_MspInit(void);
|
void HAL_MspInit(void);
|
||||||
void HAL_MspDeInit(void);
|
void HAL_MspDeInit(void);
|
||||||
HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
|
HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported variables ---------------------------------------------------------*/
|
||||||
|
/** @addtogroup HAL_Exported_Variables
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
extern __IO uint32_t uwTick;
|
||||||
|
extern uint32_t uwTickPrio;
|
||||||
|
extern HAL_TickFreqTypeDef uwTickFreq;
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
@ -159,6 +187,9 @@ HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
|
||||||
void HAL_IncTick(void);
|
void HAL_IncTick(void);
|
||||||
void HAL_Delay(__IO uint32_t Delay);
|
void HAL_Delay(__IO uint32_t Delay);
|
||||||
uint32_t HAL_GetTick(void);
|
uint32_t HAL_GetTick(void);
|
||||||
|
uint32_t HAL_GetTickPrio(void);
|
||||||
|
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
|
||||||
|
HAL_TickFreqTypeDef HAL_GetTickFreq(void);
|
||||||
void HAL_SuspendTick(void);
|
void HAL_SuspendTick(void);
|
||||||
void HAL_ResumeTick(void);
|
void HAL_ResumeTick(void);
|
||||||
uint32_t HAL_GetHalVersion(void);
|
uint32_t HAL_GetHalVersion(void);
|
||||||
|
@ -172,7 +203,9 @@ void HAL_DBGMCU_EnableDBGStandbyMode(void);
|
||||||
void HAL_DBGMCU_DisableDBGStandbyMode(void);
|
void HAL_DBGMCU_DisableDBGStandbyMode(void);
|
||||||
void HAL_EnableCompensationCell(void);
|
void HAL_EnableCompensationCell(void);
|
||||||
void HAL_DisableCompensationCell(void);
|
void HAL_DisableCompensationCell(void);
|
||||||
void HAL_GetUID(uint32_t *UID);
|
uint32_t HAL_GetUIDw0(void);
|
||||||
|
uint32_t HAL_GetUIDw1(void);
|
||||||
|
uint32_t HAL_GetUIDw2(void);
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -6,32 +6,16 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
#ifndef __STM32F2xx_HAL_CORTEX_H
|
#ifndef __STM32F2xx_HAL_CORTEX_H
|
||||||
|
|
|
@ -7,29 +7,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
@ -45,7 +29,7 @@
|
||||||
/* Includes ------------------------------------------------------------------*/
|
/* Includes ------------------------------------------------------------------*/
|
||||||
#include "stm32f2xx.h"
|
#include "stm32f2xx.h"
|
||||||
#include "Legacy/stm32_hal_legacy.h"
|
#include "Legacy/stm32_hal_legacy.h"
|
||||||
#include <stdio.h>
|
#include <stddef.h>
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
/* Exported types ------------------------------------------------------------*/
|
||||||
|
|
||||||
|
@ -70,18 +54,19 @@ typedef enum
|
||||||
} HAL_LockTypeDef;
|
} HAL_LockTypeDef;
|
||||||
|
|
||||||
/* Exported macro ------------------------------------------------------------*/
|
/* Exported macro ------------------------------------------------------------*/
|
||||||
|
|
||||||
|
#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
|
||||||
|
|
||||||
#define HAL_MAX_DELAY 0xFFFFFFFFU
|
#define HAL_MAX_DELAY 0xFFFFFFFFU
|
||||||
|
|
||||||
#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET)
|
#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT))
|
||||||
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET)
|
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)
|
||||||
|
|
||||||
#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
|
#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
|
||||||
do{ \
|
do{ \
|
||||||
(__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
|
(__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
|
||||||
(__DMA_HANDLE__).Parent = (__HANDLE__); \
|
(__DMA_HANDLE__).Parent = (__HANDLE__); \
|
||||||
} while(0)
|
} while(0U)
|
||||||
|
|
||||||
#define UNUSED(x) ((void)(x))
|
|
||||||
|
|
||||||
/** @brief Reset the Handle's State field.
|
/** @brief Reset the Handle's State field.
|
||||||
* @param __HANDLE__ specifies the Peripheral Handle.
|
* @param __HANDLE__ specifies the Peripheral Handle.
|
||||||
|
@ -135,7 +120,7 @@ typedef enum
|
||||||
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
|
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
|
||||||
#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
|
#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
|
||||||
#ifndef __ALIGN_END
|
#ifndef __ALIGN_END
|
||||||
#define __ALIGN_END __attribute__ ((aligned (4)))
|
#define __ALIGN_END __attribute__ ((aligned (4U)))
|
||||||
#endif /* __ALIGN_END */
|
#endif /* __ALIGN_END */
|
||||||
#ifndef __ALIGN_BEGIN
|
#ifndef __ALIGN_BEGIN
|
||||||
#define __ALIGN_BEGIN
|
#define __ALIGN_BEGIN
|
||||||
|
@ -146,7 +131,7 @@ typedef enum
|
||||||
#endif /* __ALIGN_END */
|
#endif /* __ALIGN_END */
|
||||||
#ifndef __ALIGN_BEGIN
|
#ifndef __ALIGN_BEGIN
|
||||||
#if defined (__CC_ARM) /* ARM Compiler */
|
#if defined (__CC_ARM) /* ARM Compiler */
|
||||||
#define __ALIGN_BEGIN __align(4)
|
#define __ALIGN_BEGIN __align(4U)
|
||||||
#elif defined (__ICCARM__) /* IAR Compiler */
|
#elif defined (__ICCARM__) /* IAR Compiler */
|
||||||
#define __ALIGN_BEGIN
|
#define __ALIGN_BEGIN
|
||||||
#endif /* __CC_ARM */
|
#endif /* __CC_ARM */
|
||||||
|
|
|
@ -6,32 +6,16 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
#ifndef __STM32F2xx_HAL_DMA_H
|
#ifndef __STM32F2xx_HAL_DMA_H
|
||||||
|
|
|
@ -6,29 +6,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -0,0 +1,293 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f2xx_hal_exti.h
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @brief Header file of EXTI HAL module.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
|
*
|
||||||
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
|
* the "License"; You may not use this file except in compliance with the
|
||||||
|
* License. You may obtain a copy of the License at:
|
||||||
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
|
#ifndef STM32F2xx_HAL_EXTI_H
|
||||||
|
#define STM32F2xx_HAL_EXTI_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f2xx_hal_def.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F2xx_HAL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup EXTI EXTI
|
||||||
|
* @brief EXTI HAL module driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported types ------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/** @defgroup EXTI_Exported_Types EXTI Exported Types
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief HAL EXTI common Callback ID enumeration definition
|
||||||
|
*/
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
HAL_EXTI_COMMON_CB_ID = 0x00U
|
||||||
|
} EXTI_CallbackIDTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief EXTI Handle structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t Line; /*!< Exti line number */
|
||||||
|
void (* PendingCallback)(void); /*!< Exti pending callback */
|
||||||
|
} EXTI_HandleTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief EXTI Configuration structure definition
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t Line; /*!< The Exti line to be configured. This parameter
|
||||||
|
can be a value of @ref EXTI_Line */
|
||||||
|
uint32_t Mode; /*!< The Exit Mode to be configured for a core.
|
||||||
|
This parameter can be a combination of @ref EXTI_Mode */
|
||||||
|
uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter
|
||||||
|
can be a value of @ref EXTI_Trigger */
|
||||||
|
uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured.
|
||||||
|
This parameter is only possible for line 0 to 15. It
|
||||||
|
can be a value of @ref EXTI_GPIOSel */
|
||||||
|
} EXTI_ConfigTypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported constants --------------------------------------------------------*/
|
||||||
|
/** @defgroup EXTI_Exported_Constants EXTI Exported Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup EXTI_Line EXTI Line
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define EXTI_LINE_0 (EXTI_GPIO | 0x00u) /*!< External interrupt line 0 */
|
||||||
|
#define EXTI_LINE_1 (EXTI_GPIO | 0x01u) /*!< External interrupt line 1 */
|
||||||
|
#define EXTI_LINE_2 (EXTI_GPIO | 0x02u) /*!< External interrupt line 2 */
|
||||||
|
#define EXTI_LINE_3 (EXTI_GPIO | 0x03u) /*!< External interrupt line 3 */
|
||||||
|
#define EXTI_LINE_4 (EXTI_GPIO | 0x04u) /*!< External interrupt line 4 */
|
||||||
|
#define EXTI_LINE_5 (EXTI_GPIO | 0x05u) /*!< External interrupt line 5 */
|
||||||
|
#define EXTI_LINE_6 (EXTI_GPIO | 0x06u) /*!< External interrupt line 6 */
|
||||||
|
#define EXTI_LINE_7 (EXTI_GPIO | 0x07u) /*!< External interrupt line 7 */
|
||||||
|
#define EXTI_LINE_8 (EXTI_GPIO | 0x08u) /*!< External interrupt line 8 */
|
||||||
|
#define EXTI_LINE_9 (EXTI_GPIO | 0x09u) /*!< External interrupt line 9 */
|
||||||
|
#define EXTI_LINE_10 (EXTI_GPIO | 0x0Au) /*!< External interrupt line 10 */
|
||||||
|
#define EXTI_LINE_11 (EXTI_GPIO | 0x0Bu) /*!< External interrupt line 11 */
|
||||||
|
#define EXTI_LINE_12 (EXTI_GPIO | 0x0Cu) /*!< External interrupt line 12 */
|
||||||
|
#define EXTI_LINE_13 (EXTI_GPIO | 0x0Du) /*!< External interrupt line 13 */
|
||||||
|
#define EXTI_LINE_14 (EXTI_GPIO | 0x0Eu) /*!< External interrupt line 14 */
|
||||||
|
#define EXTI_LINE_15 (EXTI_GPIO | 0x0Fu) /*!< External interrupt line 15 */
|
||||||
|
#define EXTI_LINE_16 (EXTI_CONFIG | 0x10u) /*!< External interrupt line 16 Connected to the PVD Output */
|
||||||
|
#define EXTI_LINE_17 (EXTI_CONFIG | 0x11u) /*!< External interrupt line 17 Connected to the RTC Alarm event */
|
||||||
|
#define EXTI_LINE_18 (EXTI_CONFIG | 0x12u) /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */
|
||||||
|
#define EXTI_LINE_19 (EXTI_CONFIG | 0x13u) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
|
||||||
|
#define EXTI_LINE_20 (EXTI_CONFIG | 0x14u) /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */
|
||||||
|
#define EXTI_LINE_21 (EXTI_CONFIG | 0x15u) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */
|
||||||
|
#define EXTI_LINE_22 (EXTI_CONFIG | 0x16u) /*!< External interrupt line 22 Connected to the RTC Wakeup event */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup EXTI_Mode EXTI Mode
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define EXTI_MODE_NONE 0x00000000u
|
||||||
|
#define EXTI_MODE_INTERRUPT 0x00000001u
|
||||||
|
#define EXTI_MODE_EVENT 0x00000002u
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup EXTI_Trigger EXTI Trigger
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define EXTI_TRIGGER_NONE 0x00000000u
|
||||||
|
#define EXTI_TRIGGER_RISING 0x00000001u
|
||||||
|
#define EXTI_TRIGGER_FALLING 0x00000002u
|
||||||
|
#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup EXTI_GPIOSel EXTI GPIOSel
|
||||||
|
* @brief
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define EXTI_GPIOA 0x00000000u
|
||||||
|
#define EXTI_GPIOB 0x00000001u
|
||||||
|
#define EXTI_GPIOC 0x00000002u
|
||||||
|
#define EXTI_GPIOD 0x00000003u
|
||||||
|
#define EXTI_GPIOE 0x00000004u
|
||||||
|
#define EXTI_GPIOF 0x00000005u
|
||||||
|
#define EXTI_GPIOG 0x00000006u
|
||||||
|
#define EXTI_GPIOH 0x00000007u
|
||||||
|
#define EXTI_GPIOI 0x00000008u
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Exported macro ------------------------------------------------------------*/
|
||||||
|
/** @defgroup EXTI_Exported_Macros EXTI Exported Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private constants --------------------------------------------------------*/
|
||||||
|
/** @defgroup EXTI_Private_Constants EXTI Private Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/**
|
||||||
|
* @brief EXTI Line property definition
|
||||||
|
*/
|
||||||
|
#define EXTI_PROPERTY_SHIFT 24u
|
||||||
|
#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT)
|
||||||
|
#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
|
||||||
|
#define EXTI_PROPERTY_MASK (EXTI_CONFIG | EXTI_GPIO)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief EXTI bit usage
|
||||||
|
*/
|
||||||
|
#define EXTI_PIN_MASK 0x0000001Fu
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief EXTI Mask for interrupt & event mode
|
||||||
|
*/
|
||||||
|
#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief EXTI Mask for trigger possibilities
|
||||||
|
*/
|
||||||
|
#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief EXTI Line number
|
||||||
|
*/
|
||||||
|
#define EXTI_LINE_NB 23uL
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private macros ------------------------------------------------------------*/
|
||||||
|
/** @defgroup EXTI_Private_Macros EXTI Private Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \
|
||||||
|
((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
|
||||||
|
(((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
|
||||||
|
(((__LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB))
|
||||||
|
|
||||||
|
#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & EXTI_MODE_MASK) != 0x00u) && \
|
||||||
|
(((__LINE__) & ~EXTI_MODE_MASK) == 0x00u))
|
||||||
|
|
||||||
|
#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
|
||||||
|
|
||||||
|
#define IS_EXTI_PENDING_EDGE(__LINE__) ((__LINE__) == EXTI_TRIGGER_RISING_FALLING)
|
||||||
|
|
||||||
|
#define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00u)
|
||||||
|
|
||||||
|
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
|
||||||
|
((__PORT__) == EXTI_GPIOB) || \
|
||||||
|
((__PORT__) == EXTI_GPIOC) || \
|
||||||
|
((__PORT__) == EXTI_GPIOD) || \
|
||||||
|
((__PORT__) == EXTI_GPIOE) || \
|
||||||
|
((__PORT__) == EXTI_GPIOF) || \
|
||||||
|
((__PORT__) == EXTI_GPIOG) || \
|
||||||
|
((__PORT__) == EXTI_GPIOH) || \
|
||||||
|
((__PORT__) == EXTI_GPIOI))
|
||||||
|
|
||||||
|
#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
/** @defgroup EXTI_Exported_Functions EXTI Exported Functions
|
||||||
|
* @brief EXTI Exported Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
|
||||||
|
* @brief Configuration functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* Configuration functions ****************************************************/
|
||||||
|
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
|
||||||
|
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
|
||||||
|
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
|
||||||
|
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
|
||||||
|
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
|
||||||
|
* @brief IO operation functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* IO operation functions *****************************************************/
|
||||||
|
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
|
||||||
|
uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
|
||||||
|
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
|
||||||
|
void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* STM32F2xx_HAL_EXTI_H */
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
@ -6,32 +6,16 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
#ifndef __STM32F2xx_HAL_FLASH_H
|
#ifndef __STM32F2xx_HAL_FLASH_H
|
||||||
|
|
|
@ -6,32 +6,16 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
#ifndef __STM32F2xx_HAL_FLASH_EX_H
|
#ifndef __STM32F2xx_HAL_FLASH_EX_H
|
||||||
|
|
|
@ -6,32 +6,16 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
#ifndef __STM32F2xx_HAL_GPIO_H
|
#ifndef __STM32F2xx_HAL_GPIO_H
|
||||||
|
@ -278,7 +262,7 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
|
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
|
||||||
#define IS_GPIO_PIN(PIN) ((((PIN) & GPIO_PIN_MASK ) != 0x00U) && (((PIN) & ~GPIO_PIN_MASK) == 0x00U))
|
#define IS_GPIO_PIN(PIN) (((((uint32_t)PIN) & GPIO_PIN_MASK ) != 0x00U) && ((((uint32_t)PIN) & ~GPIO_PIN_MASK) == 0x00U))
|
||||||
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\
|
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\
|
||||||
((MODE) == GPIO_MODE_OUTPUT_PP) ||\
|
((MODE) == GPIO_MODE_OUTPUT_PP) ||\
|
||||||
((MODE) == GPIO_MODE_OUTPUT_OD) ||\
|
((MODE) == GPIO_MODE_OUTPUT_OD) ||\
|
||||||
|
|
|
@ -6,32 +6,16 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
#ifndef __STM32F2xx_HAL_GPIO_EX_H
|
#ifndef __STM32F2xx_HAL_GPIO_EX_H
|
||||||
|
|
|
@ -6,32 +6,16 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
#ifndef __STM32F2xx_HAL_PWR_H
|
#ifndef __STM32F2xx_HAL_PWR_H
|
||||||
|
|
|
@ -6,32 +6,16 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
#ifndef __STM32F2xx_HAL_PWR_EX_H
|
#ifndef __STM32F2xx_HAL_PWR_EX_H
|
||||||
|
|
|
@ -6,29 +6,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -6,32 +6,16 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
#ifndef __STM32F2xx_HAL_RCC_EX_H
|
#ifndef __STM32F2xx_HAL_RCC_EX_H
|
||||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -2,43 +2,27 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @file stm32f2xx_hal_tim_ex.h
|
* @file stm32f2xx_hal_tim_ex.h
|
||||||
* @author MCD Application Team
|
* @author MCD Application Team
|
||||||
* @brief Header file of TIM HAL Extension module.
|
* @brief Header file of TIM HAL Extended module.
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
#ifndef __STM32F2xx_HAL_TIM_EX_H
|
#ifndef STM32F2xx_HAL_TIM_EX_H
|
||||||
#define __STM32F2xx_HAL_TIM_EX_H
|
#define STM32F2xx_HAL_TIM_EX_H
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
extern "C" {
|
extern "C" {
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
@ -50,291 +34,250 @@
|
||||||
|
|
||||||
/** @addtogroup TIMEx
|
/** @addtogroup TIMEx
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Exported types ------------------------------------------------------------*/
|
/* Exported types ------------------------------------------------------------*/
|
||||||
/** @defgroup TIMEx_Exported_Types TIM Exported Types
|
/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief TIM Hall sensor Configuration Structure definition
|
* @brief TIM Hall sensor Configuration Structure definition
|
||||||
*/
|
*/
|
||||||
|
|
||||||
typedef struct
|
typedef struct
|
||||||
{
|
{
|
||||||
|
uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
|
||||||
uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
|
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
|
||||||
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
|
|
||||||
|
|
||||||
uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
|
uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
|
||||||
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
|
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
|
||||||
|
|
||||||
uint32_t IC1Filter; /*!< Specifies the input capture filter.
|
uint32_t IC1Filter; /*!< Specifies the input capture filter.
|
||||||
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
|
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
|
||||||
uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
|
|
||||||
This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
|
uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
|
||||||
|
This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
|
||||||
} TIM_HallSensor_InitTypeDef;
|
} TIM_HallSensor_InitTypeDef;
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief TIM Master configuration Structure definition
|
|
||||||
*/
|
|
||||||
typedef struct {
|
|
||||||
uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection.
|
|
||||||
This parameter can be a value of @ref TIM_Master_Mode_Selection */
|
|
||||||
uint32_t MasterSlaveMode; /*!< Master/slave mode selection.
|
|
||||||
This parameter can be a value of @ref TIM_Master_Slave_Mode */
|
|
||||||
}TIM_MasterConfigTypeDef;
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief TIM Break and Dead time configuration Structure definition
|
|
||||||
*/
|
|
||||||
typedef struct
|
|
||||||
{
|
|
||||||
uint32_t OffStateRunMode; /*!< TIM off state in run mode.
|
|
||||||
This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
|
|
||||||
uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode.
|
|
||||||
This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
|
|
||||||
uint32_t LockLevel; /*!< TIM Lock level.
|
|
||||||
This parameter can be a value of @ref TIM_Lock_level */
|
|
||||||
uint32_t DeadTime; /*!< TIM dead Time.
|
|
||||||
This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
|
|
||||||
uint32_t BreakState; /*!< TIM Break State.
|
|
||||||
This parameter can be a value of @ref TIM_Break_Input_enable_disable */
|
|
||||||
uint32_t BreakPolarity; /*!< TIM Break input polarity.
|
|
||||||
This parameter can be a value of @ref TIM_Break_Polarity */
|
|
||||||
uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state.
|
|
||||||
This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
|
|
||||||
}TIM_BreakDeadTimeConfigTypeDef;
|
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
/* End of exported types -----------------------------------------------------*/
|
||||||
|
|
||||||
/* Exported constants --------------------------------------------------------*/
|
/* Exported constants --------------------------------------------------------*/
|
||||||
/** @defgroup TIMEx_Exported_Constants TIM Exported Constants
|
/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/** @defgroup TIMEx_Remap TIM Remap
|
/** @defgroup TIMEx_Remap TIM Extended Remapping
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
#define TIM_TIM2_TIM8_TRGO 0x00000000U
|
#define TIM_TIM2_TIM8_TRGO 0x00000000U /*!< TIM2 ITR1 is connected to TIM8 TRGO */
|
||||||
#define TIM_TIM2_ETH_PTP 0x00000400U
|
#define TIM_TIM2_ETH_PTP TIM_OR_ITR1_RMP_0 /*!< TIM2 ITR1 is connected to PTP trigger output */
|
||||||
#define TIM_TIM2_USBFS_SOF 0x00000800U
|
#define TIM_TIM2_USBFS_SOF TIM_OR_ITR1_RMP_1 /*!< TIM2 ITR1 is connected to OTG FS SOF */
|
||||||
#define TIM_TIM2_USBHS_SOF 0x00000C00U
|
#define TIM_TIM2_USBHS_SOF (TIM_OR_ITR1_RMP_1 | TIM_OR_ITR1_RMP_0) /*!< TIM2 ITR1 is connected to OTG HS SOF */
|
||||||
#define TIM_TIM5_GPIO 0x00000000U
|
|
||||||
#define TIM_TIM5_LSI 0x00000040U
|
#define TIM_TIM5_GPIO 0x00000000U /*!< TIM5 TI4 is connected to GPIO */
|
||||||
#define TIM_TIM5_LSE 0x00000080U
|
#define TIM_TIM5_LSI TIM_OR_TI4_RMP_0 /*!< TIM5 TI4 is connected to LSI */
|
||||||
#define TIM_TIM5_RTC 0x000000C0U
|
#define TIM_TIM5_LSE TIM_OR_TI4_RMP_1 /*!< TIM5 TI4 is connected to LSE */
|
||||||
#define TIM_TIM11_GPIO 0x00000000U
|
#define TIM_TIM5_RTC (TIM_OR_TI4_RMP_1 | TIM_OR_TI4_RMP_0) /*!< TIM5 TI4 is connected to the RTC wakeup interrupt */
|
||||||
#define TIM_TIM11_HSE 0x00000002U
|
|
||||||
|
#define TIM_TIM11_GPIO 0x00000000U /*!< TIM11 TI1 is connected to GPIO */
|
||||||
|
#define TIM_TIM11_HSE TIM_OR_TI1_RMP_1 /*!< TIM11 TI1 is connected to HSE_RTC clock */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
/* End of exported constants -------------------------------------------------*/
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Exported macro ------------------------------------------------------------*/
|
/* Exported macro ------------------------------------------------------------*/
|
||||||
/* Exported functions --------------------------------------------------------*/
|
/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
|
||||||
/** @addtogroup TIMEx_Exported_Functions
|
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/** @addtogroup TIMEx_Exported_Functions_Group1
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
/* End of exported macro -----------------------------------------------------*/
|
||||||
|
|
||||||
|
/* Private macro -------------------------------------------------------------*/
|
||||||
|
/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \
|
||||||
|
((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO) || \
|
||||||
|
((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || \
|
||||||
|
((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || \
|
||||||
|
(((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \
|
||||||
|
((TIM_REMAP) == TIM_TIM5_LSI) || \
|
||||||
|
((TIM_REMAP) == TIM_TIM5_LSE) || \
|
||||||
|
((TIM_REMAP) == TIM_TIM5_RTC))) || \
|
||||||
|
(((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \
|
||||||
|
((TIM_REMAP) == TIM_TIM11_HSE))))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
/* End of private macro ------------------------------------------------------*/
|
||||||
|
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
|
||||||
|
* @brief Timer Hall Sensor functions
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
/* Timer Hall Sensor functions **********************************************/
|
/* Timer Hall Sensor functions **********************************************/
|
||||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef* htim, TIM_HallSensor_InitTypeDef* sConfig);
|
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);
|
||||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef* htim);
|
HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
|
||||||
|
|
||||||
void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef* htim);
|
void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
|
||||||
void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef* htim);
|
void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
|
||||||
|
|
||||||
/* Blocking mode: Polling */
|
/* Blocking mode: Polling */
|
||||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef* htim);
|
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
|
||||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef* htim);
|
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
|
||||||
/* Non-Blocking mode: Interrupt */
|
/* Non-Blocking mode: Interrupt */
|
||||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef* htim);
|
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
|
||||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef* htim);
|
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
|
||||||
/* Non-Blocking mode: DMA */
|
/* Non-Blocking mode: DMA */
|
||||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef* htim, uint32_t *pData, uint16_t Length);
|
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
|
||||||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef* htim);
|
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/** @addtogroup TIMEx_Exported_Functions_Group2
|
/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
|
||||||
|
* @brief Timer Complementary Output Compare functions
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
/* Timer Complementary Output Compare functions *****************************/
|
/* Timer Complementary Output Compare functions *****************************/
|
||||||
/* Blocking mode: Polling */
|
/* Blocking mode: Polling */
|
||||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef* htim, uint32_t Channel);
|
HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef* htim, uint32_t Channel);
|
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||||
|
|
||||||
/* Non-Blocking mode: Interrupt */
|
/* Non-Blocking mode: Interrupt */
|
||||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
|
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
|
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||||
|
|
||||||
/* Non-Blocking mode: DMA */
|
/* Non-Blocking mode: DMA */
|
||||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef* htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
|
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
|
||||||
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef* htim, uint32_t Channel);
|
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/** @addtogroup TIMEx_Exported_Functions_Group3
|
/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
|
||||||
|
* @brief Timer Complementary PWM functions
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
/* Timer Complementary PWM functions ****************************************/
|
/* Timer Complementary PWM functions ****************************************/
|
||||||
/* Blocking mode: Polling */
|
/* Blocking mode: Polling */
|
||||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef* htim, uint32_t Channel);
|
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef* htim, uint32_t Channel);
|
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||||
|
|
||||||
/* Non-Blocking mode: Interrupt */
|
/* Non-Blocking mode: Interrupt */
|
||||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
|
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t Channel);
|
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||||
/* Non-Blocking mode: DMA */
|
/* Non-Blocking mode: DMA */
|
||||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef* htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
|
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
|
||||||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef* htim, uint32_t Channel);
|
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/** @addtogroup TIMEx_Exported_Functions_Group4
|
/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
|
||||||
|
* @brief Timer Complementary One Pulse functions
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
/* Timer Complementary One Pulse functions **********************************/
|
/* Timer Complementary One Pulse functions **********************************/
|
||||||
/* Blocking mode: Polling */
|
/* Blocking mode: Polling */
|
||||||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
|
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
|
||||||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
|
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
|
||||||
|
|
||||||
/* Non-Blocking mode: Interrupt */
|
/* Non-Blocking mode: Interrupt */
|
||||||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
|
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
|
||||||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t OutputChannel);
|
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/** @addtogroup TIMEx_Exported_Functions_Group5
|
/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
|
||||||
|
* @brief Peripheral Control functions
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
/* Extension Control functions ************************************************/
|
/* Extended Control functions ************************************************/
|
||||||
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef* htim, uint32_t InputTrigger, uint32_t CommutationSource);
|
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
|
||||||
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef* htim, uint32_t InputTrigger, uint32_t CommutationSource);
|
uint32_t CommutationSource);
|
||||||
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef* htim, uint32_t InputTrigger, uint32_t CommutationSource);
|
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
|
||||||
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef* htim, TIM_MasterConfigTypeDef * sMasterConfig);
|
uint32_t CommutationSource);
|
||||||
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef* htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
|
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
|
||||||
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef* htim, uint32_t Remap);
|
uint32_t CommutationSource);
|
||||||
|
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
|
||||||
|
TIM_MasterConfigTypeDef *sMasterConfig);
|
||||||
|
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
|
||||||
|
TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
|
||||||
|
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/** @addtogroup TIMEx_Exported_Functions_Group6
|
/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
|
||||||
|
* @brief Extended Callbacks functions
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
/* Extension Callback *********************************************************/
|
/* Extended Callback **********************************************************/
|
||||||
void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef* htim);
|
void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim);
|
||||||
void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef* htim);
|
void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim);
|
||||||
|
void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
|
||||||
|
* @brief Extended Peripheral State functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/* Extended Peripheral State functions ***************************************/
|
||||||
|
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
/* End of exported functions -------------------------------------------------*/
|
||||||
|
|
||||||
|
/* Private functions----------------------------------------------------------*/
|
||||||
|
/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
|
void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
|
||||||
|
void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
/* End of private functions --------------------------------------------------*/
|
||||||
|
|
||||||
/** @addtogroup TIMEx_Exported_Functions_Group7
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
/* Extension Peripheral State functions **************************************/
|
|
||||||
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef* htim);
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private types -------------------------------------------------------------*/
|
|
||||||
/* Private variables ---------------------------------------------------------*/
|
|
||||||
/* Private constants ---------------------------------------------------------*/
|
|
||||||
/* Private macros ------------------------------------------------------------*/
|
|
||||||
/** @defgroup TIMEx_Private_Macros TIM Private Macros
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO)||\
|
|
||||||
((TIM_REMAP) == TIM_TIM2_ETH_PTP)||\
|
|
||||||
((TIM_REMAP) == TIM_TIM2_USBFS_SOF)||\
|
|
||||||
((TIM_REMAP) == TIM_TIM2_USBHS_SOF)||\
|
|
||||||
((TIM_REMAP) == TIM_TIM5_GPIO)||\
|
|
||||||
((TIM_REMAP) == TIM_TIM5_LSI)||\
|
|
||||||
((TIM_REMAP) == TIM_TIM5_LSE)||\
|
|
||||||
((TIM_REMAP) == TIM_TIM5_RTC)||\
|
|
||||||
((TIM_REMAP) == TIM_TIM11_GPIO)||\
|
|
||||||
((TIM_REMAP) == TIM_TIM11_HSE))
|
|
||||||
|
|
||||||
#define IS_TIM_DEADTIME(DEADTIME) ((DEADTIME) <= 0xFFU)
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Sets the TIM Output compare preload.
|
|
||||||
* @param __HANDLE__ TIM handle.
|
|
||||||
* @param __CHANNEL__ TIM Channels to be configured.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
||||||
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
||||||
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
|
||||||
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
|
|
||||||
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
|
|
||||||
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
|
|
||||||
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
|
|
||||||
((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @brief Resets the TIM Output compare preload.
|
|
||||||
* @param __HANDLE__ TIM handle.
|
|
||||||
* @param __CHANNEL__ TIM Channels to be configured.
|
|
||||||
* This parameter can be one of the following values:
|
|
||||||
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
|
|
||||||
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
|
|
||||||
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
|
|
||||||
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
|
|
||||||
* @retval None
|
|
||||||
*/
|
|
||||||
#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
|
|
||||||
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\
|
|
||||||
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\
|
|
||||||
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\
|
|
||||||
((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Private functions ---------------------------------------------------------*/
|
|
||||||
/** @defgroup TIMEx_Private_Functions TIM Private Functions
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/**
|
|
||||||
* @}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#endif /* __STM32F2xx_HAL_TIM_EX_H */
|
|
||||||
|
#endif /* STM32F2xx_HAL_TIM_EX_H */
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
|
|
|
@ -23,29 +23,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -22,29 +22,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -6,29 +6,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -6,29 +6,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -6,29 +6,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -6,29 +6,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -6,29 +6,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -6,36 +6,20 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||||
#ifndef __STM32F2xx_LL_SPI_H
|
#ifndef STM32F2xx_LL_SPI_H
|
||||||
#define __STM32F2xx_LL_SPI_H
|
#define STM32F2xx_LL_SPI_H
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
extern "C" {
|
extern "C" {
|
||||||
|
@ -162,7 +146,7 @@ typedef struct
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */
|
#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */
|
||||||
#define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */
|
#define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
@ -252,8 +236,8 @@ typedef struct
|
||||||
/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
|
/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
#define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled */
|
#define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled */
|
||||||
#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled */
|
#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled */
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
@ -336,7 +320,7 @@ __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
|
__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
|
||||||
{
|
{
|
||||||
return (READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE));
|
return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -628,7 +612,7 @@ __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
|
__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
|
||||||
{
|
{
|
||||||
return (READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN));
|
return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL);
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -747,7 +731,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
|
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
|
||||||
{
|
{
|
||||||
return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE));
|
return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL);
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -758,7 +742,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
|
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
|
||||||
{
|
{
|
||||||
return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE));
|
return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL);
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -769,7 +753,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
|
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
|
||||||
{
|
{
|
||||||
return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR));
|
return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL);
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -780,7 +764,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
|
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
|
||||||
{
|
{
|
||||||
return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF));
|
return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -791,7 +775,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
|
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
|
||||||
{
|
{
|
||||||
return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR));
|
return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -809,7 +793,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
|
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
|
||||||
{
|
{
|
||||||
return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY));
|
return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL);
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -820,7 +804,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
|
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
|
||||||
{
|
{
|
||||||
return (READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE));
|
return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL);
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -844,11 +828,10 @@ __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
|
__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
|
||||||
{
|
{
|
||||||
__IO uint32_t tmpreg;
|
__IO uint32_t tmpreg_sr;
|
||||||
tmpreg = SPIx->SR;
|
tmpreg_sr = SPIx->SR;
|
||||||
(void) tmpreg;
|
(void) tmpreg_sr;
|
||||||
tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
|
CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
|
||||||
(void) tmpreg;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -966,7 +949,7 @@ __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
|
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
|
||||||
{
|
{
|
||||||
return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE));
|
return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL);
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -977,7 +960,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
|
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
|
||||||
{
|
{
|
||||||
return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE));
|
return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL);
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -988,7 +971,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
|
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
|
||||||
{
|
{
|
||||||
return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE));
|
return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL);
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -1029,7 +1012,7 @@ __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
|
__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
|
||||||
{
|
{
|
||||||
return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN));
|
return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL);
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -1062,7 +1045,7 @@ __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
|
__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
|
||||||
{
|
{
|
||||||
return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN));
|
return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL);
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -1073,7 +1056,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
|
__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
|
||||||
{
|
{
|
||||||
return (uint32_t) & (SPIx->DR);
|
return (uint32_t) &(SPIx->DR);
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -1115,7 +1098,12 @@ __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
|
__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
|
||||||
{
|
{
|
||||||
SPIx->DR = TxData;
|
#if defined (__GNUC__)
|
||||||
|
__IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR);
|
||||||
|
*spidr = TxData;
|
||||||
|
#else
|
||||||
|
*((__IO uint8_t *)&SPIx->DR) = TxData;
|
||||||
|
#endif /* __GNUC__ */
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -1127,7 +1115,12 @@ __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
|
__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
|
||||||
{
|
{
|
||||||
|
#if defined (__GNUC__)
|
||||||
|
__IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR);
|
||||||
|
*spidr = TxData;
|
||||||
|
#else
|
||||||
SPIx->DR = TxData;
|
SPIx->DR = TxData;
|
||||||
|
#endif /* __GNUC__ */
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -1313,16 +1306,16 @@ typedef struct
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#define LL_I2S_AUDIOFREQ_192K 192000U /*!< Audio Frequency configuration 192000 Hz */
|
#define LL_I2S_AUDIOFREQ_192K 192000U /*!< Audio Frequency configuration 192000 Hz */
|
||||||
#define LL_I2S_AUDIOFREQ_96K 96000U /*!< Audio Frequency configuration 96000 Hz */
|
#define LL_I2S_AUDIOFREQ_96K 96000U /*!< Audio Frequency configuration 96000 Hz */
|
||||||
#define LL_I2S_AUDIOFREQ_48K 48000U /*!< Audio Frequency configuration 48000 Hz */
|
#define LL_I2S_AUDIOFREQ_48K 48000U /*!< Audio Frequency configuration 48000 Hz */
|
||||||
#define LL_I2S_AUDIOFREQ_44K 44100U /*!< Audio Frequency configuration 44100 Hz */
|
#define LL_I2S_AUDIOFREQ_44K 44100U /*!< Audio Frequency configuration 44100 Hz */
|
||||||
#define LL_I2S_AUDIOFREQ_32K 32000U /*!< Audio Frequency configuration 32000 Hz */
|
#define LL_I2S_AUDIOFREQ_32K 32000U /*!< Audio Frequency configuration 32000 Hz */
|
||||||
#define LL_I2S_AUDIOFREQ_22K 22050U /*!< Audio Frequency configuration 22050 Hz */
|
#define LL_I2S_AUDIOFREQ_22K 22050U /*!< Audio Frequency configuration 22050 Hz */
|
||||||
#define LL_I2S_AUDIOFREQ_16K 16000U /*!< Audio Frequency configuration 16000 Hz */
|
#define LL_I2S_AUDIOFREQ_16K 16000U /*!< Audio Frequency configuration 16000 Hz */
|
||||||
#define LL_I2S_AUDIOFREQ_11K 11025U /*!< Audio Frequency configuration 11025 Hz */
|
#define LL_I2S_AUDIOFREQ_11K 11025U /*!< Audio Frequency configuration 11025 Hz */
|
||||||
#define LL_I2S_AUDIOFREQ_8K 8000U /*!< Audio Frequency configuration 8000 Hz */
|
#define LL_I2S_AUDIOFREQ_8K 8000U /*!< Audio Frequency configuration 8000 Hz */
|
||||||
#define LL_I2S_AUDIOFREQ_DEFAULT 2U /*!< Audio Freq not specified. Register I2SDIV = 2 */
|
#define LL_I2S_AUDIOFREQ_DEFAULT 2U /*!< Audio Freq not specified. Register I2SDIV = 2 */
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
@ -1407,7 +1400,7 @@ __STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
|
__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
|
||||||
{
|
{
|
||||||
return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE));
|
return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE)) ? 1UL : 0UL);
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -1616,7 +1609,7 @@ __STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
|
__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
|
||||||
{
|
{
|
||||||
return (READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE));
|
return ((READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE)) ? 1UL : 0UL);
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -1679,7 +1672,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
|
__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
|
||||||
{
|
{
|
||||||
return (READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR));
|
return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL);
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -1704,7 +1697,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
|
__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
|
||||||
{
|
{
|
||||||
return (READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE));
|
return ((READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE)) ? 1UL : 0UL);
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -1993,6 +1986,6 @@ void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear,
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#endif /* __STM32F2xx_LL_SPI_H */
|
#endif /* STM32F2xx_LL_SPI_H */
|
||||||
|
|
||||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||||
|
|
|
@ -18,29 +18,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -6,29 +6,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
@ -215,7 +199,7 @@ typedef struct
|
||||||
|
|
||||||
/** @defgroup USART_LL_EC_PARITY Parity Control
|
/** @defgroup USART_LL_EC_PARITY Parity Control
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
#define LL_USART_PARITY_NONE 0x00000000U /*!< Parity control disabled */
|
#define LL_USART_PARITY_NONE 0x00000000U /*!< Parity control disabled */
|
||||||
#define LL_USART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */
|
#define LL_USART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */
|
||||||
#define LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */
|
#define LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */
|
||||||
|
@ -391,7 +375,7 @@ typedef struct
|
||||||
*/
|
*/
|
||||||
#define __LL_USART_DIV_SAMPLING16_100(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__)*25)/(4*(__BAUDRATE__)))
|
#define __LL_USART_DIV_SAMPLING16_100(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__)*25)/(4*(__BAUDRATE__)))
|
||||||
#define __LL_USART_DIVMANT_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__))/100)
|
#define __LL_USART_DIVMANT_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__))/100)
|
||||||
#define __LL_USART_DIVFRAQ_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 16 + 50) / 100)
|
#define __LL_USART_DIVFRAQ_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) ((((__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 16) + 50) / 100)
|
||||||
/* USART BRR = mantissa + overflow + fraction
|
/* USART BRR = mantissa + overflow + fraction
|
||||||
= (USART DIVMANT << 4) + (USART DIVFRAQ & 0xF0) + (USART DIVFRAQ & 0x0F) */
|
= (USART DIVMANT << 4) + (USART DIVFRAQ & 0xF0) + (USART DIVFRAQ & 0x0F) */
|
||||||
#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \
|
#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \
|
||||||
|
@ -1883,7 +1867,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx)
|
||||||
* @brief Clear Parity Error Flag
|
* @brief Clear Parity Error Flag
|
||||||
* @note Clearing this flag is done by a read access to the USARTx_SR
|
* @note Clearing this flag is done by a read access to the USARTx_SR
|
||||||
* register followed by a read access to the USARTx_DR register.
|
* register followed by a read access to the USARTx_DR register.
|
||||||
* @note Please also consider that when clearing this flag, other flags as
|
* @note Please also consider that when clearing this flag, other flags as
|
||||||
* NE, FE, ORE, IDLE would also be cleared.
|
* NE, FE, ORE, IDLE would also be cleared.
|
||||||
* @rmtoll SR PE LL_USART_ClearFlag_PE
|
* @rmtoll SR PE LL_USART_ClearFlag_PE
|
||||||
* @param USARTx USART Instance
|
* @param USARTx USART Instance
|
||||||
|
@ -1902,7 +1886,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx)
|
||||||
* @brief Clear Framing Error Flag
|
* @brief Clear Framing Error Flag
|
||||||
* @note Clearing this flag is done by a read access to the USARTx_SR
|
* @note Clearing this flag is done by a read access to the USARTx_SR
|
||||||
* register followed by a read access to the USARTx_DR register.
|
* register followed by a read access to the USARTx_DR register.
|
||||||
* @note Please also consider that when clearing this flag, other flags as
|
* @note Please also consider that when clearing this flag, other flags as
|
||||||
* PE, NE, ORE, IDLE would also be cleared.
|
* PE, NE, ORE, IDLE would also be cleared.
|
||||||
* @rmtoll SR FE LL_USART_ClearFlag_FE
|
* @rmtoll SR FE LL_USART_ClearFlag_FE
|
||||||
* @param USARTx USART Instance
|
* @param USARTx USART Instance
|
||||||
|
@ -1921,7 +1905,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx)
|
||||||
* @brief Clear Noise detected Flag
|
* @brief Clear Noise detected Flag
|
||||||
* @note Clearing this flag is done by a read access to the USARTx_SR
|
* @note Clearing this flag is done by a read access to the USARTx_SR
|
||||||
* register followed by a read access to the USARTx_DR register.
|
* register followed by a read access to the USARTx_DR register.
|
||||||
* @note Please also consider that when clearing this flag, other flags as
|
* @note Please also consider that when clearing this flag, other flags as
|
||||||
* PE, FE, ORE, IDLE would also be cleared.
|
* PE, FE, ORE, IDLE would also be cleared.
|
||||||
* @rmtoll SR NF LL_USART_ClearFlag_NE
|
* @rmtoll SR NF LL_USART_ClearFlag_NE
|
||||||
* @param USARTx USART Instance
|
* @param USARTx USART Instance
|
||||||
|
@ -1940,7 +1924,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx)
|
||||||
* @brief Clear OverRun Error Flag
|
* @brief Clear OverRun Error Flag
|
||||||
* @note Clearing this flag is done by a read access to the USARTx_SR
|
* @note Clearing this flag is done by a read access to the USARTx_SR
|
||||||
* register followed by a read access to the USARTx_DR register.
|
* register followed by a read access to the USARTx_DR register.
|
||||||
* @note Please also consider that when clearing this flag, other flags as
|
* @note Please also consider that when clearing this flag, other flags as
|
||||||
* PE, NE, FE, IDLE would also be cleared.
|
* PE, NE, FE, IDLE would also be cleared.
|
||||||
* @rmtoll SR ORE LL_USART_ClearFlag_ORE
|
* @rmtoll SR ORE LL_USART_ClearFlag_ORE
|
||||||
* @param USARTx USART Instance
|
* @param USARTx USART Instance
|
||||||
|
@ -1959,7 +1943,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx)
|
||||||
* @brief Clear IDLE line detected Flag
|
* @brief Clear IDLE line detected Flag
|
||||||
* @note Clearing this flag is done by a read access to the USARTx_SR
|
* @note Clearing this flag is done by a read access to the USARTx_SR
|
||||||
* register followed by a read access to the USARTx_DR register.
|
* register followed by a read access to the USARTx_DR register.
|
||||||
* @note Please also consider that when clearing this flag, other flags as
|
* @note Please also consider that when clearing this flag, other flags as
|
||||||
* PE, NE, FE, ORE would also be cleared.
|
* PE, NE, FE, ORE would also be cleared.
|
||||||
* @rmtoll SR IDLE LL_USART_ClearFlag_IDLE
|
* @rmtoll SR IDLE LL_USART_ClearFlag_IDLE
|
||||||
* @param USARTx USART Instance
|
* @param USARTx USART Instance
|
||||||
|
@ -1982,7 +1966,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)
|
__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)
|
||||||
{
|
{
|
||||||
WRITE_REG(USARTx->SR , ~(USART_SR_TC));
|
WRITE_REG(USARTx->SR, ~(USART_SR_TC));
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -1993,7 +1977,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void LL_USART_ClearFlag_RXNE(USART_TypeDef *USARTx)
|
__STATIC_INLINE void LL_USART_ClearFlag_RXNE(USART_TypeDef *USARTx)
|
||||||
{
|
{
|
||||||
WRITE_REG(USARTx->SR , ~(USART_SR_RXNE));
|
WRITE_REG(USARTx->SR, ~(USART_SR_RXNE));
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -2006,7 +1990,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_RXNE(USART_TypeDef *USARTx)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)
|
__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)
|
||||||
{
|
{
|
||||||
WRITE_REG(USARTx->SR , ~(USART_SR_LBD));
|
WRITE_REG(USARTx->SR, ~(USART_SR_LBD));
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -2019,7 +2003,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx)
|
__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx)
|
||||||
{
|
{
|
||||||
WRITE_REG(USARTx->SR , ~(USART_SR_CTS));
|
WRITE_REG(USARTx->SR, ~(USART_SR_CTS));
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -2398,7 +2382,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx)
|
||||||
__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx)
|
__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx)
|
||||||
{
|
{
|
||||||
/* return address of DR register */
|
/* return address of DR register */
|
||||||
return ((uint32_t) &(USARTx->DR));
|
return ((uint32_t) & (USARTx->DR));
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
|
@ -18,29 +18,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
@ -217,7 +201,7 @@ __STATIC_INLINE uint32_t LL_GetUID_Word2(void)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t LL_GetFlashSize(void)
|
__STATIC_INLINE uint32_t LL_GetFlashSize(void)
|
||||||
{
|
{
|
||||||
return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)));
|
return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0xFFFF);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
|
@ -21,32 +21,16 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
/* Includes ------------------------------------------------------------------*/
|
||||||
#include "stm32f2xx_hal.h"
|
#include "stm32f2xx_hal.h"
|
||||||
|
@ -66,11 +50,11 @@
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
/**
|
/**
|
||||||
* @brief STM32F2xx HAL Driver version number V1.2.1
|
* @brief STM32F2xx HAL Driver version number V1.2.4
|
||||||
*/
|
*/
|
||||||
#define __STM32F2xx_HAL_VERSION_MAIN 0x01U /*!< [31:24] main version */
|
#define __STM32F2xx_HAL_VERSION_MAIN 0x01U /*!< [31:24] main version */
|
||||||
#define __STM32F2xx_HAL_VERSION_SUB1 0x02U /*!< [23:16] sub1 version */
|
#define __STM32F2xx_HAL_VERSION_SUB1 0x02U /*!< [23:16] sub1 version */
|
||||||
#define __STM32F2xx_HAL_VERSION_SUB2 0x01U /*!< [15:8] sub2 version */
|
#define __STM32F2xx_HAL_VERSION_SUB2 0x04U /*!< [15:8] sub2 version */
|
||||||
#define __STM32F2xx_HAL_VERSION_RC 0x00U /*!< [7:0] release candidate */
|
#define __STM32F2xx_HAL_VERSION_RC 0x00U /*!< [7:0] release candidate */
|
||||||
#define __STM32F2xx_HAL_VERSION ((__STM32F2xx_HAL_VERSION_MAIN << 24U)\
|
#define __STM32F2xx_HAL_VERSION ((__STM32F2xx_HAL_VERSION_MAIN << 24U)\
|
||||||
|(__STM32F2xx_HAL_VERSION_SUB1 << 16U)\
|
|(__STM32F2xx_HAL_VERSION_SUB1 << 16U)\
|
||||||
|
@ -97,11 +81,13 @@
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Private macro -------------------------------------------------------------*/
|
/* Private macro -------------------------------------------------------------*/
|
||||||
/* Private variables ---------------------------------------------------------*/
|
/* Exported variables ---------------------------------------------------------*/
|
||||||
/** @addtogroup HAL_Private_Variables
|
/** @addtogroup HAL_Exported_Variables
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
__IO uint32_t uwTick;
|
__IO uint32_t uwTick;
|
||||||
|
uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
|
||||||
|
HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
@ -260,11 +246,22 @@ __weak void HAL_MspDeInit(void)
|
||||||
*/
|
*/
|
||||||
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
||||||
{
|
{
|
||||||
/*Configure the SysTick to have interrupt in 1ms time basis*/
|
/* Configure the SysTick to have interrupt in 1ms time basis*/
|
||||||
HAL_SYSTICK_Config(SystemCoreClock/1000U);
|
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
|
||||||
|
{
|
||||||
|
return HAL_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
/*Configure the SysTick IRQ priority */
|
/* Configure the SysTick IRQ priority */
|
||||||
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0U);
|
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
|
||||||
|
{
|
||||||
|
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
|
||||||
|
uwTickPrio = TickPriority;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return HAL_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
/* Return function status */
|
/* Return function status */
|
||||||
return HAL_OK;
|
return HAL_OK;
|
||||||
|
@ -308,7 +305,7 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
||||||
*/
|
*/
|
||||||
__weak void HAL_IncTick(void)
|
__weak void HAL_IncTick(void)
|
||||||
{
|
{
|
||||||
uwTick++;
|
uwTick += uwTickFreq;
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -322,6 +319,46 @@ __weak uint32_t HAL_GetTick(void)
|
||||||
return uwTick;
|
return uwTick;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function returns a tick priority.
|
||||||
|
* @retval tick priority
|
||||||
|
*/
|
||||||
|
uint32_t HAL_GetTickPrio(void)
|
||||||
|
{
|
||||||
|
return uwTickPrio;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set new tick Freq.
|
||||||
|
* @retval status
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
|
||||||
|
{
|
||||||
|
HAL_StatusTypeDef status = HAL_OK;
|
||||||
|
assert_param(IS_TICKFREQ(Freq));
|
||||||
|
|
||||||
|
if (uwTickFreq != Freq)
|
||||||
|
{
|
||||||
|
/* Apply the new tick Freq */
|
||||||
|
status = HAL_InitTick(uwTickPrio);
|
||||||
|
if (status == HAL_OK)
|
||||||
|
{
|
||||||
|
uwTickFreq = Freq;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief return tick frequency.
|
||||||
|
* @retval tick period in Hz
|
||||||
|
*/
|
||||||
|
HAL_TickFreqTypeDef HAL_GetTickFreq(void)
|
||||||
|
{
|
||||||
|
return uwTickFreq;
|
||||||
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief This function provides minimum delay (in milliseconds) based
|
* @brief This function provides minimum delay (in milliseconds) based
|
||||||
* on variable incremented.
|
* on variable incremented.
|
||||||
|
@ -337,14 +374,14 @@ __weak void HAL_Delay(__IO uint32_t Delay)
|
||||||
{
|
{
|
||||||
uint32_t tickstart = HAL_GetTick();
|
uint32_t tickstart = HAL_GetTick();
|
||||||
uint32_t wait = Delay;
|
uint32_t wait = Delay;
|
||||||
|
|
||||||
/* Add a period to guarantee minimum wait */
|
/* Add a freq to guarantee minimum wait */
|
||||||
if (wait < HAL_MAX_DELAY)
|
if (wait < HAL_MAX_DELAY)
|
||||||
{
|
{
|
||||||
wait++;
|
wait += (uint32_t)(uwTickFreq);
|
||||||
}
|
}
|
||||||
|
|
||||||
while((HAL_GetTick() - tickstart) < wait)
|
while ((HAL_GetTick() - tickstart) < wait)
|
||||||
{
|
{
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -485,15 +522,30 @@ void HAL_DisableCompensationCell(void)
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Return the unique device identifier (UID based on 96 bits)
|
* @brief Returns first word of the unique device identifier (UID based on 96 bits)
|
||||||
* @param UID pointer to 3 words array.
|
|
||||||
* @retval Device identifier
|
* @retval Device identifier
|
||||||
*/
|
*/
|
||||||
void HAL_GetUID(uint32_t *UID)
|
uint32_t HAL_GetUIDw0(void)
|
||||||
{
|
{
|
||||||
UID[0] = (uint32_t)(READ_REG(*((uint32_t *)UID_BASE)));
|
return (READ_REG(*((uint32_t *)UID_BASE)));
|
||||||
UID[1] = (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE + 4U))));
|
}
|
||||||
UID[2] = (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE + 8U))));
|
|
||||||
|
/**
|
||||||
|
* @brief Returns second word of the unique device identifier (UID based on 96 bits)
|
||||||
|
* @retval Device identifier
|
||||||
|
*/
|
||||||
|
uint32_t HAL_GetUIDw1(void)
|
||||||
|
{
|
||||||
|
return (READ_REG(*((uint32_t *)(UID_BASE + 4U))));
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Returns third word of the unique device identifier (UID based on 96 bits)
|
||||||
|
* @retval Device identifier
|
||||||
|
*/
|
||||||
|
uint32_t HAL_GetUIDw2(void)
|
||||||
|
{
|
||||||
|
return (READ_REG(*((uint32_t *)(UID_BASE + 8U))));
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -68,29 +68,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -83,32 +83,16 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
/* Includes ------------------------------------------------------------------*/
|
||||||
#include "stm32f2xx_hal.h"
|
#include "stm32f2xx_hal.h"
|
||||||
|
@ -367,13 +351,21 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
|
||||||
/* Get DMA steam Base Address */
|
/* Get DMA steam Base Address */
|
||||||
regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
|
regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
|
||||||
|
|
||||||
|
/* Clean all callbacks */
|
||||||
|
hdma->XferCpltCallback = NULL;
|
||||||
|
hdma->XferHalfCpltCallback = NULL;
|
||||||
|
hdma->XferM1CpltCallback = NULL;
|
||||||
|
hdma->XferM1HalfCpltCallback = NULL;
|
||||||
|
hdma->XferErrorCallback = NULL;
|
||||||
|
hdma->XferAbortCallback = NULL;
|
||||||
|
|
||||||
/* Clear all interrupt flags at correct offset within the register */
|
/* Clear all interrupt flags at correct offset within the register */
|
||||||
regs->IFCR = 0x3FU << hdma->StreamIndex;
|
regs->IFCR = 0x3FU << hdma->StreamIndex;
|
||||||
|
|
||||||
/* Initialize the error code */
|
/* Reset the error code */
|
||||||
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
||||||
|
|
||||||
/* Initialize the DMA state */
|
/* Reset the DMA state */
|
||||||
hdma->State = HAL_DMA_STATE_RESET;
|
hdma->State = HAL_DMA_STATE_RESET;
|
||||||
|
|
||||||
/* Release Lock */
|
/* Release Lock */
|
||||||
|
@ -486,7 +478,6 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress,
|
||||||
|
|
||||||
/* Enable Common interrupts*/
|
/* Enable Common interrupts*/
|
||||||
hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;
|
hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;
|
||||||
hdma->Instance->FCR |= DMA_IT_FE;
|
|
||||||
|
|
||||||
if(hdma->XferHalfCpltCallback != NULL)
|
if(hdma->XferHalfCpltCallback != NULL)
|
||||||
{
|
{
|
||||||
|
@ -1164,7 +1155,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t
|
||||||
/* Configure DMA Stream data length */
|
/* Configure DMA Stream data length */
|
||||||
hdma->Instance->NDTR = DataLength;
|
hdma->Instance->NDTR = DataLength;
|
||||||
|
|
||||||
/* Peripheral to Memory */
|
/* Memory to Peripheral */
|
||||||
if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
|
if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
|
||||||
{
|
{
|
||||||
/* Configure DMA Stream destination address */
|
/* Configure DMA Stream destination address */
|
||||||
|
@ -1173,7 +1164,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t
|
||||||
/* Configure DMA Stream source address */
|
/* Configure DMA Stream source address */
|
||||||
hdma->Instance->M0AR = SrcAddress;
|
hdma->Instance->M0AR = SrcAddress;
|
||||||
}
|
}
|
||||||
/* Memory to Peripheral */
|
/* Peripheral to Memory */
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
/* Configure DMA Stream source address */
|
/* Configure DMA Stream source address */
|
||||||
|
|
|
@ -25,29 +25,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -0,0 +1,559 @@
|
||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file stm32f2xx_hal_exti.c
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @brief EXTI HAL module driver.
|
||||||
|
* This file provides firmware functions to manage the following
|
||||||
|
* functionalities of the Extended Interrupts and events controller (EXTI) peripheral:
|
||||||
|
* + Initialization and de-initialization functions
|
||||||
|
* + IO operation functions
|
||||||
|
*
|
||||||
|
@verbatim
|
||||||
|
==============================================================================
|
||||||
|
##### EXTI Peripheral features #####
|
||||||
|
==============================================================================
|
||||||
|
[..]
|
||||||
|
(+) Each Exti line can be configured within this driver.
|
||||||
|
|
||||||
|
(+) Exti line can be configured in 3 different modes
|
||||||
|
(++) Interrupt
|
||||||
|
(++) Event
|
||||||
|
(++) Both of them
|
||||||
|
|
||||||
|
(+) Configurable Exti lines can be configured with 3 different triggers
|
||||||
|
(++) Rising
|
||||||
|
(++) Falling
|
||||||
|
(++) Both of them
|
||||||
|
|
||||||
|
(+) When set in interrupt mode, configurable Exti lines have two different
|
||||||
|
interrupts pending registers which allow to distinguish which transition
|
||||||
|
occurs:
|
||||||
|
(++) Rising edge pending interrupt
|
||||||
|
(++) Falling
|
||||||
|
|
||||||
|
(+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
|
||||||
|
be selected through multiplexer.
|
||||||
|
|
||||||
|
##### How to use this driver #####
|
||||||
|
==============================================================================
|
||||||
|
[..]
|
||||||
|
|
||||||
|
(#) Configure the EXTI line using HAL_EXTI_SetConfigLine().
|
||||||
|
(++) Choose the interrupt line number by setting "Line" member from
|
||||||
|
EXTI_ConfigTypeDef structure.
|
||||||
|
(++) Configure the interrupt and/or event mode using "Mode" member from
|
||||||
|
EXTI_ConfigTypeDef structure.
|
||||||
|
(++) For configurable lines, configure rising and/or falling trigger
|
||||||
|
"Trigger" member from EXTI_ConfigTypeDef structure.
|
||||||
|
(++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
|
||||||
|
member from GPIO_InitTypeDef structure.
|
||||||
|
|
||||||
|
(#) Get current Exti configuration of a dedicated line using
|
||||||
|
HAL_EXTI_GetConfigLine().
|
||||||
|
(++) Provide exiting handle as parameter.
|
||||||
|
(++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
|
||||||
|
|
||||||
|
(#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
|
||||||
|
(++) Provide exiting handle as parameter.
|
||||||
|
|
||||||
|
(#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
|
||||||
|
(++) Provide exiting handle as first parameter.
|
||||||
|
(++) Provide which callback will be registered using one value from
|
||||||
|
EXTI_CallbackIDTypeDef.
|
||||||
|
(++) Provide callback function pointer.
|
||||||
|
|
||||||
|
(#) Get interrupt pending bit using HAL_EXTI_GetPending().
|
||||||
|
|
||||||
|
(#) Clear interrupt pending bit using HAL_EXTI_GetPending().
|
||||||
|
|
||||||
|
(#) Generate software interrupt using HAL_EXTI_GenerateSWI().
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
|
*
|
||||||
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
|
* the "License"; You may not use this file except in compliance with the
|
||||||
|
* License. You may obtain a copy of the License at:
|
||||||
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
#include "stm32f2xx_hal.h"
|
||||||
|
|
||||||
|
/** @addtogroup STM32F2xx_HAL_Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup EXTI
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/** MISRA C:2012 deviation rule has been granted for following rule:
|
||||||
|
* Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out
|
||||||
|
* of bounds [0,3] in following API :
|
||||||
|
* HAL_EXTI_SetConfigLine
|
||||||
|
* HAL_EXTI_GetConfigLine
|
||||||
|
* HAL_EXTI_ClearConfigLine
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef HAL_EXTI_MODULE_ENABLED
|
||||||
|
|
||||||
|
/* Private typedef -----------------------------------------------------------*/
|
||||||
|
/* Private defines -----------------------------------------------------------*/
|
||||||
|
/** @defgroup EXTI_Private_Constants EXTI Private Constants
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Private macros ------------------------------------------------------------*/
|
||||||
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
/* Private function prototypes -----------------------------------------------*/
|
||||||
|
/* Exported functions --------------------------------------------------------*/
|
||||||
|
|
||||||
|
/** @addtogroup EXTI_Exported_Functions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup EXTI_Exported_Functions_Group1
|
||||||
|
* @brief Configuration functions
|
||||||
|
*
|
||||||
|
@verbatim
|
||||||
|
===============================================================================
|
||||||
|
##### Configuration functions #####
|
||||||
|
===============================================================================
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set configuration of a dedicated Exti line.
|
||||||
|
* @param hexti Exti handle.
|
||||||
|
* @param pExtiConfig Pointer on EXTI configuration to be set.
|
||||||
|
* @retval HAL Status.
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
|
||||||
|
{
|
||||||
|
uint32_t regval;
|
||||||
|
uint32_t linepos;
|
||||||
|
uint32_t maskline;
|
||||||
|
|
||||||
|
/* Check null pointer */
|
||||||
|
if ((hexti == NULL) || (pExtiConfig == NULL))
|
||||||
|
{
|
||||||
|
return HAL_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Check parameters */
|
||||||
|
assert_param(IS_EXTI_LINE(pExtiConfig->Line));
|
||||||
|
assert_param(IS_EXTI_MODE(pExtiConfig->Mode));
|
||||||
|
|
||||||
|
/* Assign line number to handle */
|
||||||
|
hexti->Line = pExtiConfig->Line;
|
||||||
|
|
||||||
|
/* Compute line mask */
|
||||||
|
linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
|
||||||
|
maskline = (1uL << linepos);
|
||||||
|
|
||||||
|
/* Configure triggers for configurable lines */
|
||||||
|
if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
|
||||||
|
{
|
||||||
|
assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
|
||||||
|
|
||||||
|
/* Configure rising trigger */
|
||||||
|
/* Mask or set line */
|
||||||
|
if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u)
|
||||||
|
{
|
||||||
|
EXTI->RTSR |= maskline;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
EXTI->RTSR &= ~maskline;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Configure falling trigger */
|
||||||
|
/* Mask or set line */
|
||||||
|
if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u)
|
||||||
|
{
|
||||||
|
EXTI->FTSR |= maskline;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
EXTI->FTSR &= ~maskline;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/* Configure gpio port selection in case of gpio exti line */
|
||||||
|
if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
|
||||||
|
{
|
||||||
|
assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel));
|
||||||
|
assert_param(IS_EXTI_GPIO_PIN(linepos));
|
||||||
|
|
||||||
|
regval = SYSCFG->EXTICR[linepos >> 2u];
|
||||||
|
regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
|
||||||
|
regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
|
||||||
|
SYSCFG->EXTICR[linepos >> 2u] = regval;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Configure interrupt mode : read current mode */
|
||||||
|
/* Mask or set line */
|
||||||
|
if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u)
|
||||||
|
{
|
||||||
|
EXTI->IMR |= maskline;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
EXTI->IMR &= ~maskline;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Configure event mode : read current mode */
|
||||||
|
/* Mask or set line */
|
||||||
|
if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u)
|
||||||
|
{
|
||||||
|
EXTI->EMR |= maskline;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
EXTI->EMR &= ~maskline;
|
||||||
|
}
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get configuration of a dedicated Exti line.
|
||||||
|
* @param hexti Exti handle.
|
||||||
|
* @param pExtiConfig Pointer on structure to store Exti configuration.
|
||||||
|
* @retval HAL Status.
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
|
||||||
|
{
|
||||||
|
uint32_t regval;
|
||||||
|
uint32_t linepos;
|
||||||
|
uint32_t maskline;
|
||||||
|
|
||||||
|
/* Check null pointer */
|
||||||
|
if ((hexti == NULL) || (pExtiConfig == NULL))
|
||||||
|
{
|
||||||
|
return HAL_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Check the parameter */
|
||||||
|
assert_param(IS_EXTI_LINE(hexti->Line));
|
||||||
|
|
||||||
|
/* Store handle line number to configuration structure */
|
||||||
|
pExtiConfig->Line = hexti->Line;
|
||||||
|
|
||||||
|
/* Compute line mask */
|
||||||
|
linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
|
||||||
|
maskline = (1uL << linepos);
|
||||||
|
|
||||||
|
/* 1] Get core mode : interrupt */
|
||||||
|
|
||||||
|
/* Check if selected line is enable */
|
||||||
|
if ((EXTI->IMR & maskline) != 0x00u)
|
||||||
|
{
|
||||||
|
pExtiConfig->Mode = EXTI_MODE_INTERRUPT;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
pExtiConfig->Mode = EXTI_MODE_NONE;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Get event mode */
|
||||||
|
/* Check if selected line is enable */
|
||||||
|
if ((EXTI->EMR & maskline) != 0x00u)
|
||||||
|
{
|
||||||
|
pExtiConfig->Mode |= EXTI_MODE_EVENT;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* 2] Get trigger for configurable lines : rising */
|
||||||
|
if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
|
||||||
|
{
|
||||||
|
/* Check if configuration of selected line is enable */
|
||||||
|
if ((EXTI->RTSR & maskline) != 0x00u)
|
||||||
|
{
|
||||||
|
pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Get falling configuration */
|
||||||
|
/* Check if configuration of selected line is enable */
|
||||||
|
if ((EXTI->FTSR & maskline) != 0x00u)
|
||||||
|
{
|
||||||
|
pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Get Gpio port selection for gpio lines */
|
||||||
|
if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
|
||||||
|
{
|
||||||
|
assert_param(IS_EXTI_GPIO_PIN(linepos));
|
||||||
|
|
||||||
|
regval = SYSCFG->EXTICR[linepos >> 2u];
|
||||||
|
pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
pExtiConfig->GPIOSel = 0x00u;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* No Trigger selected */
|
||||||
|
pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
|
||||||
|
pExtiConfig->GPIOSel = 0x00u;
|
||||||
|
}
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear whole configuration of a dedicated Exti line.
|
||||||
|
* @param hexti Exti handle.
|
||||||
|
* @retval HAL Status.
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
|
||||||
|
{
|
||||||
|
uint32_t regval;
|
||||||
|
uint32_t linepos;
|
||||||
|
uint32_t maskline;
|
||||||
|
|
||||||
|
/* Check null pointer */
|
||||||
|
if (hexti == NULL)
|
||||||
|
{
|
||||||
|
return HAL_ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Check the parameter */
|
||||||
|
assert_param(IS_EXTI_LINE(hexti->Line));
|
||||||
|
|
||||||
|
/* compute line mask */
|
||||||
|
linepos = (hexti->Line & EXTI_PIN_MASK);
|
||||||
|
maskline = (1uL << linepos);
|
||||||
|
|
||||||
|
/* 1] Clear interrupt mode */
|
||||||
|
EXTI->IMR = (EXTI->IMR & ~maskline);
|
||||||
|
|
||||||
|
/* 2] Clear event mode */
|
||||||
|
EXTI->EMR = (EXTI->EMR & ~maskline);
|
||||||
|
|
||||||
|
/* 3] Clear triggers in case of configurable lines */
|
||||||
|
if ((hexti->Line & EXTI_CONFIG) != 0x00u)
|
||||||
|
{
|
||||||
|
EXTI->RTSR = (EXTI->RTSR & ~maskline);
|
||||||
|
EXTI->FTSR = (EXTI->FTSR & ~maskline);
|
||||||
|
|
||||||
|
/* Get Gpio port selection for gpio lines */
|
||||||
|
if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO)
|
||||||
|
{
|
||||||
|
assert_param(IS_EXTI_GPIO_PIN(linepos));
|
||||||
|
|
||||||
|
regval = SYSCFG->EXTICR[linepos >> 2u];
|
||||||
|
regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
|
||||||
|
SYSCFG->EXTICR[linepos >> 2u] = regval;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Register callback for a dedicated Exti line.
|
||||||
|
* @param hexti Exti handle.
|
||||||
|
* @param CallbackID User callback identifier.
|
||||||
|
* This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.
|
||||||
|
* @param pPendingCbfn function pointer to be stored as callback.
|
||||||
|
* @retval HAL Status.
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void))
|
||||||
|
{
|
||||||
|
HAL_StatusTypeDef status = HAL_OK;
|
||||||
|
|
||||||
|
switch (CallbackID)
|
||||||
|
{
|
||||||
|
case HAL_EXTI_COMMON_CB_ID:
|
||||||
|
hexti->PendingCallback = pPendingCbfn;
|
||||||
|
break;
|
||||||
|
|
||||||
|
default:
|
||||||
|
status = HAL_ERROR;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Store line number as handle private field.
|
||||||
|
* @param hexti Exti handle.
|
||||||
|
* @param ExtiLine Exti line number.
|
||||||
|
* This parameter can be from 0 to @ref EXTI_LINE_NB.
|
||||||
|
* @retval HAL Status.
|
||||||
|
*/
|
||||||
|
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
|
||||||
|
{
|
||||||
|
/* Check the parameters */
|
||||||
|
assert_param(IS_EXTI_LINE(ExtiLine));
|
||||||
|
|
||||||
|
/* Check null pointer */
|
||||||
|
if (hexti == NULL)
|
||||||
|
{
|
||||||
|
return HAL_ERROR;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Store line number as handle private field */
|
||||||
|
hexti->Line = ExtiLine;
|
||||||
|
|
||||||
|
return HAL_OK;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup EXTI_Exported_Functions_Group2
|
||||||
|
* @brief EXTI IO functions.
|
||||||
|
*
|
||||||
|
@verbatim
|
||||||
|
===============================================================================
|
||||||
|
##### IO operation functions #####
|
||||||
|
===============================================================================
|
||||||
|
|
||||||
|
@endverbatim
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Handle EXTI interrupt request.
|
||||||
|
* @param hexti Exti handle.
|
||||||
|
* @retval none.
|
||||||
|
*/
|
||||||
|
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
|
||||||
|
{
|
||||||
|
uint32_t regval;
|
||||||
|
uint32_t maskline;
|
||||||
|
|
||||||
|
/* Compute line mask */
|
||||||
|
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
|
||||||
|
|
||||||
|
/* Get pending bit */
|
||||||
|
regval = (EXTI->PR & maskline);
|
||||||
|
if (regval != 0x00u)
|
||||||
|
{
|
||||||
|
/* Clear pending bit */
|
||||||
|
EXTI->PR = maskline;
|
||||||
|
|
||||||
|
/* Call callback */
|
||||||
|
if (hexti->PendingCallback != NULL)
|
||||||
|
{
|
||||||
|
hexti->PendingCallback();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get interrupt pending bit of a dedicated line.
|
||||||
|
* @param hexti Exti handle.
|
||||||
|
* @param Edge Specify which pending edge as to be checked.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg @ref EXTI_TRIGGER_RISING_FALLING
|
||||||
|
* This parameter is kept for compatibility with other series.
|
||||||
|
* @retval 1 if interrupt is pending else 0.
|
||||||
|
*/
|
||||||
|
uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
|
||||||
|
{
|
||||||
|
uint32_t regval;
|
||||||
|
uint32_t linepos;
|
||||||
|
uint32_t maskline;
|
||||||
|
|
||||||
|
/* Check parameters */
|
||||||
|
assert_param(IS_EXTI_LINE(hexti->Line));
|
||||||
|
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
|
||||||
|
assert_param(IS_EXTI_PENDING_EDGE(Edge));
|
||||||
|
|
||||||
|
/* Compute line mask */
|
||||||
|
linepos = (hexti->Line & EXTI_PIN_MASK);
|
||||||
|
maskline = (1uL << linepos);
|
||||||
|
|
||||||
|
/* return 1 if bit is set else 0 */
|
||||||
|
regval = ((EXTI->PR & maskline) >> linepos);
|
||||||
|
return regval;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear interrupt pending bit of a dedicated line.
|
||||||
|
* @param hexti Exti handle.
|
||||||
|
* @param Edge Specify which pending edge as to be clear.
|
||||||
|
* This parameter can be one of the following values:
|
||||||
|
* @arg @ref EXTI_TRIGGER_RISING_FALLING
|
||||||
|
* This parameter is kept for compatibility with other series.
|
||||||
|
* @retval None.
|
||||||
|
*/
|
||||||
|
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
|
||||||
|
{
|
||||||
|
uint32_t maskline;
|
||||||
|
|
||||||
|
/* Check parameters */
|
||||||
|
assert_param(IS_EXTI_LINE(hexti->Line));
|
||||||
|
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
|
||||||
|
assert_param(IS_EXTI_PENDING_EDGE(Edge));
|
||||||
|
|
||||||
|
/* Compute line mask */
|
||||||
|
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
|
||||||
|
|
||||||
|
/* Clear Pending bit */
|
||||||
|
EXTI->PR = maskline;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Generate a software interrupt for a dedicated line.
|
||||||
|
* @param hexti Exti handle.
|
||||||
|
* @retval None.
|
||||||
|
*/
|
||||||
|
void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
|
||||||
|
{
|
||||||
|
uint32_t maskline;
|
||||||
|
|
||||||
|
/* Check parameters */
|
||||||
|
assert_param(IS_EXTI_LINE(hexti->Line));
|
||||||
|
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
|
||||||
|
|
||||||
|
/* Compute line mask */
|
||||||
|
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
|
||||||
|
|
||||||
|
/* Generate Software interrupt */
|
||||||
|
EXTI->SWIER = maskline;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif /* HAL_EXTI_MODULE_ENABLED */
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
@ -63,32 +63,16 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
/* Includes ------------------------------------------------------------------*/
|
||||||
#include "stm32f2xx_hal.h"
|
#include "stm32f2xx_hal.h"
|
||||||
|
@ -444,18 +428,22 @@ __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
|
||||||
*/
|
*/
|
||||||
HAL_StatusTypeDef HAL_FLASH_Unlock(void)
|
HAL_StatusTypeDef HAL_FLASH_Unlock(void)
|
||||||
{
|
{
|
||||||
if((FLASH->CR & FLASH_CR_LOCK) != RESET)
|
HAL_StatusTypeDef status = HAL_OK;
|
||||||
|
|
||||||
|
if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
|
||||||
{
|
{
|
||||||
/* Authorize the FLASH Registers access */
|
/* Authorize the FLASH Registers access */
|
||||||
FLASH->KEYR = FLASH_KEY1;
|
WRITE_REG(FLASH->KEYR, FLASH_KEY1);
|
||||||
FLASH->KEYR = FLASH_KEY2;
|
WRITE_REG(FLASH->KEYR, FLASH_KEY2);
|
||||||
|
|
||||||
|
/* Verify Flash is unlocked */
|
||||||
|
if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
|
||||||
|
{
|
||||||
|
status = HAL_ERROR;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
else
|
|
||||||
{
|
return status;
|
||||||
return HAL_ERROR;
|
|
||||||
}
|
|
||||||
|
|
||||||
return HAL_OK;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -623,8 +611,14 @@ static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
|
||||||
FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD;
|
FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD;
|
||||||
FLASH->CR |= FLASH_CR_PG;
|
FLASH->CR |= FLASH_CR_PG;
|
||||||
|
|
||||||
/* Program the double-word */
|
/* Program first word */
|
||||||
*(__IO uint32_t*)Address = (uint32_t)Data;
|
*(__IO uint32_t*)Address = (uint32_t)Data;
|
||||||
|
|
||||||
|
/* Barrier to ensure programming is performed in 2 steps, in right order
|
||||||
|
(independently of compiler optimization behavior) */
|
||||||
|
__ISB();
|
||||||
|
|
||||||
|
/* Program second word */
|
||||||
*(__IO uint32_t*)(Address+4) = (uint32_t)(Data >> 32);
|
*(__IO uint32_t*)(Address+4) = (uint32_t)(Data >> 32);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -34,32 +34,16 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
/* Includes ------------------------------------------------------------------*/
|
||||||
#include "stm32f2xx_hal.h"
|
#include "stm32f2xx_hal.h"
|
||||||
|
@ -670,13 +654,13 @@ static uint8_t FLASH_OB_GetRDP(void)
|
||||||
{
|
{
|
||||||
readstatus = OB_RDP_LEVEL_2;
|
readstatus = OB_RDP_LEVEL_2;
|
||||||
}
|
}
|
||||||
else if((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_1))
|
else if((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_0))
|
||||||
{
|
{
|
||||||
readstatus = OB_RDP_LEVEL_1;
|
readstatus = OB_RDP_LEVEL_0;
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
readstatus = OB_RDP_LEVEL_0;
|
readstatus = OB_RDP_LEVEL_1;
|
||||||
}
|
}
|
||||||
|
|
||||||
return readstatus;
|
return readstatus;
|
||||||
|
|
|
@ -93,32 +93,16 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
/* Includes ------------------------------------------------------------------*/
|
||||||
#include "stm32f2xx_hal.h"
|
#include "stm32f2xx_hal.h"
|
||||||
|
@ -132,6 +116,13 @@
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
/** MISRA C:2012 deviation rule has been granted for following rules:
|
||||||
|
* Rule-18.1_d - Medium: Array pointer `GPIOx' is accessed with index [..,..]
|
||||||
|
* which may be out of array bounds [..,UNKNOWN] in following APIs:
|
||||||
|
* HAL_GPIO_Init
|
||||||
|
* HAL_GPIO_DeInit
|
||||||
|
*/
|
||||||
|
|
||||||
#ifdef HAL_GPIO_MODULE_ENABLED
|
#ifdef HAL_GPIO_MODULE_ENABLED
|
||||||
|
|
||||||
/* Private typedef -----------------------------------------------------------*/
|
/* Private typedef -----------------------------------------------------------*/
|
||||||
|
@ -185,10 +176,9 @@
|
||||||
*/
|
*/
|
||||||
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
||||||
{
|
{
|
||||||
uint32_t position;
|
uint32_t position = 0x00u;
|
||||||
uint32_t ioposition = 0x00U;
|
uint32_t iocurrent;
|
||||||
uint32_t iocurrent = 0x00U;
|
uint32_t temp;
|
||||||
uint32_t temp = 0x00U;
|
|
||||||
|
|
||||||
/* Check the parameters */
|
/* Check the parameters */
|
||||||
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
||||||
|
@ -197,34 +187,13 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
||||||
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
|
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
|
||||||
|
|
||||||
/* Configure the port pins */
|
/* Configure the port pins */
|
||||||
for(position = 0U; position < GPIO_NUMBER; position++)
|
while (((GPIO_Init->Pin) >> position) != 0x00u)
|
||||||
{
|
{
|
||||||
/* Get the IO position */
|
/* Get current io position */
|
||||||
ioposition = 0x01U << position;
|
iocurrent = (GPIO_Init->Pin) & (1uL << position);
|
||||||
/* Get the current IO position */
|
|
||||||
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
|
|
||||||
|
|
||||||
if(iocurrent == ioposition)
|
if (iocurrent != 0x00u)
|
||||||
{
|
{
|
||||||
/*--------------------- GPIO Mode Configuration ------------------------*/
|
|
||||||
/* In case of Alternate function mode selection */
|
|
||||||
if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
|
|
||||||
{
|
|
||||||
/* Check the Alternate function parameter */
|
|
||||||
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
|
|
||||||
/* Configure Alternate function mapped with the current IO */
|
|
||||||
temp = GPIOx->AFR[position >> 3U];
|
|
||||||
temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
|
|
||||||
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
|
|
||||||
GPIOx->AFR[position >> 3U] = temp;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
|
|
||||||
temp = GPIOx->MODER;
|
|
||||||
temp &= ~(GPIO_MODER_MODER0 << (position * 2U));
|
|
||||||
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
|
|
||||||
GPIOx->MODER = temp;
|
|
||||||
|
|
||||||
/* In case of Output or Alternate function mode selection */
|
/* In case of Output or Alternate function mode selection */
|
||||||
if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
|
if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
|
||||||
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
|
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
|
||||||
|
@ -232,24 +201,45 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
||||||
/* Check the Speed parameter */
|
/* Check the Speed parameter */
|
||||||
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
|
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
|
||||||
/* Configure the IO Speed */
|
/* Configure the IO Speed */
|
||||||
temp = GPIOx->OSPEEDR;
|
temp = GPIOx->OSPEEDR;
|
||||||
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
|
temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
|
||||||
temp |= (GPIO_Init->Speed << (position * 2U));
|
temp |= (GPIO_Init->Speed << (position * 2u));
|
||||||
GPIOx->OSPEEDR = temp;
|
GPIOx->OSPEEDR = temp;
|
||||||
|
|
||||||
/* Configure the IO Output Type */
|
/* Configure the IO Output Type */
|
||||||
temp = GPIOx->OTYPER;
|
temp = GPIOx->OTYPER;
|
||||||
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
|
temp &= ~(GPIO_OTYPER_OT0 << position) ;
|
||||||
temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
|
temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4u) << position);
|
||||||
GPIOx->OTYPER = temp;
|
GPIOx->OTYPER = temp;
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Activate the Pull-up or Pull down resistor for the current IO */
|
/* Activate the Pull-up or Pull down resistor for the current IO */
|
||||||
temp = GPIOx->PUPDR;
|
temp = GPIOx->PUPDR;
|
||||||
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
|
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2u));
|
||||||
temp |= ((GPIO_Init->Pull) << (position * 2U));
|
temp |= ((GPIO_Init->Pull) << (position * 2u));
|
||||||
GPIOx->PUPDR = temp;
|
GPIOx->PUPDR = temp;
|
||||||
|
|
||||||
|
/*--------------------- GPIO Mode Configuration ------------------------*/
|
||||||
|
/* In case of Alternate function mode selection */
|
||||||
|
if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
|
||||||
|
{
|
||||||
|
/* Check the Alternate function parameters */
|
||||||
|
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
|
||||||
|
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
|
||||||
|
|
||||||
|
/* Configure Alternate function mapped with the current IO */
|
||||||
|
temp = GPIOx->AFR[position >> 3u];
|
||||||
|
temp &= ~(0xFu << ((position & 0x07u) * 4u));
|
||||||
|
temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
|
||||||
|
GPIOx->AFR[position >> 3u] = temp;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
|
||||||
|
temp = GPIOx->MODER;
|
||||||
|
temp &= ~(GPIO_MODER_MODE0 << (position * 2u));
|
||||||
|
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
|
||||||
|
GPIOx->MODER = temp;
|
||||||
|
|
||||||
/*--------------------- EXTI Mode Configuration ------------------------*/
|
/*--------------------- EXTI Mode Configuration ------------------------*/
|
||||||
/* Configure the External Interrupt or event for the current IO */
|
/* Configure the External Interrupt or event for the current IO */
|
||||||
if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
|
if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
|
||||||
|
@ -257,14 +247,14 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
||||||
/* Enable SYSCFG Clock */
|
/* Enable SYSCFG Clock */
|
||||||
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
||||||
|
|
||||||
temp = SYSCFG->EXTICR[position >> 2U];
|
temp = SYSCFG->EXTICR[position >> 2u];
|
||||||
temp &= ~(0x0FU << (4U * (position & 0x03)));
|
temp &= ~(0x0FuL << (4u * (position & 0x03u)));
|
||||||
temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
|
temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
|
||||||
SYSCFG->EXTICR[position >> 2U] = temp;
|
SYSCFG->EXTICR[position >> 2u] = temp;
|
||||||
|
|
||||||
/* Clear EXTI line configuration */
|
/* Clear EXTI line configuration */
|
||||||
temp = EXTI->IMR;
|
temp = EXTI->IMR;
|
||||||
temp &= ~((uint32_t)iocurrent);
|
temp &= ~(iocurrent);
|
||||||
if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
|
if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
|
||||||
{
|
{
|
||||||
temp |= iocurrent;
|
temp |= iocurrent;
|
||||||
|
@ -272,7 +262,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
||||||
EXTI->IMR = temp;
|
EXTI->IMR = temp;
|
||||||
|
|
||||||
temp = EXTI->EMR;
|
temp = EXTI->EMR;
|
||||||
temp &= ~((uint32_t)iocurrent);
|
temp &= ~(iocurrent);
|
||||||
if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
|
if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
|
||||||
{
|
{
|
||||||
temp |= iocurrent;
|
temp |= iocurrent;
|
||||||
|
@ -281,7 +271,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
||||||
|
|
||||||
/* Clear Rising Falling edge configuration */
|
/* Clear Rising Falling edge configuration */
|
||||||
temp = EXTI->RTSR;
|
temp = EXTI->RTSR;
|
||||||
temp &= ~((uint32_t)iocurrent);
|
temp &= ~(iocurrent);
|
||||||
if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
|
if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
|
||||||
{
|
{
|
||||||
temp |= iocurrent;
|
temp |= iocurrent;
|
||||||
|
@ -289,7 +279,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
||||||
EXTI->RTSR = temp;
|
EXTI->RTSR = temp;
|
||||||
|
|
||||||
temp = EXTI->FTSR;
|
temp = EXTI->FTSR;
|
||||||
temp &= ~((uint32_t)iocurrent);
|
temp &= ~(iocurrent);
|
||||||
if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
|
if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
|
||||||
{
|
{
|
||||||
temp |= iocurrent;
|
temp |= iocurrent;
|
||||||
|
@ -297,6 +287,8 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
||||||
EXTI->FTSR = temp;
|
EXTI->FTSR = temp;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
position++;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -309,58 +301,60 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
||||||
*/
|
*/
|
||||||
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
|
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
|
||||||
{
|
{
|
||||||
uint32_t position;
|
uint32_t position = 0x00u;
|
||||||
uint32_t ioposition = 0x00U;
|
uint32_t iocurrent;
|
||||||
uint32_t iocurrent = 0x00U;
|
uint32_t tmp;
|
||||||
uint32_t tmp = 0x00U;
|
|
||||||
|
|
||||||
/* Check the parameters */
|
/* Check the parameters */
|
||||||
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
||||||
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||||
/* Configure the port pins */
|
|
||||||
for(position = 0U; position < GPIO_NUMBER; position++)
|
|
||||||
{
|
|
||||||
/* Get the IO position */
|
|
||||||
ioposition = 0x01U << position;
|
|
||||||
/* Get the current IO position */
|
|
||||||
iocurrent = (GPIO_Pin) & ioposition;
|
|
||||||
|
|
||||||
if(iocurrent == ioposition)
|
/* Configure the port pins */
|
||||||
|
while ((GPIO_Pin >> position) != 0x00u)
|
||||||
|
{
|
||||||
|
/* Get current io position */
|
||||||
|
iocurrent = (GPIO_Pin) & (1uL << position);
|
||||||
|
|
||||||
|
if (iocurrent != 0x00u)
|
||||||
{
|
{
|
||||||
|
/*------------------------- EXTI Mode Configuration --------------------*/
|
||||||
|
/* Clear the External Interrupt or Event for the current IO */
|
||||||
|
|
||||||
|
tmp = SYSCFG->EXTICR[position >> 2u];
|
||||||
|
tmp &= (0x0FuL << (4u * (position & 0x03u)));
|
||||||
|
if (tmp == (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))))
|
||||||
|
{
|
||||||
|
/* Clear EXTI line configuration */
|
||||||
|
EXTI->IMR &= ~((uint32_t)iocurrent);
|
||||||
|
EXTI->EMR &= ~((uint32_t)iocurrent);
|
||||||
|
|
||||||
|
/* Clear Rising Falling edge configuration */
|
||||||
|
EXTI->RTSR &= ~((uint32_t)iocurrent);
|
||||||
|
EXTI->FTSR &= ~((uint32_t)iocurrent);
|
||||||
|
|
||||||
|
/* Configure the External Interrupt or event for the current IO */
|
||||||
|
tmp = 0x0FuL << (4u * (position & 0x03u));
|
||||||
|
SYSCFG->EXTICR[position >> 2u] &= ~tmp;
|
||||||
|
}
|
||||||
|
|
||||||
/*------------------------- GPIO Mode Configuration --------------------*/
|
/*------------------------- GPIO Mode Configuration --------------------*/
|
||||||
/* Configure IO Direction in Input Floating Mode */
|
/* Configure IO Direction in Input Floating Mode */
|
||||||
GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2U));
|
GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2u));
|
||||||
|
|
||||||
/* Configure the default Alternate Function in current IO */
|
/* Configure the default Alternate Function in current IO */
|
||||||
GPIOx->AFR[position >> 3U] &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
|
GPIOx->AFR[position >> 3u] &= ~(0xFu << ((uint32_t)(position & 0x07u) * 4u));
|
||||||
|
|
||||||
/* Configure the default value for IO Speed */
|
|
||||||
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
|
|
||||||
|
|
||||||
/* Configure the default value IO Output Type */
|
|
||||||
GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ;
|
|
||||||
|
|
||||||
/* Deactivate the Pull-up and Pull-down resistor for the current IO */
|
/* Deactivate the Pull-up and Pull-down resistor for the current IO */
|
||||||
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
|
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
|
||||||
|
|
||||||
/*------------------------- EXTI Mode Configuration --------------------*/
|
/* Configure the default value IO Output Type */
|
||||||
tmp = SYSCFG->EXTICR[position >> 2U];
|
GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position);
|
||||||
tmp &= (0x0FU << (4U * (position & 0x03U)));
|
|
||||||
if(tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))))
|
|
||||||
{
|
|
||||||
/* Configure the External Interrupt or event for the current IO */
|
|
||||||
tmp = 0x0FU << (4U * (position & 0x03U));
|
|
||||||
SYSCFG->EXTICR[position >> 2U] &= ~tmp;
|
|
||||||
|
|
||||||
/* Clear EXTI line configuration */
|
/* Configure the default value for IO Speed */
|
||||||
EXTI->IMR &= ~((uint32_t)iocurrent);
|
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u));
|
||||||
EXTI->EMR &= ~((uint32_t)iocurrent);
|
|
||||||
|
|
||||||
/* Clear Rising Falling edge configuration */
|
|
||||||
EXTI->RTSR &= ~((uint32_t)iocurrent);
|
|
||||||
EXTI->FTSR &= ~((uint32_t)iocurrent);
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
position++;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -448,7 +442,14 @@ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||||
/* Check the parameters */
|
/* Check the parameters */
|
||||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||||
|
|
||||||
GPIOx->ODR ^= GPIO_Pin;
|
if ((GPIOx->ODR & GPIO_Pin) != 0X00u)
|
||||||
|
{
|
||||||
|
GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
GPIOx->BSRR = (uint32_t)GPIO_Pin;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -477,10 +478,11 @@ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||||
GPIOx->LCKR = GPIO_Pin;
|
GPIOx->LCKR = GPIO_Pin;
|
||||||
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
|
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
|
||||||
GPIOx->LCKR = tmp;
|
GPIOx->LCKR = tmp;
|
||||||
/* Read LCKK bit*/
|
/* Read LCKK register. This read is mandatory to complete key lock sequence */
|
||||||
tmp = GPIOx->LCKR;
|
tmp = GPIOx->LCKR;
|
||||||
|
|
||||||
if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)
|
/* read again in order to confirm lock is active */
|
||||||
|
if((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00u)
|
||||||
{
|
{
|
||||||
return HAL_OK;
|
return HAL_OK;
|
||||||
}
|
}
|
||||||
|
@ -498,7 +500,7 @@ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||||
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
|
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
|
||||||
{
|
{
|
||||||
/* EXTI line interrupt detected */
|
/* EXTI line interrupt detected */
|
||||||
if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
|
if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u)
|
||||||
{
|
{
|
||||||
__HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
|
__HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
|
||||||
HAL_GPIO_EXTI_Callback(GPIO_Pin);
|
HAL_GPIO_EXTI_Callback(GPIO_Pin);
|
||||||
|
|
|
@ -11,32 +11,16 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
/* Includes ------------------------------------------------------------------*/
|
||||||
#include "stm32f2xx_hal.h"
|
#include "stm32f2xx_hal.h"
|
||||||
|
|
|
@ -10,32 +10,16 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
/* Includes ------------------------------------------------------------------*/
|
||||||
#include "stm32f2xx_hal.h"
|
#include "stm32f2xx_hal.h"
|
||||||
|
|
|
@ -54,29 +54,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
@ -332,7 +316,7 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void)
|
||||||
SystemCoreClock = HSI_VALUE;
|
SystemCoreClock = HSI_VALUE;
|
||||||
|
|
||||||
/* Adapt Systick interrupt period */
|
/* Adapt Systick interrupt period */
|
||||||
if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
|
if(HAL_InitTick(uwTickPrio) != HAL_OK)
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
return HAL_ERROR;
|
||||||
}
|
}
|
||||||
|
@ -528,23 +512,36 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
|
||||||
/*------------------------------ LSE Configuration -------------------------*/
|
/*------------------------------ LSE Configuration -------------------------*/
|
||||||
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
|
||||||
{
|
{
|
||||||
|
FlagStatus pwrclkchanged = RESET;
|
||||||
|
|
||||||
/* Check the parameters */
|
/* Check the parameters */
|
||||||
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
|
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
|
||||||
|
|
||||||
/* Enable Power Clock */
|
/* Update LSE configuration in Backup Domain control register */
|
||||||
__HAL_RCC_PWR_CLK_ENABLE();
|
/* Requires to enable write access to Backup Domain of necessary */
|
||||||
|
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
|
||||||
|
{
|
||||||
|
__HAL_RCC_PWR_CLK_ENABLE();
|
||||||
|
pwrclkchanged = SET;
|
||||||
|
}
|
||||||
|
|
||||||
/* Enable write access to Backup domain */
|
/* Enable write access to Backup domain */
|
||||||
PWR->CR |= PWR_CR_DBP;
|
PWR->CR |= PWR_CR_DBP;
|
||||||
|
|
||||||
/* Wait for Backup domain Write protection enable */
|
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
||||||
tickstart = HAL_GetTick();
|
|
||||||
|
|
||||||
while((PWR->CR & PWR_CR_DBP) == RESET)
|
|
||||||
{
|
{
|
||||||
if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
|
/* Enable write access to Backup domain */
|
||||||
|
SET_BIT(PWR->CR, PWR_CR_DBP);
|
||||||
|
|
||||||
|
/* Wait for Backup domain Write protection disable */
|
||||||
|
tickstart = HAL_GetTick();
|
||||||
|
|
||||||
|
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
||||||
{
|
{
|
||||||
return HAL_TIMEOUT;
|
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
||||||
|
{
|
||||||
|
return HAL_TIMEOUT;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -579,6 +576,12 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/* Restore clock configuration if changed */
|
||||||
|
if(pwrclkchanged == SET)
|
||||||
|
{
|
||||||
|
__HAL_RCC_PWR_CLK_DISABLE();
|
||||||
|
}
|
||||||
}
|
}
|
||||||
/*-------------------------------- PLL Configuration -----------------------*/
|
/*-------------------------------- PLL Configuration -----------------------*/
|
||||||
/* Check the parameters */
|
/* Check the parameters */
|
||||||
|
@ -653,7 +656,25 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
return HAL_ERROR;
|
/* Check if there is a request to disable the PLL used as System clock source */
|
||||||
|
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
|
||||||
|
{
|
||||||
|
return HAL_ERROR;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Do not return HAL_ERROR if request repeats the current configuration */
|
||||||
|
uint32_t pllcfgr = RCC->PLLCFGR;
|
||||||
|
|
||||||
|
if((READ_BIT(pllcfgr, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
||||||
|
(READ_BIT(pllcfgr, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
|
||||||
|
((READ_BIT(pllcfgr, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos) != RCC_OscInitStruct->PLL.PLLN) ||
|
||||||
|
(READ_BIT(pllcfgr, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) ||
|
||||||
|
(READ_BIT(pllcfgr, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ))
|
||||||
|
{
|
||||||
|
return HAL_ERROR;
|
||||||
|
}
|
||||||
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
return HAL_OK;
|
return HAL_OK;
|
||||||
|
@ -815,7 +836,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
|
||||||
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
|
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
|
||||||
|
|
||||||
/* Configure the source of time base considering new system clocks settings */
|
/* Configure the source of time base considering new system clocks settings */
|
||||||
HAL_InitTick (TICK_INT_PRIORITY);
|
HAL_InitTick (uwTickPrio);
|
||||||
|
|
||||||
return HAL_OK;
|
return HAL_OK;
|
||||||
}
|
}
|
||||||
|
|
|
@ -10,32 +10,16 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
/* Includes ------------------------------------------------------------------*/
|
||||||
#include "stm32f2xx_hal.h"
|
#include "stm32f2xx_hal.h"
|
||||||
|
|
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
@ -6,32 +6,17 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#if defined(USE_FULL_LL_DRIVER)
|
#if defined(USE_FULL_LL_DRIVER)
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
|
|
@ -6,32 +6,17 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#if defined(USE_FULL_LL_DRIVER)
|
#if defined(USE_FULL_LL_DRIVER)
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
|
|
@ -6,32 +6,17 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#if defined(USE_FULL_LL_DRIVER)
|
#if defined(USE_FULL_LL_DRIVER)
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
@ -52,6 +37,22 @@
|
||||||
/** @addtogroup GPIO_LL
|
/** @addtogroup GPIO_LL
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
|
/** MISRA C:2012 deviation rule has been granted for following rules:
|
||||||
|
* Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of
|
||||||
|
* range of the shift operator in following API :
|
||||||
|
* LL_GPIO_Init
|
||||||
|
* LL_GPIO_DeInit
|
||||||
|
* LL_GPIO_SetPinMode
|
||||||
|
* LL_GPIO_GetPinMode
|
||||||
|
* LL_GPIO_SetPinSpeed
|
||||||
|
* LL_GPIO_GetPinSpeed
|
||||||
|
* LL_GPIO_SetPinPull
|
||||||
|
* LL_GPIO_GetPinPull
|
||||||
|
* LL_GPIO_GetAFPin_0_7
|
||||||
|
* LL_GPIO_SetAFPin_0_7
|
||||||
|
* LL_GPIO_SetAFPin_8_15
|
||||||
|
* LL_GPIO_GetAFPin_8_15
|
||||||
|
*/
|
||||||
|
|
||||||
/* Private types -------------------------------------------------------------*/
|
/* Private types -------------------------------------------------------------*/
|
||||||
/* Private variables ---------------------------------------------------------*/
|
/* Private variables ---------------------------------------------------------*/
|
||||||
|
@ -201,8 +202,8 @@ ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx)
|
||||||
*/
|
*/
|
||||||
ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
|
ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
|
||||||
{
|
{
|
||||||
uint32_t pinpos = 0x00000000U;
|
uint32_t pinpos;
|
||||||
uint32_t currentpin = 0x00000000U;
|
uint32_t currentpin;
|
||||||
|
|
||||||
/* Check the parameters */
|
/* Check the parameters */
|
||||||
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
||||||
|
@ -215,16 +216,13 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru
|
||||||
pinpos = POSITION_VAL(GPIO_InitStruct->Pin);
|
pinpos = POSITION_VAL(GPIO_InitStruct->Pin);
|
||||||
|
|
||||||
/* Configure the port pins */
|
/* Configure the port pins */
|
||||||
while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00000000U)
|
while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00u)
|
||||||
{
|
{
|
||||||
/* Get current io position */
|
/* Get current io position */
|
||||||
currentpin = (GPIO_InitStruct->Pin) & (0x00000001U << pinpos);
|
currentpin = (GPIO_InitStruct->Pin) & (0x00000001uL << pinpos);
|
||||||
|
|
||||||
if (currentpin)
|
if (currentpin != 0x00u)
|
||||||
{
|
{
|
||||||
/* Pin Mode configuration */
|
|
||||||
LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
|
|
||||||
|
|
||||||
if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
|
if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
|
||||||
{
|
{
|
||||||
/* Check Speed mode parameters */
|
/* Check Speed mode parameters */
|
||||||
|
@ -232,6 +230,12 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru
|
||||||
|
|
||||||
/* Speed mode configuration */
|
/* Speed mode configuration */
|
||||||
LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed);
|
LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed);
|
||||||
|
|
||||||
|
/* Check Output mode parameters */
|
||||||
|
assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
|
||||||
|
|
||||||
|
/* Output mode configuration*/
|
||||||
|
LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Pull-up Pull down resistor configuration*/
|
/* Pull-up Pull down resistor configuration*/
|
||||||
|
@ -252,19 +256,12 @@ ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStru
|
||||||
LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate);
|
LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/* Pin Mode configuration */
|
||||||
|
LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
|
||||||
}
|
}
|
||||||
pinpos++;
|
pinpos++;
|
||||||
}
|
}
|
||||||
|
|
||||||
if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
|
|
||||||
{
|
|
||||||
/* Check Output mode parameters */
|
|
||||||
assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
|
|
||||||
|
|
||||||
/* Output mode configuration*/
|
|
||||||
LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType);
|
|
||||||
|
|
||||||
}
|
|
||||||
return (SUCCESS);
|
return (SUCCESS);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -6,32 +6,17 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#if defined(USE_FULL_LL_DRIVER)
|
#if defined(USE_FULL_LL_DRIVER)
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
@ -91,7 +76,7 @@ uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void);
|
||||||
* @brief Reset the RCC clock configuration to the default reset state.
|
* @brief Reset the RCC clock configuration to the default reset state.
|
||||||
* @note The default reset state of the clock configuration is given below:
|
* @note The default reset state of the clock configuration is given below:
|
||||||
* - HSI ON and used as system clock source
|
* - HSI ON and used as system clock source
|
||||||
* - HSE and PLL OFF
|
* - HSE, PLL, PLLI2S OFF
|
||||||
* - AHB, APB1 and APB2 prescaler set to 1.
|
* - AHB, APB1 and APB2 prescaler set to 1.
|
||||||
* - CSS, MCO OFF
|
* - CSS, MCO OFF
|
||||||
* - All interrupts disabled
|
* - All interrupts disabled
|
||||||
|
@ -109,6 +94,10 @@ ErrorStatus LL_RCC_DeInit(void)
|
||||||
/* Set HSION bit */
|
/* Set HSION bit */
|
||||||
LL_RCC_HSI_Enable();
|
LL_RCC_HSI_Enable();
|
||||||
|
|
||||||
|
/* Wait for HSI READY bit */
|
||||||
|
while(LL_RCC_HSI_IsReady() != 1U)
|
||||||
|
{}
|
||||||
|
|
||||||
/* Reset CFGR register */
|
/* Reset CFGR register */
|
||||||
LL_RCC_WriteReg(CFGR, 0x00000000U);
|
LL_RCC_WriteReg(CFGR, 0x00000000U);
|
||||||
|
|
||||||
|
@ -126,18 +115,26 @@ ErrorStatus LL_RCC_DeInit(void)
|
||||||
/* Set HSITRIM bits to the reset value*/
|
/* Set HSITRIM bits to the reset value*/
|
||||||
LL_RCC_HSI_SetCalibTrimming(0x10U);
|
LL_RCC_HSI_SetCalibTrimming(0x10U);
|
||||||
|
|
||||||
|
/* Wait for PLL READY bit to be reset */
|
||||||
|
while(LL_RCC_PLL_IsReady() != 0U)
|
||||||
|
{}
|
||||||
|
|
||||||
|
/* Wait for PLLI2S READY bit to be reset */
|
||||||
|
while(LL_RCC_PLLI2S_IsReady() != 0U)
|
||||||
|
{}
|
||||||
|
|
||||||
/* Reset PLLCFGR register */
|
/* Reset PLLCFGR register */
|
||||||
LL_RCC_WriteReg(PLLCFGR, 0x24003010U);
|
LL_RCC_WriteReg(PLLCFGR, 0x24003010U);
|
||||||
|
|
||||||
/* Reset PLLI2SCFGR register */
|
/* Reset PLLI2SCFGR register */
|
||||||
LL_RCC_WriteReg(PLLI2SCFGR, 0x20003000U);
|
LL_RCC_WriteReg(PLLI2SCFGR, 0x20003000U);
|
||||||
|
|
||||||
/* Reset HSEBYP bit */
|
|
||||||
LL_RCC_HSE_DisableBypass();
|
|
||||||
|
|
||||||
/* Disable all interrupts */
|
/* Disable all interrupts */
|
||||||
LL_RCC_WriteReg(CIR, 0x00000000U);
|
LL_RCC_WriteReg(CIR, 0x00000000U);
|
||||||
|
|
||||||
|
/* Clear reset flags */
|
||||||
|
LL_RCC_ClearResetFlags();
|
||||||
|
|
||||||
return SUCCESS;
|
return SUCCESS;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -6,29 +6,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
@ -76,41 +60,41 @@
|
||||||
/** @defgroup SPI_LL_Private_Macros SPI Private Macros
|
/** @defgroup SPI_LL_Private_Macros SPI Private Macros
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
#define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \
|
#define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \
|
||||||
|| ((__VALUE__) == LL_SPI_SIMPLEX_RX) \
|
|| ((__VALUE__) == LL_SPI_SIMPLEX_RX) \
|
||||||
|| ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
|
|| ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
|
||||||
|| ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
|
|| ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
|
||||||
|
|
||||||
#define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
|
#define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
|
||||||
|| ((__VALUE__) == LL_SPI_MODE_SLAVE))
|
|| ((__VALUE__) == LL_SPI_MODE_SLAVE))
|
||||||
|
|
||||||
#define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \
|
#define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \
|
||||||
|| ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
|
|| ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
|
||||||
|
|
||||||
#define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
|
#define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
|
||||||
|| ((__VALUE__) == LL_SPI_POLARITY_HIGH))
|
|| ((__VALUE__) == LL_SPI_POLARITY_HIGH))
|
||||||
|
|
||||||
#define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
|
#define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
|
||||||
|| ((__VALUE__) == LL_SPI_PHASE_2EDGE))
|
|| ((__VALUE__) == LL_SPI_PHASE_2EDGE))
|
||||||
|
|
||||||
#define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
|
#define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
|
||||||
|| ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
|
|| ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
|
||||||
|| ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
|
|| ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
|
||||||
|
|
||||||
#define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \
|
#define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \
|
||||||
|| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \
|
|| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \
|
||||||
|| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \
|
|| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \
|
||||||
|| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \
|
|| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \
|
||||||
|| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \
|
|| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \
|
||||||
|| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \
|
|| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \
|
||||||
|| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
|
|| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
|
||||||
|| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
|
|| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
|
||||||
|
|
||||||
#define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
|
#define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
|
||||||
|| ((__VALUE__) == LL_SPI_MSB_FIRST))
|
|| ((__VALUE__) == LL_SPI_MSB_FIRST))
|
||||||
|
|
||||||
#define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
|
#define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
|
||||||
|| ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
|
|| ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
|
||||||
|
|
||||||
#define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
|
#define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
|
||||||
|
|
||||||
|
@ -186,7 +170,7 @@ ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
|
||||||
/**
|
/**
|
||||||
* @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
|
* @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
|
||||||
* @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
|
* @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
|
||||||
* SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
|
* SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
|
||||||
* @param SPIx SPI Instance
|
* @param SPIx SPI Instance
|
||||||
* @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
|
* @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
|
||||||
* @retval An ErrorStatus enumeration value. (Return always SUCCESS)
|
* @retval An ErrorStatus enumeration value. (Return always SUCCESS)
|
||||||
|
@ -310,36 +294,36 @@ void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
|
||||||
* @{
|
* @{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \
|
#define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \
|
||||||
|| ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
|
|| ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
|
||||||
|| ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \
|
|| ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \
|
||||||
|| ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
|
|| ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
|
||||||
|
|
||||||
#define IS_LL_I2S_CPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \
|
#define IS_LL_I2S_CPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \
|
||||||
|| ((__VALUE__) == LL_I2S_POLARITY_HIGH))
|
|| ((__VALUE__) == LL_I2S_POLARITY_HIGH))
|
||||||
|
|
||||||
#define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \
|
#define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \
|
||||||
|| ((__VALUE__) == LL_I2S_STANDARD_MSB) \
|
|| ((__VALUE__) == LL_I2S_STANDARD_MSB) \
|
||||||
|| ((__VALUE__) == LL_I2S_STANDARD_LSB) \
|
|| ((__VALUE__) == LL_I2S_STANDARD_LSB) \
|
||||||
|| ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
|
|| ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
|
||||||
|| ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
|
|| ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
|
||||||
|
|
||||||
#define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \
|
#define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \
|
||||||
|| ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \
|
|| ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \
|
||||||
|| ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
|
|| ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
|
||||||
|| ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
|
|| ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
|
||||||
|
|
||||||
#define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
|
#define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
|
||||||
|| ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
|
|| ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
|
||||||
|
|
||||||
#define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \
|
#define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \
|
||||||
&& ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
|
&& ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
|
||||||
|| ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
|
|| ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
|
||||||
|
|
||||||
#define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U)
|
#define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U)
|
||||||
|
|
||||||
#define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
|
#define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
|
||||||
|| ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
|
|| ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
@ -370,7 +354,7 @@ ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
|
||||||
/**
|
/**
|
||||||
* @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
|
* @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
|
||||||
* @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
|
* @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
|
||||||
* SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
|
* SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
|
||||||
* @param SPIx SPI Instance
|
* @param SPIx SPI Instance
|
||||||
* @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
|
* @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
|
||||||
* @retval An ErrorStatus enumeration value:
|
* @retval An ErrorStatus enumeration value:
|
||||||
|
@ -379,9 +363,11 @@ ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
|
||||||
*/
|
*/
|
||||||
ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
|
ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
|
||||||
{
|
{
|
||||||
uint16_t i2sdiv = 2U, i2sodd = 0U, packetlength = 1U;
|
uint32_t i2sdiv = 2U;
|
||||||
uint32_t tmp = 0U;
|
uint32_t i2sodd = 0U;
|
||||||
uint32_t sourceclock = 0U;
|
uint32_t packetlength = 1U;
|
||||||
|
uint32_t tmp;
|
||||||
|
uint32_t sourceclock;
|
||||||
ErrorStatus status = ERROR;
|
ErrorStatus status = ERROR;
|
||||||
|
|
||||||
/* Check the I2S parameters */
|
/* Check the I2S parameters */
|
||||||
|
@ -439,25 +425,25 @@ ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
|
||||||
if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
|
if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
|
||||||
{
|
{
|
||||||
/* MCLK output is enabled */
|
/* MCLK output is enabled */
|
||||||
tmp = (uint16_t)(((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
|
tmp = (((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
/* MCLK output is disabled */
|
/* MCLK output is disabled */
|
||||||
tmp = (uint16_t)(((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
|
tmp = (((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Remove the floating point */
|
/* Remove the floating point */
|
||||||
tmp = tmp / 10U;
|
tmp = tmp / 10U;
|
||||||
|
|
||||||
/* Check the parity of the divider */
|
/* Check the parity of the divider */
|
||||||
i2sodd = (uint16_t)(tmp & (uint16_t)0x0001U);
|
i2sodd = (tmp & (uint16_t)0x0001U);
|
||||||
|
|
||||||
/* Compute the i2sdiv prescaler */
|
/* Compute the i2sdiv prescaler */
|
||||||
i2sdiv = (uint16_t)((tmp - i2sodd) / 2U);
|
i2sdiv = ((tmp - i2sodd) / 2U);
|
||||||
|
|
||||||
/* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
|
/* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
|
||||||
i2sodd = (uint16_t)(i2sodd << 8U);
|
i2sodd = (i2sodd << 8U);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Test if the divider is 1 or 0 or greater than 0xFF */
|
/* Test if the divider is 1 or 0 or greater than 0xFF */
|
||||||
|
@ -498,7 +484,7 @@ void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
|
||||||
* @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
|
* @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
|
||||||
* Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
|
* Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
|
||||||
* @param SPIx SPI Instance
|
* @param SPIx SPI Instance
|
||||||
* @param PrescalerLinear value: Min_Data=0x02 and Max_Data=0xFF.
|
* @param PrescalerLinear value Min_Data=0x02 and Max_Data=0xFF.
|
||||||
* @param PrescalerParity This parameter can be one of the following values:
|
* @param PrescalerParity This parameter can be one of the following values:
|
||||||
* @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
|
* @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
|
||||||
* @arg @ref LL_I2S_PRESCALER_PARITY_ODD
|
* @arg @ref LL_I2S_PRESCALER_PARITY_ODD
|
||||||
|
|
|
@ -6,32 +6,17 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#if defined(USE_FULL_LL_DRIVER)
|
#if defined(USE_FULL_LL_DRIVER)
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
/* Includes ------------------------------------------------------------------*/
|
||||||
|
@ -73,7 +58,7 @@
|
||||||
|
|
||||||
/* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
|
/* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
|
||||||
* divided by the smallest oversampling used on the USART (i.e. 8) */
|
* divided by the smallest oversampling used on the USART (i.e. 8) */
|
||||||
#define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 10000000U)
|
#define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 7500000U)
|
||||||
|
|
||||||
/* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */
|
/* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */
|
||||||
#define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
|
#define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
|
||||||
|
@ -322,8 +307,8 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Set each @ref LL_USART_InitTypeDef field to default value.
|
* @brief Set each @ref LL_USART_InitTypeDef field to default value.
|
||||||
* @param USART_InitStruct pointer to a @ref LL_USART_InitTypeDef structure
|
* @param USART_InitStruct Pointer to a @ref LL_USART_InitTypeDef structure
|
||||||
* whose fields will be set to default values.
|
* whose fields will be set to default values.
|
||||||
* @retval None
|
* @retval None
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
@ -345,7 +330,7 @@ void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
|
||||||
* @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
|
* @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
|
||||||
* USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
|
* USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
|
||||||
* @param USARTx USART Instance
|
* @param USARTx USART Instance
|
||||||
* @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
|
* @param USART_ClockInitStruct Pointer to a @ref LL_USART_ClockInitTypeDef structure
|
||||||
* that contains the Clock configuration information for the specified USART peripheral.
|
* that contains the Clock configuration information for the specified USART peripheral.
|
||||||
* @retval An ErrorStatus enumeration value:
|
* @retval An ErrorStatus enumeration value:
|
||||||
* - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
|
* - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
|
||||||
|
@ -406,8 +391,8 @@ ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
|
* @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
|
||||||
* @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
|
* @param USART_ClockInitStruct Pointer to a @ref LL_USART_ClockInitTypeDef structure
|
||||||
* whose fields will be set to default values.
|
* whose fields will be set to default values.
|
||||||
* @retval None
|
* @retval None
|
||||||
*/
|
*/
|
||||||
void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
|
void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
|
||||||
|
|
|
@ -6,32 +6,17 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
/* Includes ------------------------------------------------------------------*/
|
||||||
#include "stm32f2xx_ll_utils.h"
|
#include "stm32f2xx_ll_utils.h"
|
||||||
#include "stm32f2xx_ll_rcc.h"
|
#include "stm32f2xx_ll_rcc.h"
|
||||||
|
|
|
@ -2,32 +2,16 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @file stm32f2xx_hal_conf.h
|
* @file stm32f2xx_hal_conf.h
|
||||||
* @brief HAL configuration file.
|
* @brief HAL configuration file.
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2018 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
@ -52,6 +36,7 @@
|
||||||
/*#define HAL_ADC_MODULE_ENABLED */
|
/*#define HAL_ADC_MODULE_ENABLED */
|
||||||
/*#define HAL_CRYP_MODULE_ENABLED */
|
/*#define HAL_CRYP_MODULE_ENABLED */
|
||||||
#define HAL_CAN_MODULE_ENABLED
|
#define HAL_CAN_MODULE_ENABLED
|
||||||
|
/*#define HAL_CAN_LEGACY_MODULE_ENABLED */
|
||||||
/*#define HAL_CRC_MODULE_ENABLED */
|
/*#define HAL_CRC_MODULE_ENABLED */
|
||||||
/*#define HAL_CRYP_MODULE_ENABLED */
|
/*#define HAL_CRYP_MODULE_ENABLED */
|
||||||
/*#define HAL_DAC_MODULE_ENABLED */
|
/*#define HAL_DAC_MODULE_ENABLED */
|
||||||
|
@ -82,6 +67,7 @@
|
||||||
#define HAL_DMA_MODULE_ENABLED
|
#define HAL_DMA_MODULE_ENABLED
|
||||||
#define HAL_RCC_MODULE_ENABLED
|
#define HAL_RCC_MODULE_ENABLED
|
||||||
#define HAL_FLASH_MODULE_ENABLED
|
#define HAL_FLASH_MODULE_ENABLED
|
||||||
|
#define HAL_EXTI_MODULE_ENABLED
|
||||||
#define HAL_PWR_MODULE_ENABLED
|
#define HAL_PWR_MODULE_ENABLED
|
||||||
#define HAL_CORTEX_MODULE_ENABLED
|
#define HAL_CORTEX_MODULE_ENABLED
|
||||||
|
|
||||||
|
@ -151,6 +137,33 @@
|
||||||
#define INSTRUCTION_CACHE_ENABLE 1
|
#define INSTRUCTION_CACHE_ENABLE 1
|
||||||
#define DATA_CACHE_ENABLE 1U
|
#define DATA_CACHE_ENABLE 1U
|
||||||
|
|
||||||
|
#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
|
||||||
|
#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */
|
||||||
|
#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */
|
||||||
|
#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */
|
||||||
|
#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */
|
||||||
|
#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */
|
||||||
|
#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */
|
||||||
|
#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */
|
||||||
|
#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */
|
||||||
|
#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */
|
||||||
|
#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */
|
||||||
|
#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */
|
||||||
|
#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */
|
||||||
|
#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */
|
||||||
|
#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */
|
||||||
|
#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */
|
||||||
|
#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */
|
||||||
|
#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */
|
||||||
|
#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */
|
||||||
|
#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */
|
||||||
|
#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */
|
||||||
|
#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */
|
||||||
|
#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */
|
||||||
|
#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */
|
||||||
|
#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */
|
||||||
|
#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */
|
||||||
|
|
||||||
/* ########################## Assert Selection ############################## */
|
/* ########################## Assert Selection ############################## */
|
||||||
/**
|
/**
|
||||||
* @brief Uncomment the line below to expanse the "assert_param" macro in the
|
* @brief Uncomment the line below to expanse the "assert_param" macro in the
|
||||||
|
@ -221,7 +234,6 @@
|
||||||
* Deactivated: CRC code cleaned from driver
|
* Deactivated: CRC code cleaned from driver
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#define USE_SPI_CRC 0U
|
|
||||||
/* Includes ------------------------------------------------------------------*/
|
/* Includes ------------------------------------------------------------------*/
|
||||||
/**
|
/**
|
||||||
* @brief Include module's header file
|
* @brief Include module's header file
|
||||||
|
@ -235,6 +247,10 @@
|
||||||
#include "stm32f2xx_hal_gpio.h"
|
#include "stm32f2xx_hal_gpio.h"
|
||||||
#endif /* HAL_GPIO_MODULE_ENABLED */
|
#endif /* HAL_GPIO_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_EXTI_MODULE_ENABLED
|
||||||
|
#include "stm32f2xx_hal_exti.h"
|
||||||
|
#endif /* HAL_EXTI_MODULE_ENABLED */
|
||||||
|
|
||||||
#ifdef HAL_DMA_MODULE_ENABLED
|
#ifdef HAL_DMA_MODULE_ENABLED
|
||||||
#include "stm32f2xx_hal_dma.h"
|
#include "stm32f2xx_hal_dma.h"
|
||||||
#endif /* HAL_DMA_MODULE_ENABLED */
|
#endif /* HAL_DMA_MODULE_ENABLED */
|
||||||
|
@ -251,6 +267,10 @@
|
||||||
#include "stm32f2xx_hal_can.h"
|
#include "stm32f2xx_hal_can.h"
|
||||||
#endif /* HAL_CAN_MODULE_ENABLED */
|
#endif /* HAL_CAN_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
|
||||||
|
#include "stm32f2xx_hal_can_legacy.h"
|
||||||
|
#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
|
||||||
|
|
||||||
#ifdef HAL_CRC_MODULE_ENABLED
|
#ifdef HAL_CRC_MODULE_ENABLED
|
||||||
#include "stm32f2xx_hal_crc.h"
|
#include "stm32f2xx_hal_crc.h"
|
||||||
#endif /* HAL_CRC_MODULE_ENABLED */
|
#endif /* HAL_CRC_MODULE_ENABLED */
|
||||||
|
@ -323,10 +343,6 @@
|
||||||
#include "stm32f2xx_hal_sd.h"
|
#include "stm32f2xx_hal_sd.h"
|
||||||
#endif /* HAL_SD_MODULE_ENABLED */
|
#endif /* HAL_SD_MODULE_ENABLED */
|
||||||
|
|
||||||
#ifdef HAL_MMC_MODULE_ENABLED
|
|
||||||
#include "stm32f2xx_hal_mmc.h"
|
|
||||||
#endif /* HAL_MMC_MODULE_ENABLED */
|
|
||||||
|
|
||||||
#ifdef HAL_SPI_MODULE_ENABLED
|
#ifdef HAL_SPI_MODULE_ENABLED
|
||||||
#include "stm32f2xx_hal_spi.h"
|
#include "stm32f2xx_hal_spi.h"
|
||||||
#endif /* HAL_SPI_MODULE_ENABLED */
|
#endif /* HAL_SPI_MODULE_ENABLED */
|
||||||
|
@ -362,20 +378,23 @@
|
||||||
#ifdef HAL_HCD_MODULE_ENABLED
|
#ifdef HAL_HCD_MODULE_ENABLED
|
||||||
#include "stm32f2xx_hal_hcd.h"
|
#include "stm32f2xx_hal_hcd.h"
|
||||||
#endif /* HAL_HCD_MODULE_ENABLED */
|
#endif /* HAL_HCD_MODULE_ENABLED */
|
||||||
|
|
||||||
|
#ifdef HAL_MMC_MODULE_ENABLED
|
||||||
|
#include "stm32f2xx_hal_mmc.h"
|
||||||
|
#endif /* HAL_MMC_MODULE_ENABLED */
|
||||||
/* Exported macro ------------------------------------------------------------*/
|
/* Exported macro ------------------------------------------------------------*/
|
||||||
#ifdef USE_FULL_ASSERT
|
#ifdef USE_FULL_ASSERT
|
||||||
/**
|
/**
|
||||||
* @brief The assert_param macro is used for function's parameters check.
|
* @brief The assert_param macro is used for function's parameters check.
|
||||||
* @param expr: If expr is false, it calls assert_failed function
|
* @param expr If expr is false, it calls assert_failed function
|
||||||
* which reports the name of the source file and the source
|
* which reports the name of the source file and the source
|
||||||
* line number of the call that failed.
|
* line number of the call that failed.
|
||||||
* If expr is true, it returns no value.
|
* If expr is true, it returns no value.
|
||||||
* @retval None
|
* @retval None
|
||||||
*/
|
*/
|
||||||
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
|
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((char *)__FILE__, __LINE__))
|
||||||
/* Exported functions ------------------------------------------------------- */
|
/* Exported functions ------------------------------------------------------- */
|
||||||
void assert_failed(uint8_t* file, uint32_t line);
|
void assert_failed(char* file, uint32_t line);
|
||||||
#else
|
#else
|
||||||
#define assert_param(expr) ((void)0U)
|
#define assert_param(expr) ((void)0U)
|
||||||
#endif /* USE_FULL_ASSERT */
|
#endif /* USE_FULL_ASSERT */
|
||||||
|
|
|
@ -21,29 +21,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
|
Binary file not shown.
|
@ -6,57 +6,57 @@ EXEC_P, HAS_SYMS, D_PAGED
|
||||||
start address 0x08008000
|
start address 0x08008000
|
||||||
|
|
||||||
Program Header:
|
Program Header:
|
||||||
0x70000001 off 0x00009f38 vaddr 0x08009f38 paddr 0x08009f38 align 2**2
|
0x70000001 off 0x00009d04 vaddr 0x08009d04 paddr 0x08009d04 align 2**2
|
||||||
filesz 0x00000008 memsz 0x00000008 flags r--
|
filesz 0x00000008 memsz 0x00000008 flags r--
|
||||||
LOAD off 0x00000000 vaddr 0x08000000 paddr 0x08000000 align 2**16
|
LOAD off 0x00000000 vaddr 0x08000000 paddr 0x08000000 align 2**16
|
||||||
filesz 0x00009f40 memsz 0x00009f40 flags r-x
|
filesz 0x00009d0c memsz 0x00009d0c flags r-x
|
||||||
LOAD off 0x00010000 vaddr 0x20000000 paddr 0x08009f40 align 2**16
|
LOAD off 0x00010000 vaddr 0x20000000 paddr 0x08009d0c align 2**16
|
||||||
filesz 0x0000006c memsz 0x00000184 flags rw-
|
filesz 0x00000074 memsz 0x0000014c flags rw-
|
||||||
private flags = 5000200: [Version5 EABI] [soft-float ABI]
|
private flags = 5000200: [Version5 EABI] [soft-float ABI]
|
||||||
|
|
||||||
Sections:
|
Sections:
|
||||||
Idx Name Size VMA LMA File off Algn
|
Idx Name Size VMA LMA File off Algn
|
||||||
0 .text 00001f38 08008000 08008000 00008000 2**2
|
0 .text 00001d04 08008000 08008000 00008000 2**2
|
||||||
CONTENTS, ALLOC, LOAD, READONLY, CODE
|
CONTENTS, ALLOC, LOAD, READONLY, CODE
|
||||||
1 .ARM.exidx 00000008 08009f38 08009f38 00009f38 2**2
|
1 .ARM.exidx 00000008 08009d04 08009d04 00009d04 2**2
|
||||||
CONTENTS, ALLOC, LOAD, READONLY, DATA
|
CONTENTS, ALLOC, LOAD, READONLY, DATA
|
||||||
2 .data 0000006c 20000000 08009f40 00010000 2**2
|
2 .data 00000074 20000000 08009d0c 00010000 2**2
|
||||||
CONTENTS, ALLOC, LOAD, DATA
|
CONTENTS, ALLOC, LOAD, DATA
|
||||||
3 .bss 00000118 2000006c 08009fac 0001006c 2**2
|
3 .bss 000000d8 20000074 08009d80 00010074 2**2
|
||||||
ALLOC
|
ALLOC
|
||||||
4 .heap 00000800 20000188 20000188 00010070 2**3
|
4 .heap 00000800 20000150 20000150 00010078 2**3
|
||||||
CONTENTS, READONLY
|
CONTENTS, READONLY
|
||||||
5 .stack_dummy 00000800 20000188 20000188 00010870 2**3
|
5 .stack_dummy 00000800 20000150 20000150 00010878 2**3
|
||||||
CONTENTS, READONLY
|
CONTENTS, READONLY
|
||||||
6 .ARM.attributes 00000029 00000000 00000000 00011070 2**0
|
6 .ARM.attributes 00000029 00000000 00000000 00011078 2**0
|
||||||
CONTENTS, READONLY
|
CONTENTS, READONLY
|
||||||
7 .comment 00000075 00000000 00000000 00011099 2**0
|
7 .comment 00000075 00000000 00000000 000110a1 2**0
|
||||||
CONTENTS, READONLY
|
CONTENTS, READONLY
|
||||||
8 .debug_line 00008987 00000000 00000000 0001110e 2**0
|
8 .debug_line 00007cf9 00000000 00000000 00011116 2**0
|
||||||
CONTENTS, READONLY, DEBUGGING
|
CONTENTS, READONLY, DEBUGGING
|
||||||
9 .debug_info 0000ee11 00000000 00000000 00019a95 2**0
|
9 .debug_info 000097f3 00000000 00000000 00018e0f 2**0
|
||||||
CONTENTS, READONLY, DEBUGGING
|
CONTENTS, READONLY, DEBUGGING
|
||||||
10 .debug_abbrev 00002557 00000000 00000000 000288a6 2**0
|
10 .debug_abbrev 00001bc4 00000000 00000000 00022602 2**0
|
||||||
CONTENTS, READONLY, DEBUGGING
|
CONTENTS, READONLY, DEBUGGING
|
||||||
11 .debug_aranges 00000640 00000000 00000000 0002ae00 2**3
|
11 .debug_aranges 000006f0 00000000 00000000 000241c8 2**3
|
||||||
CONTENTS, READONLY, DEBUGGING
|
CONTENTS, READONLY, DEBUGGING
|
||||||
12 .debug_str 000b83a6 00000000 00000000 0002b440 2**0
|
12 .debug_str 000bb254 00000000 00000000 000248b8 2**0
|
||||||
CONTENTS, READONLY, DEBUGGING
|
CONTENTS, READONLY, DEBUGGING
|
||||||
13 .debug_loc 00004003 00000000 00000000 000e37e6 2**0
|
13 .debug_loc 00003e87 00000000 00000000 000dfb0c 2**0
|
||||||
CONTENTS, READONLY, DEBUGGING
|
CONTENTS, READONLY, DEBUGGING
|
||||||
14 .debug_ranges 000005a8 00000000 00000000 000e77e9 2**0
|
14 .debug_ranges 00000688 00000000 00000000 000e3993 2**0
|
||||||
CONTENTS, READONLY, DEBUGGING
|
CONTENTS, READONLY, DEBUGGING
|
||||||
15 .debug_macro 0001fc8b 00000000 00000000 000e7d91 2**0
|
15 .debug_macro 0001f118 00000000 00000000 000e401b 2**0
|
||||||
CONTENTS, READONLY, DEBUGGING
|
CONTENTS, READONLY, DEBUGGING
|
||||||
16 .debug_frame 00000fb4 00000000 00000000 00107a1c 2**2
|
16 .debug_frame 000010dc 00000000 00000000 00103134 2**2
|
||||||
CONTENTS, READONLY, DEBUGGING
|
CONTENTS, READONLY, DEBUGGING
|
||||||
SYMBOL TABLE:
|
SYMBOL TABLE:
|
||||||
08008000 l d .text 00000000 .text
|
08008000 l d .text 00000000 .text
|
||||||
08009f38 l d .ARM.exidx 00000000 .ARM.exidx
|
08009d04 l d .ARM.exidx 00000000 .ARM.exidx
|
||||||
20000000 l d .data 00000000 .data
|
20000000 l d .data 00000000 .data
|
||||||
2000006c l d .bss 00000000 .bss
|
20000074 l d .bss 00000000 .bss
|
||||||
20000188 l d .heap 00000000 .heap
|
20000150 l d .heap 00000000 .heap
|
||||||
20000188 l d .stack_dummy 00000000 .stack_dummy
|
20000150 l d .stack_dummy 00000000 .stack_dummy
|
||||||
00000000 l d .ARM.attributes 00000000 .ARM.attributes
|
00000000 l d .ARM.attributes 00000000 .ARM.attributes
|
||||||
00000000 l d .comment 00000000 .comment
|
00000000 l d .comment 00000000 .comment
|
||||||
00000000 l d .debug_line 00000000 .debug_line
|
00000000 l d .debug_line 00000000 .debug_line
|
||||||
|
@ -75,18 +75,18 @@ SYMBOL TABLE:
|
||||||
08008280 l .text 00000000 .fill_zero_bss
|
08008280 l .text 00000000 .fill_zero_bss
|
||||||
0800827c l .text 00000000 .loop_zero_bss
|
0800827c l .text 00000000 .loop_zero_bss
|
||||||
00000000 l df *ABS* 00000000 crtstuff.c
|
00000000 l df *ABS* 00000000 crtstuff.c
|
||||||
08009f34 l O .text 00000000 __EH_FRAME_BEGIN__
|
08009d00 l O .text 00000000 __EH_FRAME_BEGIN__
|
||||||
08008188 l F .text 00000000 __do_global_dtors_aux
|
08008188 l F .text 00000000 __do_global_dtors_aux
|
||||||
2000006c l .bss 00000001 completed.8879
|
20000074 l .bss 00000001 completed.8879
|
||||||
20000068 l O .data 00000000 __do_global_dtors_aux_fini_array_entry
|
20000070 l O .data 00000000 __do_global_dtors_aux_fini_array_entry
|
||||||
080081ac l F .text 00000000 frame_dummy
|
080081ac l F .text 00000000 frame_dummy
|
||||||
20000070 l .bss 00000018 object.8884
|
20000078 l .bss 00000018 object.8884
|
||||||
20000064 l O .data 00000000 __frame_dummy_init_array_entry
|
2000006c l O .data 00000000 __frame_dummy_init_array_entry
|
||||||
00000000 l df *ABS* 00000000 c:/progra~2/gnutoo~1/82018-~1/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/crt0.o
|
00000000 l df *ABS* 00000000 c:/progra~2/gnutoo~1/82018-~1/bin/../lib/gcc/arm-none-eabi/8.2.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/crt0.o
|
||||||
00000000 l df *ABS* 00000000 stm32f2xx_hal_gpio.c
|
00000000 l df *ABS* 00000000 stm32f2xx_hal_gpio.c
|
||||||
00000000 l df *ABS* 00000000 stm32f2xx_hal_uart.c
|
00000000 l df *ABS* 00000000 stm32f2xx_hal_uart.c
|
||||||
08008528 l F .text 00000334 UART_SetConfig
|
08008520 l F .text 00000174 UART_SetConfig
|
||||||
0800885c l F .text 00000062 UART_WaitOnFlagUntilTimeout
|
08008694 l F .text 00000062 UART_WaitOnFlagUntilTimeout
|
||||||
00000000 l df *ABS* 00000000 stm32f2xx_hal_can.c
|
00000000 l df *ABS* 00000000 stm32f2xx_hal_can.c
|
||||||
00000000 l df *ABS* 00000000 stm32f2xx_hal.c
|
00000000 l df *ABS* 00000000 stm32f2xx_hal.c
|
||||||
00000000 l df *ABS* 00000000 stm32f2xx_hal_rcc.c
|
00000000 l df *ABS* 00000000 stm32f2xx_hal_rcc.c
|
||||||
|
@ -95,27 +95,26 @@ SYMBOL TABLE:
|
||||||
00000000 l df *ABS* 00000000 _exit.c
|
00000000 l df *ABS* 00000000 _exit.c
|
||||||
00000000 l df *ABS* 00000000 timer.c
|
00000000 l df *ABS* 00000000 timer.c
|
||||||
00000000 l df *ABS* 00000000 led.c
|
00000000 l df *ABS* 00000000 led.c
|
||||||
20000088 l O .bss 00000001 led_toggle_state.7011
|
20000090 l O .bss 00000001 led_toggle_state.6150
|
||||||
2000008c l O .bss 00000004 timer_counter_last.7012
|
20000094 l O .bss 00000004 timer_counter_last.6151
|
||||||
00000000 l df *ABS* 00000000 main.c
|
00000000 l df *ABS* 00000000 main.c
|
||||||
08009724 l F .text 00000010 VectorBase_Config
|
080094f8 l F .text 00000010 VectorBase_Config
|
||||||
08009734 l F .text 00000056 SystemClock_Config
|
08009508 l F .text 00000056 SystemClock_Config
|
||||||
0800978a l F .text 00000018 Init
|
0800955e l F .text 00000018 Init
|
||||||
00000000 l df *ABS* 00000000 boot.c
|
00000000 l df *ABS* 00000000 boot.c
|
||||||
080098ec l F .text 0000002c BootComRs232Init
|
080096c0 l F .text 0000002c BootComRs232Init
|
||||||
08009918 l F .text 00000070 CanGetSpeedConfig
|
080096ec l F .text 00000070 CanGetSpeedConfig
|
||||||
08009988 l F .text 000000a8 BootComCanInit
|
0800975c l F .text 00000098 BootComCanInit
|
||||||
08009a30 l F .text 0000001c Rs232ReceiveByte
|
080097f4 l F .text 0000001c Rs232ReceiveByte
|
||||||
08009a7c l F .text 00000098 BootComRs232CheckActivationRequest
|
08009840 l F .text 00000098 BootComRs232CheckActivationRequest
|
||||||
08009b14 l F .text 00000038 BootComCanCheckActivationRequest
|
080098d8 l F .text 00000040 BootComCanCheckActivationRequest
|
||||||
20000090 l O .bss 00000044 canHandle
|
20000098 l O .bss 00000028 canHandle
|
||||||
200000d4 l O .bss 00000024 canRxMessage
|
200000c0 l O .bss 00000040 rs232Handle
|
||||||
200000f8 l O .bss 00000040 rs232Handle
|
20000100 l O .bss 00000041 xcpCtoReqPacket.6170
|
||||||
20000138 l O .bss 00000041 xcpCtoReqPacket.7031
|
20000141 l O .bss 00000001 xcpCtoRxInProgress.6172
|
||||||
20000179 l O .bss 00000001 xcpCtoRxInProgress.7033
|
20000142 l O .bss 00000001 xcpCtoRxLength.6171
|
||||||
2000017a l O .bss 00000001 xcpCtoRxLength.7032
|
20000144 l O .bss 00000004 xcpCtoRxStartTime.6173
|
||||||
2000017c l O .bss 00000004 xcpCtoRxStartTime.7034
|
08009cd8 l O .text 00000024 canTiming
|
||||||
08009f0c l O .text 00000024 canTiming
|
|
||||||
00000000 l df *ABS* 00000000 _aeabi_uldivmod.o
|
00000000 l df *ABS* 00000000 _aeabi_uldivmod.o
|
||||||
00000000 l df *ABS* 00000000 libgcc2.c
|
00000000 l df *ABS* 00000000 libgcc2.c
|
||||||
00000000 l df *ABS* 00000000 _dvmd_tls.o
|
00000000 l df *ABS* 00000000 _dvmd_tls.o
|
||||||
|
@ -125,173 +124,176 @@ SYMBOL TABLE:
|
||||||
00000000 l df *ABS* 00000000 c:/progra~2/gnutoo~1/82018-~1/bin/../lib/gcc/arm-none-eabi/8.2.1/thumb/v7-m/nofp/crti.o
|
00000000 l df *ABS* 00000000 c:/progra~2/gnutoo~1/82018-~1/bin/../lib/gcc/arm-none-eabi/8.2.1/thumb/v7-m/nofp/crti.o
|
||||||
00000000 l df *ABS* 00000000 c:/progra~2/gnutoo~1/82018-~1/bin/../lib/gcc/arm-none-eabi/8.2.1/thumb/v7-m/nofp/crtn.o
|
00000000 l df *ABS* 00000000 c:/progra~2/gnutoo~1/82018-~1/bin/../lib/gcc/arm-none-eabi/8.2.1/thumb/v7-m/nofp/crtn.o
|
||||||
00000000 l df *ABS* 00000000 impure.c
|
00000000 l df *ABS* 00000000 impure.c
|
||||||
20000004 l O .data 00000060 impure_data
|
2000000c l O .data 00000060 impure_data
|
||||||
00000000 l df *ABS* 00000000 crtstuff.c
|
00000000 l df *ABS* 00000000 crtstuff.c
|
||||||
08009f34 l O .text 00000000 __FRAME_END__
|
08009d00 l O .text 00000000 __FRAME_END__
|
||||||
00000000 l df *ABS* 00000000
|
00000000 l df *ABS* 00000000
|
||||||
20000068 l .data 00000000 __init_array_end
|
20000070 l .data 00000000 __init_array_end
|
||||||
20000064 l .data 00000000 __preinit_array_end
|
2000006c l .data 00000000 __preinit_array_end
|
||||||
20000064 l .data 00000000 __init_array_start
|
2000006c l .data 00000000 __init_array_start
|
||||||
20000064 l .data 00000000 __preinit_array_start
|
2000006c l .data 00000000 __preinit_array_start
|
||||||
080082f0 w F .text 00000002 RTC_Alarm_IRQHandler
|
080082f0 w F .text 00000002 RTC_Alarm_IRQHandler
|
||||||
0800833e w F .text 00000002 HASH_RNG_IRQHandler
|
0800833e w F .text 00000002 HASH_RNG_IRQHandler
|
||||||
080082ae w F .text 00000002 EXTI2_IRQHandler
|
080082ae w F .text 00000002 EXTI2_IRQHandler
|
||||||
08009f04 g O .text 00000008 APBPrescTable
|
08009cd0 g O .text 00000008 APBPrescTable
|
||||||
080082fa w F .text 00000002 TIM8_CC_IRQHandler
|
080082fa w F .text 00000002 TIM8_CC_IRQHandler
|
||||||
20000188 g .heap 00000800 __HeapBase
|
20000150 g .heap 00000800 __HeapBase
|
||||||
08008296 w F .text 00000002 DebugMon_Handler
|
08008296 w F .text 00000002 DebugMon_Handler
|
||||||
00000800 g *ABS* 00000000 __HEAP_SIZE
|
00000800 g *ABS* 00000000 __HEAP_SIZE
|
||||||
20000000 g .data 00000000 __data_start__
|
20000000 g .data 00000000 __data_start__
|
||||||
08009500 g F .text 0000002c HAL_RCC_GetPCLK1Freq
|
080092d4 g F .text 0000002c HAL_RCC_GetPCLK1Freq
|
||||||
0800957c g F .text 00000068 HAL_NVIC_SetPriority
|
08009350 g F .text 00000068 HAL_NVIC_SetPriority
|
||||||
080082d4 w F .text 00000002 TIM1_CC_IRQHandler
|
080082d4 w F .text 00000002 TIM1_CC_IRQHandler
|
||||||
0800952c g F .text 0000002c HAL_RCC_GetPCLK2Freq
|
08009300 g F .text 0000002c HAL_RCC_GetPCLK2Freq
|
||||||
08008326 w F .text 00000002 DMA2_Stream5_IRQHandler
|
08008326 w F .text 00000002 DMA2_Stream5_IRQHandler
|
||||||
0800828c w F .text 00000002 HardFault_Handler
|
0800828c w F .text 00000002 HardFault_Handler
|
||||||
080082be w F .text 00000002 DMA1_Stream5_IRQHandler
|
080082be w F .text 00000002 DMA1_Stream5_IRQHandler
|
||||||
080096b4 g F .text 0000000c SysTick_Handler
|
08009488 g F .text 0000000c SysTick_Handler
|
||||||
0800851c g F .text 0000000c HAL_GPIO_WritePin
|
08008514 g F .text 0000000c HAL_GPIO_WritePin
|
||||||
080082a0 w F .text 00000002 PVD_IRQHandler
|
080082a0 w F .text 00000002 PVD_IRQHandler
|
||||||
08008300 w F .text 00000002 SDIO_IRQHandler
|
08008300 w F .text 00000002 SDIO_IRQHandler
|
||||||
080082a2 w F .text 00000002 TAMP_STAMP_IRQHandler
|
080082a2 w F .text 00000002 TAMP_STAMP_IRQHandler
|
||||||
080094f4 g F .text 0000000c HAL_RCC_GetHCLKFreq
|
080092c8 g F .text 0000000c HAL_RCC_GetHCLKFreq
|
||||||
08008298 w F .text 00000002 PendSV_Handler
|
08008298 w F .text 00000002 PendSV_Handler
|
||||||
0800828a w F .text 00000002 NMI_Handler
|
0800828a w F .text 00000002 NMI_Handler
|
||||||
08009f40 g .ARM.exidx 00000000 __exidx_end
|
08009d0c g .ARM.exidx 00000000 __exidx_end
|
||||||
08008320 w F .text 00000002 CAN2_RX1_IRQHandler
|
08008320 w F .text 00000002 CAN2_RX1_IRQHandler
|
||||||
080082b0 w F .text 00000002 EXTI3_IRQHandler
|
080082b0 w F .text 00000002 EXTI3_IRQHandler
|
||||||
080092ec g F .text 000000a4 HAL_RCC_GetSysClockFreq
|
080090b8 g F .text 000000a4 HAL_RCC_GetSysClockFreq
|
||||||
08009f40 g .ARM.exidx 00000000 __etext
|
08009d0c g .ARM.exidx 00000000 __etext
|
||||||
080082f8 w F .text 00000002 TIM8_TRG_COM_TIM14_IRQHandler
|
080082f8 w F .text 00000002 TIM8_TRG_COM_TIM14_IRQHandler
|
||||||
080097b8 g F .text 00000134 HAL_MspInit
|
0800958c g F .text 00000134 HAL_MspInit
|
||||||
08009630 w F .text 00000002 HAL_SYSTICK_Callback
|
08009404 w F .text 00000002 HAL_SYSTICK_Callback
|
||||||
080082d0 w F .text 00000002 TIM1_UP_TIM10_IRQHandler
|
080082d0 w F .text 00000002 TIM1_UP_TIM10_IRQHandler
|
||||||
080082f6 w F .text 00000002 TIM8_UP_TIM13_IRQHandler
|
080082f6 w F .text 00000002 TIM8_UP_TIM13_IRQHandler
|
||||||
08008330 w F .text 00000002 I2C3_ER_IRQHandler
|
08008330 w F .text 00000002 I2C3_ER_IRQHandler
|
||||||
08008348 g F .text 000001d4 HAL_GPIO_Init
|
08008348 g F .text 000001cc HAL_GPIO_Init
|
||||||
080082aa w F .text 00000002 EXTI0_IRQHandler
|
080082aa w F .text 00000002 EXTI0_IRQHandler
|
||||||
080082e0 w F .text 00000002 I2C2_EV_IRQHandler
|
080082e0 w F .text 00000002 I2C2_EV_IRQHandler
|
||||||
08009b58 g F .text 00000000 .hidden __aeabi_uldivmod
|
08009924 g F .text 00000000 .hidden __aeabi_uldivmod
|
||||||
080082b8 w F .text 00000002 DMA1_Stream2_IRQHandler
|
080082b8 w F .text 00000002 DMA1_Stream2_IRQHandler
|
||||||
080082c6 w F .text 00000002 CAN1_RX0_IRQHandler
|
080082c6 w F .text 00000002 CAN1_RX0_IRQHandler
|
||||||
20000000 g O .data 00000004 SystemCoreClock
|
20000008 g O .data 00000004 SystemCoreClock
|
||||||
08008336 w F .text 00000002 OTG_HS_WKUP_IRQHandler
|
08008336 w F .text 00000002 OTG_HS_WKUP_IRQHandler
|
||||||
|
20000000 g O .data 00000001 uwTickFreq
|
||||||
|
08008ab8 g F .text 0000005c HAL_CAN_Start
|
||||||
08008292 w F .text 00000002 UsageFault_Handler
|
08008292 w F .text 00000002 UsageFault_Handler
|
||||||
08008322 w F .text 00000002 CAN2_SCE_IRQHandler
|
08008322 w F .text 00000002 CAN2_SCE_IRQHandler
|
||||||
08008312 w F .text 00000002 DMA2_Stream2_IRQHandler
|
08008312 w F .text 00000002 DMA2_Stream2_IRQHandler
|
||||||
20000988 g .heap 00000000 __HeapLimit
|
20000950 g .heap 00000000 __HeapLimit
|
||||||
2000006c g .bss 00000000 __bss_start__
|
20000074 g .bss 00000000 __bss_start__
|
||||||
080082e4 w F .text 00000002 SPI1_IRQHandler
|
080082e4 w F .text 00000002 SPI1_IRQHandler
|
||||||
08009b88 g F .text 000002d0 .hidden __udivmoddi4
|
08009954 g F .text 000002d0 .hidden __udivmoddi4
|
||||||
08008a04 g F .text 00000114 HAL_CAN_ConfigFilter
|
0800898c g F .text 0000012c HAL_CAN_ConfigFilter
|
||||||
0800830a w F .text 00000002 TIM6_DAC_IRQHandler
|
0800830a w F .text 00000002 TIM6_DAC_IRQHandler
|
||||||
080082ce w F .text 00000002 TIM1_BRK_TIM9_IRQHandler
|
080082ce w F .text 00000002 TIM1_BRK_TIM9_IRQHandler
|
||||||
0800833a w F .text 00000002 DCMI_IRQHandler
|
0800833a w F .text 00000002 DCMI_IRQHandler
|
||||||
20000180 g O .bss 00000004 uwTick
|
20000148 g O .bss 00000004 uwTick
|
||||||
0800831e w F .text 00000002 CAN2_RX0_IRQHandler
|
0800831e w F .text 00000002 CAN2_RX0_IRQHandler
|
||||||
080095e4 g F .text 0000002c HAL_SYSTICK_Config
|
080093b8 g F .text 0000002c HAL_SYSTICK_Config
|
||||||
08009f38 g .text 00000000 __exidx_start
|
08009d04 g .text 00000000 __exidx_start
|
||||||
08008314 w F .text 00000002 DMA2_Stream3_IRQHandler
|
08008314 w F .text 00000002 DMA2_Stream3_IRQHandler
|
||||||
08009f30 g O .text 00000004 _global_impure_ptr
|
08009cfc g O .text 00000004 _global_impure_ptr
|
||||||
08009e84 g F .text 00000048 __libc_init_array
|
08009c50 g F .text 00000048 __libc_init_array
|
||||||
080081c8 g F .text 00000000 _mainCRTStartup
|
080081c8 g F .text 00000000 _mainCRTStartup
|
||||||
08008b18 w F .text 00000002 HAL_CAN_MspInit
|
0800883e w F .text 00000002 HAL_CAN_MspInit
|
||||||
0800832c w F .text 00000002 USART6_IRQHandler
|
0800832c w F .text 00000002 USART6_IRQHandler
|
||||||
08009edc g F .text 00000000 _init
|
08009ca8 g F .text 00000000 _init
|
||||||
08009a58 g F .text 00000024 BootActivate
|
0800981c g F .text 00000024 BootActivate
|
||||||
080082ec w F .text 00000002 USART3_IRQHandler
|
080082ec w F .text 00000002 USART3_IRQHandler
|
||||||
0800833c w F .text 00000002 CRYP_IRQHandler
|
0800833c w F .text 00000002 CRYP_IRQHandler
|
||||||
0800891e g F .text 000000e4 HAL_UART_Receive
|
08008756 g F .text 000000e8 HAL_UART_Receive
|
||||||
0800823c g F .text 00000038 Reset_Handler
|
0800823c g F .text 00000038 Reset_Handler
|
||||||
080082c8 w F .text 00000002 CAN1_RX1_IRQHandler
|
080082c8 w F .text 00000002 CAN1_RX1_IRQHandler
|
||||||
08008308 w F .text 00000002 UART5_IRQHandler
|
08008308 w F .text 00000002 UART5_IRQHandler
|
||||||
0800830e w F .text 00000002 DMA2_Stream0_IRQHandler
|
0800830e w F .text 00000002 DMA2_Stream0_IRQHandler
|
||||||
08008f4c g F .text 00000034 HAL_Init
|
20000004 g O .data 00000004 uwTickPrio
|
||||||
080096c0 g F .text 00000014 LedInit
|
08008c94 g F .text 00000034 HAL_Init
|
||||||
|
08009494 g F .text 00000014 LedInit
|
||||||
080082da w F .text 00000002 TIM4_IRQHandler
|
080082da w F .text 00000002 TIM4_IRQHandler
|
||||||
20000188 g .heap 00000000 end
|
20000150 g .heap 00000000 end
|
||||||
080082dc w F .text 00000002 I2C1_EV_IRQHandler
|
080082dc w F .text 00000002 I2C1_EV_IRQHandler
|
||||||
080082c0 w F .text 00000002 DMA1_Stream6_IRQHandler
|
080082c0 w F .text 00000002 DMA1_Stream6_IRQHandler
|
||||||
2000006c g .data 00000000 __data_end__
|
20000074 g .data 00000000 __data_end__
|
||||||
080082b6 w F .text 00000002 DMA1_Stream1_IRQHandler
|
080082b6 w F .text 00000002 DMA1_Stream1_IRQHandler
|
||||||
08008306 w F .text 00000002 UART4_IRQHandler
|
08008306 w F .text 00000002 UART4_IRQHandler
|
||||||
20000184 g .bss 00000000 __bss_end__
|
2000014c g .bss 00000000 __bss_end__
|
||||||
00000800 g *ABS* 00000000 __STACK_SIZE
|
00000800 g *ABS* 00000000 __STACK_SIZE
|
||||||
080082d8 w F .text 00000002 TIM3_IRQHandler
|
080082d8 w F .text 00000002 TIM3_IRQHandler
|
||||||
080082a8 w F .text 00000002 RCC_IRQHandler
|
080082a8 w F .text 00000002 RCC_IRQHandler
|
||||||
080082f4 w F .text 00000002 TIM8_BRK_TIM12_IRQHandler
|
080082f4 w F .text 00000002 TIM8_BRK_TIM12_IRQHandler
|
||||||
0800829c w F .text 00000002 Default_Handler
|
0800829c w F .text 00000002 Default_Handler
|
||||||
080081c8 g F .text 00000000 _start
|
080081c8 g F .text 00000000 _start
|
||||||
08009ef4 g O .text 00000010 AHBPrescTable
|
08009cc0 g O .text 00000010 AHBPrescTable
|
||||||
080082ee w F .text 00000002 EXTI15_10_IRQHandler
|
080082ee w F .text 00000002 EXTI15_10_IRQHandler
|
||||||
080082c2 w F .text 00000002 ADC_IRQHandler
|
080082c2 w F .text 00000002 ADC_IRQHandler
|
||||||
08009390 g F .text 00000164 HAL_RCC_ClockConfig
|
0800915c g F .text 0000016c HAL_RCC_ClockConfig
|
||||||
08009558 g F .text 00000024 HAL_NVIC_SetPriorityGrouping
|
0800932c g F .text 00000024 HAL_NVIC_SetPriorityGrouping
|
||||||
080082fc w F .text 00000002 DMA1_Stream7_IRQHandler
|
080082fc w F .text 00000002 DMA1_Stream7_IRQHandler
|
||||||
0800830c w F .text 00000002 TIM7_IRQHandler
|
0800830c w F .text 00000002 TIM7_IRQHandler
|
||||||
0800831c w F .text 00000002 CAN2_TX_IRQHandler
|
0800831c w F .text 00000002 CAN2_TX_IRQHandler
|
||||||
08008302 w F .text 00000002 TIM5_IRQHandler
|
08008302 w F .text 00000002 TIM5_IRQHandler
|
||||||
0800832a w F .text 00000002 DMA2_Stream7_IRQHandler
|
0800832a w F .text 00000002 DMA2_Stream7_IRQHandler
|
||||||
0800832e w F .text 00000002 I2C3_EV_IRQHandler
|
0800832e w F .text 00000002 I2C3_EV_IRQHandler
|
||||||
08009e58 w F .text 00000002 .hidden __aeabi_ldiv0
|
08009c24 w F .text 00000002 .hidden __aeabi_ldiv0
|
||||||
080082cc w F .text 00000002 EXTI9_5_IRQHandler
|
080082cc w F .text 00000002 EXTI9_5_IRQHandler
|
||||||
080082a4 w F .text 00000002 RTC_WKUP_IRQHandler
|
080082a4 w F .text 00000002 RTC_WKUP_IRQHandler
|
||||||
0800831a w F .text 00000002 ETH_WKUP_IRQHandler
|
0800831a w F .text 00000002 ETH_WKUP_IRQHandler
|
||||||
08008f90 w F .text 0000000c HAL_GetTick
|
08008ce0 w F .text 0000000c HAL_GetTick
|
||||||
080082e6 w F .text 00000002 SPI2_IRQHandler
|
080082e6 w F .text 00000002 SPI2_IRQHandler
|
||||||
08008334 w F .text 00000002 OTG_HS_EP1_IN_IRQHandler
|
08008334 w F .text 00000002 OTG_HS_EP1_IN_IRQHandler
|
||||||
08009ecc g F .text 00000010 memset
|
08009c98 g F .text 00000010 memset
|
||||||
0800828e w F .text 00000002 MemManage_Handler
|
0800828e w F .text 00000002 MemManage_Handler
|
||||||
08008000 g .text 00000188 __isr_vector
|
08008000 g .text 00000188 __isr_vector
|
||||||
080097a2 g F .text 00000014 main
|
08009576 g F .text 00000014 main
|
||||||
080082b4 w F .text 00000002 DMA1_Stream0_IRQHandler
|
080082b4 w F .text 00000002 DMA1_Stream0_IRQHandler
|
||||||
|
08008b14 g F .text 00000132 HAL_CAN_GetRxMessage
|
||||||
080082c4 w F .text 00000002 CAN1_TX_IRQHandler
|
080082c4 w F .text 00000002 CAN1_TX_IRQHandler
|
||||||
08008294 w F .text 00000002 SVC_Handler
|
08008294 w F .text 00000002 SVC_Handler
|
||||||
20000188 g .heap 00000000 __end__
|
20000150 g .heap 00000000 __end__
|
||||||
080082b2 w F .text 00000002 EXTI4_IRQHandler
|
080082b2 w F .text 00000002 EXTI4_IRQHandler
|
||||||
08009a4c g F .text 0000000c BootComInit
|
08009810 g F .text 0000000c BootComInit
|
||||||
0800963c g F .text 00000040 SystemInit
|
08009410 g F .text 00000040 SystemInit
|
||||||
08009ee8 g F .text 00000000 _fini
|
08009cb4 g F .text 00000000 _fini
|
||||||
080088be w F .text 00000002 HAL_UART_MspInit
|
080086f6 w F .text 00000002 HAL_UART_MspInit
|
||||||
08008f20 w F .text 0000002c HAL_InitTick
|
08008c48 w F .text 0000004c HAL_InitTick
|
||||||
080082fe w F .text 00000002 FSMC_IRQHandler
|
080082fe w F .text 00000002 FSMC_IRQHandler
|
||||||
20020000 g .bss 00000000 __StackTop
|
20020000 g .bss 00000000 __StackTop
|
||||||
08008318 w F .text 00000002 ETH_IRQHandler
|
08008318 w F .text 00000002 ETH_IRQHandler
|
||||||
08008f80 w F .text 00000010 HAL_IncTick
|
08008cc8 w F .text 00000018 HAL_IncTick
|
||||||
08008332 w F .text 00000002 OTG_HS_EP1_OUT_IRQHandler
|
08008332 w F .text 00000002 OTG_HS_EP1_OUT_IRQHandler
|
||||||
0800829e w F .text 00000002 WWDG_IRQHandler
|
0800829e w F .text 00000002 WWDG_IRQHandler
|
||||||
080096d4 g F .text 00000050 LedToggle
|
080094a8 g F .text 00000050 LedToggle
|
||||||
080082d6 w F .text 00000002 TIM2_IRQHandler
|
080082d6 w F .text 00000002 TIM2_IRQHandler
|
||||||
080082f2 w F .text 00000002 OTG_FS_WKUP_IRQHandler
|
080082f2 w F .text 00000002 OTG_FS_WKUP_IRQHandler
|
||||||
080082d2 w F .text 00000002 TIM1_TRG_COM_TIM11_IRQHandler
|
080082d2 w F .text 00000002 TIM1_TRG_COM_TIM11_IRQHandler
|
||||||
08008338 w F .text 00000002 OTG_HS_IRQHandler
|
08008338 w F .text 00000002 OTG_HS_IRQHandler
|
||||||
08009610 g F .text 00000020 HAL_SYSTICK_CLKSourceConfig
|
080093e4 g F .text 00000020 HAL_SYSTICK_CLKSourceConfig
|
||||||
08008b1a g F .text 00000176 HAL_CAN_Init
|
08008840 g F .text 0000014c HAL_CAN_Init
|
||||||
20020000 g *ABS* 00000000 __stack
|
20020000 g *ABS* 00000000 __stack
|
||||||
080082ac w F .text 00000002 EXTI1_IRQHandler
|
080082ac w F .text 00000002 EXTI1_IRQHandler
|
||||||
2001f800 g *ABS* 00000800 __StackLimit
|
2001f800 g *ABS* 00000800 __StackLimit
|
||||||
080082ea w F .text 00000002 USART2_IRQHandler
|
080082ea w F .text 00000002 USART2_IRQHandler
|
||||||
08008f9c g F .text 00000350 HAL_RCC_OscConfig
|
08008cec g F .text 000003cc HAL_RCC_OscConfig
|
||||||
08009e5c g F .text 00000028 exit
|
08009c28 g F .text 00000028 exit
|
||||||
080082e2 w F .text 00000002 I2C2_ER_IRQHandler
|
080082e2 w F .text 00000002 I2C2_ER_IRQHandler
|
||||||
08008310 w F .text 00000002 DMA2_Stream1_IRQHandler
|
08008310 w F .text 00000002 DMA2_Stream1_IRQHandler
|
||||||
08009b4c g F .text 0000000c BootComCheckActivationRequest
|
08009918 g F .text 0000000c BootComCheckActivationRequest
|
||||||
08009e58 w F .text 00000002 .hidden __aeabi_idiv0
|
08009c24 w F .text 00000002 .hidden __aeabi_idiv0
|
||||||
080082ca w F .text 00000002 CAN1_SCE_IRQHandler
|
080082ca w F .text 00000002 CAN1_SCE_IRQHandler
|
||||||
080082a6 w F .text 00000002 FLASH_IRQHandler
|
080082a6 w F .text 00000002 FLASH_IRQHandler
|
||||||
0800967c w F .text 00000002 _exit
|
08009450 w F .text 00000002 _exit
|
||||||
08008316 w F .text 00000002 DMA2_Stream4_IRQHandler
|
08008316 w F .text 00000002 DMA2_Stream4_IRQHandler
|
||||||
08008290 w F .text 00000002 BusFault_Handler
|
08008290 w F .text 00000002 BusFault_Handler
|
||||||
080082e8 w F .text 00000002 USART1_IRQHandler
|
080082e8 w F .text 00000002 USART1_IRQHandler
|
||||||
08009632 g F .text 00000008 HAL_SYSTICK_IRQHandler
|
08009406 g F .text 00000008 HAL_SYSTICK_IRQHandler
|
||||||
08008324 w F .text 00000002 OTG_FS_IRQHandler
|
08008324 w F .text 00000002 OTG_FS_IRQHandler
|
||||||
08008304 w F .text 00000002 SPI3_IRQHandler
|
08008304 w F .text 00000002 SPI3_IRQHandler
|
||||||
080082bc w F .text 00000002 DMA1_Stream4_IRQHandler
|
080082bc w F .text 00000002 DMA1_Stream4_IRQHandler
|
||||||
080088c0 g F .text 0000005e HAL_UART_Init
|
080086f8 g F .text 0000005e HAL_UART_Init
|
||||||
080082de w F .text 00000002 I2C1_ER_IRQHandler
|
080082de w F .text 00000002 I2C1_ER_IRQHandler
|
||||||
08008c90 g F .text 00000290 HAL_CAN_Receive
|
08009480 g F .text 00000008 TimerGet
|
||||||
080096ac g F .text 00000008 TimerGet
|
08009454 g F .text 0000002c TimerInit
|
||||||
08009680 g F .text 0000002c TimerInit
|
|
||||||
08008328 w F .text 00000002 DMA2_Stream6_IRQHandler
|
08008328 w F .text 00000002 DMA2_Stream6_IRQHandler
|
||||||
080082ba w F .text 00000002 DMA1_Stream3_IRQHandler
|
080082ba w F .text 00000002 DMA1_Stream3_IRQHandler
|
||||||
|
|
||||||
|
|
|
@ -2,7 +2,7 @@ S01E000062696E2F64656D6F70726F675F73746D3332663230372E737265632A
|
||||||
S31508008000000002203D8200088B8200088D8200084D
|
S31508008000000002203D8200088B8200088D8200084D
|
||||||
S315080080108F82000891820008938200080000000001
|
S315080080108F82000891820008938200080000000001
|
||||||
S315080080200000000000000000000000009582000823
|
S315080080200000000000000000000000009582000823
|
||||||
S31508008030978200080000000099820008B59600089B
|
S3150800803097820008000000009982000889940008C9
|
||||||
S315080080409F820008A1820008A3820008A582000872
|
S315080080409F820008A1820008A3820008A582000872
|
||||||
S31508008050A7820008A9820008AB820008AD82000842
|
S31508008050A7820008A9820008AB820008AD82000842
|
||||||
S31508008060AF820008B1820008B3820008B582000812
|
S31508008060AF820008B1820008B3820008B582000812
|
||||||
|
@ -25,21 +25,21 @@ S315080081602F8300083183000833830008358300080D
|
||||||
S3150800817037830008398300083B8300083D830008DD
|
S3150800817037830008398300083B8300083D830008DD
|
||||||
S315080081803F830008EE11AA5510B5054C237833B97C
|
S315080081803F830008EE11AA5510B5054C237833B97C
|
||||||
S31508008190044B13B10448AFF300800123237010BDCC
|
S31508008190044B13B10448AFF300800123237010BDCC
|
||||||
S315080081A06C00002000000000349F000808B5034B4F
|
S315080081A07400002000000000009D000808B5034B7D
|
||||||
S315080081B01BB103490348AFF3008008BD0000000067
|
S315080081B01BB103490348AFF3008008BD0000000067
|
||||||
S315080081C070000020349F0008154B002B08BF134B86
|
S315080081C078000020009D0008154B002B08BF134BB4
|
||||||
S315080081D09D46A3F5803A00218B460F461348144A5C
|
S315080081D09D46A3F5803A00218B460F461348144A5C
|
||||||
S315080081E0121A01F073FE0F4B002B00D098470E4B66
|
S315080081E0121A01F059FD0F4B002B00D098470E4B81
|
||||||
S315080081F0002B00D098470020002104000D000D48F0
|
S315080081F0002B00D098470020002104000D000D48F0
|
||||||
S31508008200002802D00C48AFF3008001F03BFE2000A6
|
S31508008200002802D00C48AFF3008001F021FD2000C1
|
||||||
S31508008210290001F0C6FA01F021FE00BF000008009F
|
S31508008210290001F0B0F901F007FD00BF00000800D1
|
||||||
S315080082200000022000000000000000006C00002092
|
S31508008220000002200000000000000000740000208A
|
||||||
S3150800823084010020000000000000000007498D4668
|
S315080082304C010020000000000000000007498D46A0
|
||||||
S315080082400749084A084B9A42BEBF51F8040B42F840
|
S315080082400749084A084B9A42BEBF51F8040B42F840
|
||||||
S31508008250040BF8E705488047054800470000022058
|
S31508008250040BF8E705488047054800470000022058
|
||||||
S31508008260409F0008000000206C0000203D96000892
|
S315080082600C9D0008000000207400002011940008EE
|
||||||
S31508008270C98100083249334A002301E041F8043B2A
|
S31508008270C98100083249334A002301E041F8043B2A
|
||||||
S315080082809142FBD301F08DFAFEE7FEE7FEE7FEE733
|
S315080082809142FBD301F077F9FEE7FEE7FEE7FEE74A
|
||||||
S31508008290FEE7FEE7FEE7FEE7FEE7FEE7FEE7FEE7A8
|
S31508008290FEE7FEE7FEE7FEE7FEE7FEE7FEE7FEE7A8
|
||||||
S315080082A0FEE7FEE7FEE7FEE7FEE7FEE7FEE7FEE798
|
S315080082A0FEE7FEE7FEE7FEE7FEE7FEE7FEE7FEE798
|
||||||
S315080082B0FEE7FEE7FEE7FEE7FEE7FEE7FEE7FEE788
|
S315080082B0FEE7FEE7FEE7FEE7FEE7FEE7FEE7FEE788
|
||||||
|
@ -51,460 +51,426 @@ S31508008300FEE7FEE7FEE7FEE7FEE7FEE7FEE7FEE737
|
||||||
S31508008310FEE7FEE7FEE7FEE7FEE7FEE7FEE7FEE727
|
S31508008310FEE7FEE7FEE7FEE7FEE7FEE7FEE7FEE727
|
||||||
S31508008320FEE7FEE7FEE7FEE7FEE7FEE7FEE7FEE717
|
S31508008320FEE7FEE7FEE7FEE7FEE7FEE7FEE7FEE717
|
||||||
S31508008330FEE7FEE7FEE7FEE7FEE7FEE7FEE7FEE707
|
S31508008330FEE7FEE7FEE7FEE7FEE7FEE7FEE7FEE707
|
||||||
S315080083406C0000208401002000230F2B00F2DC8043
|
S31508008340740000204C010020F0B583B0002336E00D
|
||||||
S31508008350F0B482B039E0082200E00022B2403A4385
|
S31508008350082400E00024B4403C430235694E46F840
|
||||||
S3150800836002356A4E46F82520694A1568E24302EA4C
|
S315080083602540694C2568D44304EA05064F6817F486
|
||||||
S3150800837005064F6817F4803F01D044EA0506644DA8
|
S31508008370803F01D042EA0506634D2E606D6804EA27
|
||||||
S315080083802E606D6802EA05064F6817F4003F01D0B3
|
S3150800838005064F6817F4003F01D042EA05065E4D20
|
||||||
S3150800839044EA05065E4D6E60AD6802EA05064F685A
|
S315080083906E60AD6804EA05064F6817F4801F01D0C1
|
||||||
S315080083A017F4801F01D044EA0506594DAE60ED6802
|
S315080083A042EA0506584DAE60ED682C404E6816F454
|
||||||
S315080083B02A404E6816F4001F01D044EA0502544CC0
|
S315080083B0001F01D042EA0504534AD46001330A6813
|
||||||
S315080083C0E26001330F2B00F29C8001229A400C6870
|
S315080083C032FA03F400F09B8001249C402240F5D049
|
||||||
S315080083D01440A242F5D14D68022D01D0122D10D1BC
|
S315080083D04D686E1E012E03D9112D01D0122D12D112
|
||||||
S315080083E0DE08083650F826C003F00705AF000F254B
|
S315080083E086685F000325BD4026EA0506CD68BD40C0
|
||||||
S315080083F0BD402CEA050C0D69BD4045EA0C0540F860
|
S315080083F035438560466826EA04064D68C5F30014C9
|
||||||
S31508008400265006685F000325BD40ED4305EA060CC5
|
S315080084009C4034434460C5685F000324BC40E44391
|
||||||
S315080084104E6806F00306BE4046EA0C0606604E683D
|
S3150800841025408E68BE402E43C6604D68022D01D0A9
|
||||||
S3150800842006F1FF3CBCF1010F03D9112E01D0122E23
|
S31508008420122D13D1DE08083650F826E003F00705AA
|
||||||
S3150800843010D1866805EA060CCE68BE4046EA0C06E8
|
S315080084304FEA850C0F2505FA0CF52EEA050E0D698F
|
||||||
S315080084408660466826EA02024E68C6F300169E4013
|
S3150800844005FA0CF545EA0E0540F8265005682C4055
|
||||||
S3150800845016434660C26815408A68BA402A43C26015
|
S315080084504D6805F00305BD402C4304604C6814F0D4
|
||||||
S315080084604A6812F0805FACD000220192294A556C06
|
S31508008460805FABD000240194284C656C45F48045A8
|
||||||
S3150800847045F480455564526C02F480420192019A93
|
S315080084706564646C04F480440194019C9D08AE1CF8
|
||||||
S315080084809D08AE1C214A52F8267003F00302960096
|
S31508008480204C54F8267003F00304A6000F24B440C9
|
||||||
S315080084900F22B24027EA02071F4A90423FF45DAF17
|
S3150800849027EA04071E4CA0423FF45CAF04F580644B
|
||||||
S315080084A002F5806290421ED002F5806290421CD08E
|
S315080084A0A0421ED004F58064A0421CD004F5806466
|
||||||
S315080084B002F5806290421AD002F58062904218D086
|
S315080084B0A0421AD004F58064A04218D004F580645E
|
||||||
S315080084C002F58062904216D002F58062904214D07E
|
S315080084C0A04216D004F58064A04214D004F5806456
|
||||||
S315080084D002F58062904212D002F5806290423FF423
|
S315080084D0A04212D004F58064A0423FF439AF0924C3
|
||||||
S315080084E03AAF09223AE7012238E7022236E70322A1
|
S315080084E039E7012437E7022435E7032433E7042470
|
||||||
S315080084F034E7042232E7052230E706222EE7072270
|
S315080084F031E705242FE706242DE707242BE703B0E9
|
||||||
S315080085002CE702B0F0BC7047704700BF0038014046
|
S31508008500F0BD00BF00380140003C01400038024081
|
||||||
S31508008510003C014000380240000002400AB1816177
|
S31508008510000002400AB18161704709048161704711
|
||||||
S3150800852070470904816170472DE9F84304460168DC
|
S3150800852038B504460268136923F44053C1680B43FF
|
||||||
S315080085300A6922F44052C36813430B610168CA688A
|
S31508008530136183680269134342691343C2691A4384
|
||||||
S3150800854022F4164222F00C0283680069034360692C
|
S315080085400168CB6823F4164323F00C031343CB606E
|
||||||
S315080085500343E06903431343CB6021684A6922F465
|
S315080085500268536923F4407381690B435361C36905
|
||||||
S315080085604072A36913434B61E369B3F5004F60D0CA
|
S31508008560B3F5004F27D00368484A93426DD002F509
|
||||||
S315080085702368B84A934200F0148102F58062934258
|
S315080085708062934269D000F0ADFE00EB800000EB0C
|
||||||
S3150800858000F00F8100F0BCFF00EB800000EB8000DC
|
S31508008580800063689B00B0FBF3F0414DA5FB003209
|
||||||
S315080085906568AD00B0FBF5F5AF4FA7FB05356D096E
|
S315080085905109642202FB110213013233A5FB03239E
|
||||||
S315080085A02E0100F0ADFF00EB800000EB800065684F
|
S315080085A05B0903F0F00202EB011203F00F032168E6
|
||||||
S315080085B0AD00B0FBF5F900F0A3FF00EB800000EB7F
|
S315080085B013448B6068E00368344A934224D002F57A
|
||||||
S315080085C080006568AD00B0FBF5F5A7FB05356D09BC
|
S315080085C08062934220D000F085FE00EB800000EB2D
|
||||||
S315080085D04FF0640808FB15952D013235A7FB0535C4
|
S315080085D0800063685B00B0FBF3F02D4DA5FB00320D
|
||||||
S315080085E06D0905F0F005354400F08AFF00EB8000C0
|
S315080085E05109642202FB1102D3003233A5FB03238F
|
||||||
S315080085F000EB80006668B600B0FBF6F600F080FF78
|
S315080085F05B095A0002F4F87202EB011203F0070352
|
||||||
S3150800860000EB800000EB800063689B00B0FBF3F092
|
S31508008600216813448B603FE000F07AFE00EB80009F
|
||||||
S31508008610A7FB0030400908FB10684FEA081808F164
|
S3150800861000EB800063685B00B0FBF3F01C4DA5FB24
|
||||||
S315080086203208A7FB0837C7F3431723682F449F6010
|
S3150800862000325109642202FB1102D3003233A5FB42
|
||||||
S315080086300DE12368874A93425BD002F58062934234
|
S3150800863003235B095A0002F4F87202EB011203F0F5
|
||||||
S3150800864057D000F05DFF00EB800000EB8000656806
|
S315080086400703216813448B601EE000F059FE00EB17
|
||||||
S315080086506D00B0FBF5F5804FA7FB05356D092E01BA
|
S31508008650800000EB800063689B00B0FBF3F00C4DD4
|
||||||
S3150800866000F04EFF00EB800000EB800065686D00AF
|
S31508008660A5FB00325109642202FB110213013233C1
|
||||||
S31508008670B0FBF5F900F044FF00EB800000EB80004A
|
S31508008670A5FB03235B0903F0F00202EB011203F0EA
|
||||||
S3150800868065686D00B0FBF5F5A7FB05356D094FF07C
|
S315080086800F03216813448B6038BD00BF00100140FA
|
||||||
S31508008690640808FB1595ED003235A7FB05356D090D
|
S315080086901F85EB512DE9F04105460F4616469846CB
|
||||||
S315080086A06D0005F4F875354400F02AFF00EB8000EC
|
S315080086A0069C2B681B6837EA03030CBF01230023CB
|
||||||
S315080086B000EB800066687600B0FBF6F600F020FF57
|
S315080086B0B3421DD1B4F1FF3FF3D02CB100F010FB4B
|
||||||
S315080086C000EB800000EB800063685B00B0FBF3F30F
|
S315080086C0A0EB0800A042ECD92A68D36823F4D0733B
|
||||||
S315080086D0A7FB03235B0908FB13684FEAC80808F1E0
|
S315080086D0D3602A68536923F001035361202385F880
|
||||||
S315080086E03208A7FB0837C7F3421723682F449F6051
|
S315080086E0393085F83A30002385F83830032000E021
|
||||||
S315080086F0ADE000F01BFF00EB800000EB8000656832
|
S315080086F00020BDE8F081704758B310B5044690F8DD
|
||||||
S315080087006D00B0FBF5F5544FA7FB05356D092E0135
|
S3150800870039300BB3242384F839302268D36823F42C
|
||||||
S3150800871000F00CFF00EB800000EB800065686D0040
|
S315080087100053D3602046FFF703FF2268136923F44A
|
||||||
S31508008720B0FBF5F900F002FF00EB800000EB8000DB
|
S31508008720904313612268536923F02A035361226830
|
||||||
S3150800873065686D00B0FBF5F5A7FB05356D094FF0CB
|
S31508008730D36843F40053D3600020E063202384F811
|
||||||
S31508008740640808FB1595ED003235A7FB05356D095C
|
S31508008740393084F83A3010BD80F83830FFF7D3FF57
|
||||||
S315080087506D0005F4F875354400F0E8FE00EB80007E
|
S31508008750D8E7012070472DE9F04383B01E4690F80C
|
||||||
S3150800876000EB800066687600B0FBF6F600F0DEFEE9
|
S315080087603A30DBB2202B5CD104460D4690460029F0
|
||||||
S3150800877000EB800000EB800063685B00B0FBF3F35E
|
S315080087705BD0002A5BD090F83830012B59D0012302
|
||||||
S31508008780A7FB03235B0908FB13684FEAC80808F12F
|
S3150800878080F838304FF00009C0F83C90222380F872
|
||||||
S315080087903208A7FB0837C7F3421723682F449F60A0
|
S315080087903A3000F0A5FA0746A4F82C80A4F82E80F3
|
||||||
S315080087A055E000F0C3FE00EB800000EB8000656832
|
S315080087A084F838901DE000963B460022202120469A
|
||||||
S315080087B0AD00B0FBF5F5284FA7FB05356D092E0171
|
S315080087B0FFF770FF00283ED1236933B923685B6849
|
||||||
S315080087C000F0B4FE00EB800000EB80006568AD00A9
|
S315080087C0C3F3080325F8023B0BE023685B68DBB2BA
|
||||||
S315080087D0B0FBF5F900F0AAFE00EB800000EB800084
|
S315080087D025F8013B05E023685B6803F07F0305F88D
|
||||||
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|
||||||
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||||||
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|
||||||
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||||||
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||||||
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||||||
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||||||
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|
||||||
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|
||||||
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|
||||||
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|
||||||
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|
||||||
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|
||||||
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|
||||||
S7050800800072
|
S7050800800072
|
||||||
|
|
|
@ -127,10 +127,11 @@ static void BootComRs232Init(void)
|
||||||
rs232Handle.Instance = USART3;
|
rs232Handle.Instance = USART3;
|
||||||
rs232Handle.Init.BaudRate = BOOT_COM_RS232_BAUDRATE;
|
rs232Handle.Init.BaudRate = BOOT_COM_RS232_BAUDRATE;
|
||||||
rs232Handle.Init.WordLength = UART_WORDLENGTH_8B;
|
rs232Handle.Init.WordLength = UART_WORDLENGTH_8B;
|
||||||
rs232Handle.Init.StopBits = UART_STOPBITS_1;
|
rs232Handle.Init.StopBits = UART_STOPBITS_1;
|
||||||
rs232Handle.Init.Parity = UART_PARITY_NONE;
|
rs232Handle.Init.Parity = UART_PARITY_NONE;
|
||||||
rs232Handle.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
rs232Handle.Init.Mode = UART_MODE_TX_RX;
|
||||||
rs232Handle.Init.Mode = UART_MODE_TX_RX;
|
rs232Handle.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
||||||
|
rs232Handle.Init.OverSampling = UART_OVERSAMPLING_16;
|
||||||
/* Initialize the UART peripheral. */
|
/* Initialize the UART peripheral. */
|
||||||
HAL_UART_Init(&rs232Handle);
|
HAL_UART_Init(&rs232Handle);
|
||||||
} /*** end of BootComRs232Init ***/
|
} /*** end of BootComRs232Init ***/
|
||||||
|
@ -285,9 +286,6 @@ static const tCanBusTiming canTiming[] =
|
||||||
/** \brief CAN handle to be used in API calls. */
|
/** \brief CAN handle to be used in API calls. */
|
||||||
static CAN_HandleTypeDef canHandle;
|
static CAN_HandleTypeDef canHandle;
|
||||||
|
|
||||||
/** \brief Message buffer for receiving CAN messages. */
|
|
||||||
static CanRxMsgTypeDef canRxMessage;
|
|
||||||
|
|
||||||
|
|
||||||
/************************************************************************************//**
|
/************************************************************************************//**
|
||||||
** \brief Search algorithm to match the desired baudrate to a possible bus
|
** \brief Search algorithm to match the desired baudrate to a possible bus
|
||||||
|
@ -341,7 +339,7 @@ static void BootComCanInit(void)
|
||||||
{
|
{
|
||||||
unsigned short prescaler = 0;
|
unsigned short prescaler = 0;
|
||||||
unsigned char tseg1 = 0, tseg2 = 0;
|
unsigned char tseg1 = 0, tseg2 = 0;
|
||||||
CAN_FilterConfTypeDef filterConfig;
|
CAN_FilterTypeDef filterConfig;
|
||||||
unsigned long rxMsgId = BOOT_COM_CAN_RX_MSG_ID;
|
unsigned long rxMsgId = BOOT_COM_CAN_RX_MSG_ID;
|
||||||
unsigned long rxFilterId, rxFilterMask;
|
unsigned long rxFilterId, rxFilterMask;
|
||||||
|
|
||||||
|
@ -350,18 +348,16 @@ static void BootComCanInit(void)
|
||||||
|
|
||||||
/* set the CAN controller configuration. */
|
/* set the CAN controller configuration. */
|
||||||
canHandle.Instance = CAN1;
|
canHandle.Instance = CAN1;
|
||||||
canHandle.pTxMsg = NULL;
|
canHandle.Init.TimeTriggeredMode = DISABLE;
|
||||||
canHandle.pRxMsg = &canRxMessage;
|
canHandle.Init.AutoBusOff = DISABLE;
|
||||||
canHandle.Init.TTCM = DISABLE;
|
canHandle.Init.AutoWakeUp = DISABLE;
|
||||||
canHandle.Init.ABOM = DISABLE;
|
canHandle.Init.AutoRetransmission = ENABLE;
|
||||||
canHandle.Init.AWUM = DISABLE;
|
canHandle.Init.ReceiveFifoLocked = DISABLE;
|
||||||
canHandle.Init.NART = DISABLE;
|
canHandle.Init.TransmitFifoPriority = DISABLE;
|
||||||
canHandle.Init.RFLM = DISABLE;
|
|
||||||
canHandle.Init.TXFP = DISABLE;
|
|
||||||
canHandle.Init.Mode = CAN_MODE_NORMAL;
|
canHandle.Init.Mode = CAN_MODE_NORMAL;
|
||||||
canHandle.Init.SJW = CAN_SJW_1TQ;
|
canHandle.Init.SyncJumpWidth = CAN_SJW_1TQ;
|
||||||
canHandle.Init.BS1 = ((unsigned long)tseg1 - 1) << CAN_BTR_TS1_Pos;
|
canHandle.Init.TimeSeg1 = ((unsigned long)tseg1 - 1) << CAN_BTR_TS1_Pos;
|
||||||
canHandle.Init.BS2 = ((unsigned long)tseg2 - 1) << CAN_BTR_TS2_Pos;
|
canHandle.Init.TimeSeg2 = ((unsigned long)tseg2 - 1) << CAN_BTR_TS2_Pos;
|
||||||
canHandle.Init.Prescaler = prescaler;
|
canHandle.Init.Prescaler = prescaler;
|
||||||
/* initialize the CAN controller. this only fails if the CAN controller hardware is
|
/* initialize the CAN controller. this only fails if the CAN controller hardware is
|
||||||
* faulty. no need to evaluate the return value as there is nothing we can do about
|
* faulty. no need to evaluate the return value as there is nothing we can do about
|
||||||
|
@ -386,29 +382,20 @@ static void BootComCanInit(void)
|
||||||
/* configure the reception filter. note that the implementation of this function
|
/* configure the reception filter. note that the implementation of this function
|
||||||
* always returns HAL_OK, so no need to evaluate the return value.
|
* always returns HAL_OK, so no need to evaluate the return value.
|
||||||
*/
|
*/
|
||||||
if (canHandle.Instance == CAN1)
|
filterConfig.FilterBank = 0;
|
||||||
{
|
|
||||||
/* filter 0 is the first filter assigned to the bxCAN master (CAN1) */
|
|
||||||
filterConfig.FilterNumber = 0;
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
/* filter 14 is the first filter assigned to the bxCAN slave (CAN2) */
|
|
||||||
filterConfig.FilterNumber = 14;
|
|
||||||
}
|
|
||||||
filterConfig.FilterMode = CAN_FILTERMODE_IDMASK;
|
filterConfig.FilterMode = CAN_FILTERMODE_IDMASK;
|
||||||
filterConfig.FilterScale = CAN_FILTERSCALE_32BIT;
|
filterConfig.FilterScale = CAN_FILTERSCALE_32BIT;
|
||||||
filterConfig.FilterIdHigh = (rxFilterId >> 16) & 0x0000FFFFu;
|
filterConfig.FilterIdHigh = (rxFilterId >> 16) & 0x0000FFFFu;
|
||||||
filterConfig.FilterIdLow = rxFilterId & 0x0000FFFFu;
|
filterConfig.FilterIdLow = rxFilterId & 0x0000FFFFu;
|
||||||
filterConfig.FilterMaskIdHigh = (rxFilterMask >> 16) & 0x0000FFFFu;
|
filterConfig.FilterMaskIdHigh = (rxFilterMask >> 16) & 0x0000FFFFu;
|
||||||
filterConfig.FilterMaskIdLow = rxFilterMask & 0x0000FFFFu;
|
filterConfig.FilterMaskIdLow = rxFilterMask & 0x0000FFFFu;
|
||||||
filterConfig.FilterFIFOAssignment = 0;
|
filterConfig.FilterFIFOAssignment = CAN_RX_FIFO0;
|
||||||
filterConfig.FilterActivation = ENABLE;
|
filterConfig.FilterActivation = ENABLE;
|
||||||
/* select the start slave bank number (for CAN1). this configuration assigns filter
|
filterConfig.SlaveStartFilterBank = 14;
|
||||||
* banks 0..13 to CAN1 and 14..27 to CAN2.
|
|
||||||
*/
|
|
||||||
filterConfig.BankNumber = 14;
|
|
||||||
(void)HAL_CAN_ConfigFilter(&canHandle, &filterConfig);
|
(void)HAL_CAN_ConfigFilter(&canHandle, &filterConfig);
|
||||||
|
/* start the CAN peripheral. no need to evaluate the return value as there is nothing
|
||||||
|
* we can do about a faulty CAN controller. */
|
||||||
|
(void)HAL_CAN_Start(&canHandle);
|
||||||
} /*** end of BootComCanInit ***/
|
} /*** end of BootComCanInit ***/
|
||||||
|
|
||||||
|
|
||||||
|
@ -422,16 +409,18 @@ static void BootComCanCheckActivationRequest(void)
|
||||||
{
|
{
|
||||||
unsigned long rxMsgId = BOOT_COM_CAN_RX_MSG_ID;
|
unsigned long rxMsgId = BOOT_COM_CAN_RX_MSG_ID;
|
||||||
unsigned char packetIdMatches = 0;
|
unsigned char packetIdMatches = 0;
|
||||||
|
CAN_RxHeaderTypeDef rxMsgHeader;
|
||||||
|
unsigned char rxMsgData[8];
|
||||||
|
|
||||||
/* poll for received CAN messages that await processing. */
|
/* poll for received CAN messages that await processing. */
|
||||||
if (HAL_CAN_Receive(&canHandle, CAN_FIFO0, 0) == HAL_OK)
|
if (HAL_CAN_GetRxMessage(&canHandle, CAN_RX_FIFO0, &rxMsgHeader, rxMsgData) == HAL_OK)
|
||||||
{
|
{
|
||||||
/* check if this message has the configured CAN packet identifier. */
|
/* check if this message has the configured CAN packet identifier. */
|
||||||
if ((rxMsgId & 0x80000000) == 0)
|
if ((rxMsgId & 0x80000000) == 0)
|
||||||
{
|
{
|
||||||
/* was an 11-bit CAN message received that matches? */
|
/* was an 11-bit CAN message received that matches? */
|
||||||
if ( (canHandle.pRxMsg->StdId == rxMsgId) &&
|
if ( (rxMsgHeader.StdId == rxMsgId) &&
|
||||||
(canHandle.pRxMsg->IDE == CAN_ID_STD) )
|
(rxMsgHeader.IDE == CAN_ID_STD) )
|
||||||
{
|
{
|
||||||
/* set flag that a packet with a matching CAN identifier was received. */
|
/* set flag that a packet with a matching CAN identifier was received. */
|
||||||
packetIdMatches = 1;
|
packetIdMatches = 1;
|
||||||
|
@ -442,8 +431,8 @@ static void BootComCanCheckActivationRequest(void)
|
||||||
/* negate the ID-type bit */
|
/* negate the ID-type bit */
|
||||||
rxMsgId &= ~0x80000000;
|
rxMsgId &= ~0x80000000;
|
||||||
/* was an 29-bit CAN message received that matches? */
|
/* was an 29-bit CAN message received that matches? */
|
||||||
if ( (canHandle.pRxMsg->ExtId == rxMsgId) &&
|
if ( (rxMsgHeader.ExtId == rxMsgId) &&
|
||||||
(canHandle.pRxMsg->IDE == CAN_ID_EXT) )
|
(rxMsgHeader.IDE == CAN_ID_EXT) )
|
||||||
{
|
{
|
||||||
/* set flag that a packet with a matching CAN identifier was received. */
|
/* set flag that a packet with a matching CAN identifier was received. */
|
||||||
packetIdMatches = 1;
|
packetIdMatches = 1;
|
||||||
|
@ -454,7 +443,7 @@ static void BootComCanCheckActivationRequest(void)
|
||||||
if (packetIdMatches == 1)
|
if (packetIdMatches == 1)
|
||||||
{
|
{
|
||||||
/* check if this was an XCP CONNECT command */
|
/* check if this was an XCP CONNECT command */
|
||||||
if ((canHandle.pRxMsg->Data[0] == 0xff) && (canHandle.pRxMsg->DLC == 2))
|
if ((rxMsgData[0] == 0xff) && (rxMsgHeader.DLC == 2))
|
||||||
{
|
{
|
||||||
/* connection request received so start the bootloader */
|
/* connection request received so start the bootloader */
|
||||||
BootActivate();
|
BootActivate();
|
||||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -16,29 +16,13 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
*
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
*/
|
*/
|
||||||
|
@ -97,11 +81,11 @@
|
||||||
#endif /* USE_HAL_DRIVER */
|
#endif /* USE_HAL_DRIVER */
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief CMSIS Device version number V2.2.1
|
* @brief CMSIS Device version number V2.2.3
|
||||||
*/
|
*/
|
||||||
#define __STM32F2xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
|
#define __STM32F2xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
|
||||||
#define __STM32F2xx_CMSIS_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */
|
#define __STM32F2xx_CMSIS_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */
|
||||||
#define __STM32F2xx_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
|
#define __STM32F2xx_CMSIS_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */
|
||||||
#define __STM32F2xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
|
#define __STM32F2xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
|
||||||
#define __STM32F2xx_CMSIS_VERSION ((__STM32F2xx_CMSIS_VERSION_MAIN << 24)\
|
#define __STM32F2xx_CMSIS_VERSION ((__STM32F2xx_CMSIS_VERSION_MAIN << 24)\
|
||||||
|(__STM32F2xx_CMSIS_VERSION_SUB1 << 16)\
|
|(__STM32F2xx_CMSIS_VERSION_SUB1 << 16)\
|
||||||
|
@ -137,21 +121,21 @@
|
||||||
*/
|
*/
|
||||||
typedef enum
|
typedef enum
|
||||||
{
|
{
|
||||||
RESET = 0,
|
RESET = 0U,
|
||||||
SET = !RESET
|
SET = !RESET
|
||||||
} FlagStatus, ITStatus;
|
} FlagStatus, ITStatus;
|
||||||
|
|
||||||
typedef enum
|
typedef enum
|
||||||
{
|
{
|
||||||
DISABLE = 0,
|
DISABLE = 0U,
|
||||||
ENABLE = !DISABLE
|
ENABLE = !DISABLE
|
||||||
} FunctionalState;
|
} FunctionalState;
|
||||||
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
|
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
|
||||||
|
|
||||||
typedef enum
|
typedef enum
|
||||||
{
|
{
|
||||||
ERROR = 0,
|
SUCCESS = 0U,
|
||||||
SUCCESS = !ERROR
|
ERROR = !SUCCESS
|
||||||
} ErrorStatus;
|
} ErrorStatus;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
|
@ -2,36 +2,20 @@
|
||||||
******************************************************************************
|
******************************************************************************
|
||||||
* @file system_stm32f2xx.h
|
* @file system_stm32f2xx.h
|
||||||
* @author MCD Application Team
|
* @author MCD Application Team
|
||||||
* @brief CMSIS Cortex-M3 Device System Source File for STM32F2xx devices.
|
* @brief CMSIS Cortex-M3 Device System Source File for STM32F2xx devices.
|
||||||
******************************************************************************
|
****************************************************************************
|
||||||
* @attention
|
* @attention
|
||||||
*
|
*
|
||||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||||
|
* All rights reserved.</center></h2>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without modification,
|
* This software component is licensed by ST under BSD 3-Clause license,
|
||||||
* are permitted provided that the following conditions are met:
|
* the "License"; You may not use this file except in compliance with the
|
||||||
* 1. Redistributions of source code must retain the above copyright notice,
|
* License. You may obtain a copy of the License at:
|
||||||
* this list of conditions and the following disclaimer.
|
* opensource.org/licenses/BSD-3-Clause
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
||||||
* this list of conditions and the following disclaimer in the documentation
|
|
||||||
* and/or other materials provided with the distribution.
|
|
||||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
*
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
******************************************************************************
|
||||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
*/
|
||||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
||||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
||||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
||||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
||||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
||||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
******************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
/** @addtogroup CMSIS
|
/** @addtogroup CMSIS
|
||||||
* @{
|
* @{
|
||||||
|
|
|
@ -1,136 +0,0 @@
|
||||||
/* ----------------------------------------------------------------------
|
|
||||||
* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* $Date: 19. October 2015
|
|
||||||
* $Revision: V.1.4.5 a
|
|
||||||
*
|
|
||||||
* Project: CMSIS DSP Library
|
|
||||||
* Title: arm_common_tables.h
|
|
||||||
*
|
|
||||||
* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
|
|
||||||
*
|
|
||||||
* Target Processor: Cortex-M4/Cortex-M3
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions
|
|
||||||
* are met:
|
|
||||||
* - Redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer.
|
|
||||||
* - Redistributions in binary form must reproduce the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer in
|
|
||||||
* the documentation and/or other materials provided with the
|
|
||||||
* distribution.
|
|
||||||
* - Neither the name of ARM LIMITED nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this
|
|
||||||
* software without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
||||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
||||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
|
||||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
|
||||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
|
||||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
|
||||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
|
||||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
|
||||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
|
||||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
||||||
* POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
* -------------------------------------------------------------------- */
|
|
||||||
|
|
||||||
#ifndef _ARM_COMMON_TABLES_H
|
|
||||||
#define _ARM_COMMON_TABLES_H
|
|
||||||
|
|
||||||
#include "arm_math.h"
|
|
||||||
|
|
||||||
extern const uint16_t armBitRevTable[1024];
|
|
||||||
extern const q15_t armRecipTableQ15[64];
|
|
||||||
extern const q31_t armRecipTableQ31[64];
|
|
||||||
/* extern const q31_t realCoefAQ31[1024]; */
|
|
||||||
/* extern const q31_t realCoefBQ31[1024]; */
|
|
||||||
extern const float32_t twiddleCoef_16[32];
|
|
||||||
extern const float32_t twiddleCoef_32[64];
|
|
||||||
extern const float32_t twiddleCoef_64[128];
|
|
||||||
extern const float32_t twiddleCoef_128[256];
|
|
||||||
extern const float32_t twiddleCoef_256[512];
|
|
||||||
extern const float32_t twiddleCoef_512[1024];
|
|
||||||
extern const float32_t twiddleCoef_1024[2048];
|
|
||||||
extern const float32_t twiddleCoef_2048[4096];
|
|
||||||
extern const float32_t twiddleCoef_4096[8192];
|
|
||||||
#define twiddleCoef twiddleCoef_4096
|
|
||||||
extern const q31_t twiddleCoef_16_q31[24];
|
|
||||||
extern const q31_t twiddleCoef_32_q31[48];
|
|
||||||
extern const q31_t twiddleCoef_64_q31[96];
|
|
||||||
extern const q31_t twiddleCoef_128_q31[192];
|
|
||||||
extern const q31_t twiddleCoef_256_q31[384];
|
|
||||||
extern const q31_t twiddleCoef_512_q31[768];
|
|
||||||
extern const q31_t twiddleCoef_1024_q31[1536];
|
|
||||||
extern const q31_t twiddleCoef_2048_q31[3072];
|
|
||||||
extern const q31_t twiddleCoef_4096_q31[6144];
|
|
||||||
extern const q15_t twiddleCoef_16_q15[24];
|
|
||||||
extern const q15_t twiddleCoef_32_q15[48];
|
|
||||||
extern const q15_t twiddleCoef_64_q15[96];
|
|
||||||
extern const q15_t twiddleCoef_128_q15[192];
|
|
||||||
extern const q15_t twiddleCoef_256_q15[384];
|
|
||||||
extern const q15_t twiddleCoef_512_q15[768];
|
|
||||||
extern const q15_t twiddleCoef_1024_q15[1536];
|
|
||||||
extern const q15_t twiddleCoef_2048_q15[3072];
|
|
||||||
extern const q15_t twiddleCoef_4096_q15[6144];
|
|
||||||
extern const float32_t twiddleCoef_rfft_32[32];
|
|
||||||
extern const float32_t twiddleCoef_rfft_64[64];
|
|
||||||
extern const float32_t twiddleCoef_rfft_128[128];
|
|
||||||
extern const float32_t twiddleCoef_rfft_256[256];
|
|
||||||
extern const float32_t twiddleCoef_rfft_512[512];
|
|
||||||
extern const float32_t twiddleCoef_rfft_1024[1024];
|
|
||||||
extern const float32_t twiddleCoef_rfft_2048[2048];
|
|
||||||
extern const float32_t twiddleCoef_rfft_4096[4096];
|
|
||||||
|
|
||||||
|
|
||||||
/* floating-point bit reversal tables */
|
|
||||||
#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )
|
|
||||||
#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )
|
|
||||||
#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )
|
|
||||||
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
|
|
||||||
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
|
|
||||||
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
|
|
||||||
#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
|
|
||||||
#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
|
|
||||||
#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
|
|
||||||
|
|
||||||
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
|
|
||||||
|
|
||||||
/* fixed-point bit reversal tables */
|
|
||||||
#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 )
|
|
||||||
#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 )
|
|
||||||
#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 )
|
|
||||||
#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
|
|
||||||
#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
|
|
||||||
#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
|
|
||||||
#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
|
|
||||||
#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
|
|
||||||
#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
|
|
||||||
|
|
||||||
extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
|
|
||||||
extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
|
|
||||||
|
|
||||||
/* Tables for Fast Math Sine and Cosine */
|
|
||||||
extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
|
|
||||||
extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
|
|
||||||
extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
|
|
||||||
|
|
||||||
#endif /* ARM_COMMON_TABLES_H */
|
|
|
@ -1,79 +0,0 @@
|
||||||
/* ----------------------------------------------------------------------
|
|
||||||
* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
|
|
||||||
*
|
|
||||||
* $Date: 19. March 2015
|
|
||||||
* $Revision: V.1.4.5
|
|
||||||
*
|
|
||||||
* Project: CMSIS DSP Library
|
|
||||||
* Title: arm_const_structs.h
|
|
||||||
*
|
|
||||||
* Description: This file has constant structs that are initialized for
|
|
||||||
* user convenience. For example, some can be given as
|
|
||||||
* arguments to the arm_cfft_f32() function.
|
|
||||||
*
|
|
||||||
* Target Processor: Cortex-M4/Cortex-M3
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions
|
|
||||||
* are met:
|
|
||||||
* - Redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer.
|
|
||||||
* - Redistributions in binary form must reproduce the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer in
|
|
||||||
* the documentation and/or other materials provided with the
|
|
||||||
* distribution.
|
|
||||||
* - Neither the name of ARM LIMITED nor the names of its contributors
|
|
||||||
* may be used to endorse or promote products derived from this
|
|
||||||
* software without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
||||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
||||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
|
||||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
|
||||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
|
||||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
|
||||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
|
||||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
||||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
|
||||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
|
||||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
||||||
* POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
* -------------------------------------------------------------------- */
|
|
||||||
|
|
||||||
#ifndef _ARM_CONST_STRUCTS_H
|
|
||||||
#define _ARM_CONST_STRUCTS_H
|
|
||||||
|
|
||||||
#include "arm_math.h"
|
|
||||||
#include "arm_common_tables.h"
|
|
||||||
|
|
||||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
|
|
||||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
|
|
||||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
|
|
||||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
|
|
||||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
|
|
||||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
|
|
||||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
|
|
||||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
|
|
||||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
|
|
||||||
|
|
||||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
|
|
||||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
|
|
||||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
|
|
||||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
|
|
||||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
|
|
||||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
|
|
||||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
|
|
||||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
|
|
||||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
|
|
||||||
|
|
||||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
|
|
||||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
|
|
||||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
|
|
||||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
|
|
||||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
|
|
||||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
|
|
||||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
|
|
||||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
|
|
||||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
|
|
||||||
|
|
||||||
#endif
|
|
File diff suppressed because it is too large
Load Diff
|
@ -1,43 +1,104 @@
|
||||||
/**************************************************************************//**
|
/**************************************************************************//**
|
||||||
* @file cmsis_armcc.h
|
* @file cmsis_armcc.h
|
||||||
* @brief CMSIS Cortex-M Core Function/Instruction Header File
|
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
|
||||||
* @version V4.30
|
* @version V5.0.4
|
||||||
* @date 20. October 2015
|
* @date 10. January 2018
|
||||||
******************************************************************************/
|
******************************************************************************/
|
||||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
/*
|
||||||
|
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||||
All rights reserved.
|
*
|
||||||
Redistribution and use in source and binary forms, with or without
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
modification, are permitted provided that the following conditions are met:
|
*
|
||||||
- Redistributions of source code must retain the above copyright
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
notice, this list of conditions and the following disclaimer.
|
* not use this file except in compliance with the License.
|
||||||
- Redistributions in binary form must reproduce the above copyright
|
* You may obtain a copy of the License at
|
||||||
notice, this list of conditions and the following disclaimer in the
|
*
|
||||||
documentation and/or other materials provided with the distribution.
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
- Neither the name of ARM nor the names of its contributors may be used
|
*
|
||||||
to endorse or promote products derived from this software without
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
specific prior written permission.
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
*
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
* See the License for the specific language governing permissions and
|
||||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
* limitations under the License.
|
||||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
*/
|
||||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
|
||||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
|
||||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
|
||||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
|
||||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
|
||||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
|
||||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
||||||
POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
---------------------------------------------------------------------------*/
|
|
||||||
|
|
||||||
|
|
||||||
#ifndef __CMSIS_ARMCC_H
|
#ifndef __CMSIS_ARMCC_H
|
||||||
#define __CMSIS_ARMCC_H
|
#define __CMSIS_ARMCC_H
|
||||||
|
|
||||||
|
|
||||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
|
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
|
||||||
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
|
#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* CMSIS compiler control architecture macros */
|
||||||
|
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
|
||||||
|
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
|
||||||
|
#define __ARM_ARCH_6M__ 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
|
||||||
|
#define __ARM_ARCH_7M__ 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
|
||||||
|
#define __ARM_ARCH_7EM__ 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* __ARM_ARCH_8M_BASE__ not applicable */
|
||||||
|
/* __ARM_ARCH_8M_MAIN__ not applicable */
|
||||||
|
|
||||||
|
|
||||||
|
/* CMSIS compiler specific defines */
|
||||||
|
#ifndef __ASM
|
||||||
|
#define __ASM __asm
|
||||||
|
#endif
|
||||||
|
#ifndef __INLINE
|
||||||
|
#define __INLINE __inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_INLINE
|
||||||
|
#define __STATIC_INLINE static __inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_FORCEINLINE
|
||||||
|
#define __STATIC_FORCEINLINE static __forceinline
|
||||||
|
#endif
|
||||||
|
#ifndef __NO_RETURN
|
||||||
|
#define __NO_RETURN __declspec(noreturn)
|
||||||
|
#endif
|
||||||
|
#ifndef __USED
|
||||||
|
#define __USED __attribute__((used))
|
||||||
|
#endif
|
||||||
|
#ifndef __WEAK
|
||||||
|
#define __WEAK __attribute__((weak))
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED
|
||||||
|
#define __PACKED __attribute__((packed))
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_STRUCT
|
||||||
|
#define __PACKED_STRUCT __packed struct
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_UNION
|
||||||
|
#define __PACKED_UNION __packed union
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||||
|
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_WRITE
|
||||||
|
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_READ
|
||||||
|
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_WRITE
|
||||||
|
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_READ
|
||||||
|
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
|
||||||
|
#endif
|
||||||
|
#ifndef __ALIGNED
|
||||||
|
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||||
|
#endif
|
||||||
|
#ifndef __RESTRICT
|
||||||
|
#define __RESTRICT __restrict
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* ########################### Core Function Access ########################### */
|
/* ########################### Core Function Access ########################### */
|
||||||
|
@ -46,7 +107,19 @@
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Enable IRQ Interrupts
|
||||||
|
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
|
||||||
|
Can only be executed in Privileged modes.
|
||||||
|
*/
|
||||||
/* intrinsic void __enable_irq(); */
|
/* intrinsic void __enable_irq(); */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Disable IRQ Interrupts
|
||||||
|
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
|
||||||
|
Can only be executed in Privileged modes.
|
||||||
|
*/
|
||||||
/* intrinsic void __disable_irq(); */
|
/* intrinsic void __disable_irq(); */
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
@ -181,7 +254,8 @@ __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
|
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Enable FIQ
|
\brief Enable FIQ
|
||||||
|
@ -256,14 +330,13 @@ __STATIC_INLINE uint32_t __get_FAULTMASK(void)
|
||||||
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||||
{
|
{
|
||||||
register uint32_t __regFaultMask __ASM("faultmask");
|
register uint32_t __regFaultMask __ASM("faultmask");
|
||||||
__regFaultMask = (faultMask & (uint32_t)1);
|
__regFaultMask = (faultMask & (uint32_t)1U);
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
|
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||||
|
|
||||||
|
|
||||||
#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Get FPSCR
|
\brief Get FPSCR
|
||||||
\details Returns the current value of the Floating Point Status/Control register.
|
\details Returns the current value of the Floating Point Status/Control register.
|
||||||
|
@ -271,7 +344,8 @@ __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE uint32_t __get_FPSCR(void)
|
__STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||||
{
|
{
|
||||||
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
|
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||||
|
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||||
register uint32_t __regfpscr __ASM("fpscr");
|
register uint32_t __regfpscr __ASM("fpscr");
|
||||||
return(__regfpscr);
|
return(__regfpscr);
|
||||||
#else
|
#else
|
||||||
|
@ -287,15 +361,15 @@ __STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||||
*/
|
*/
|
||||||
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||||
{
|
{
|
||||||
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
|
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||||
|
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||||
register uint32_t __regfpscr __ASM("fpscr");
|
register uint32_t __regfpscr __ASM("fpscr");
|
||||||
__regfpscr = (fpscr);
|
__regfpscr = (fpscr);
|
||||||
|
#else
|
||||||
|
(void)fpscr;
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/*@} end of CMSIS_Core_RegAccFunctions */
|
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||||
|
|
||||||
|
@ -369,9 +443,10 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||||
__schedule_barrier();\
|
__schedule_barrier();\
|
||||||
} while (0U)
|
} while (0U)
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Reverse byte order (32 bit)
|
\brief Reverse byte order (32 bit)
|
||||||
\details Reverses the byte order in integer value.
|
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
|
||||||
\param [in] value Value to reverse
|
\param [in] value Value to reverse
|
||||||
\return Reversed value
|
\return Reversed value
|
||||||
*/
|
*/
|
||||||
|
@ -380,7 +455,7 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Reverse byte order (16 bit)
|
\brief Reverse byte order (16 bit)
|
||||||
\details Reverses the byte order in two unsigned short values.
|
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
|
||||||
\param [in] value Value to reverse
|
\param [in] value Value to reverse
|
||||||
\return Reversed value
|
\return Reversed value
|
||||||
*/
|
*/
|
||||||
|
@ -392,14 +467,15 @@ __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(u
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief Reverse byte order in signed short value
|
\brief Reverse byte order (16 bit)
|
||||||
\details Reverses the byte order in a signed short value with sign extension to integer.
|
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
|
||||||
\param [in] value Value to reverse
|
\param [in] value Value to reverse
|
||||||
\return Reversed value
|
\return Reversed value
|
||||||
*/
|
*/
|
||||||
#ifndef __NO_EMBEDDED_ASM
|
#ifndef __NO_EMBEDDED_ASM
|
||||||
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
|
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
|
||||||
{
|
{
|
||||||
revsh r0, r0
|
revsh r0, r0
|
||||||
bx lr
|
bx lr
|
||||||
|
@ -410,8 +486,8 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
|
||||||
/**
|
/**
|
||||||
\brief Rotate Right in unsigned value (32 bit)
|
\brief Rotate Right in unsigned value (32 bit)
|
||||||
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||||
\param [in] value Value to rotate
|
\param [in] op1 Value to rotate
|
||||||
\param [in] value Number of Bits to rotate
|
\param [in] op2 Number of Bits to rotate
|
||||||
\return Rotated value
|
\return Rotated value
|
||||||
*/
|
*/
|
||||||
#define __ROR __ror
|
#define __ROR __ror
|
||||||
|
@ -433,23 +509,24 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
|
||||||
\param [in] value Value to reverse
|
\param [in] value Value to reverse
|
||||||
\return Reversed value
|
\return Reversed value
|
||||||
*/
|
*/
|
||||||
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
|
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||||
#define __RBIT __rbit
|
#define __RBIT __rbit
|
||||||
#else
|
#else
|
||||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||||
{
|
{
|
||||||
uint32_t result;
|
uint32_t result;
|
||||||
int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
|
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
|
||||||
|
|
||||||
result = value; /* r will be reversed bits of v; first get LSB of v */
|
result = value; /* r will be reversed bits of v; first get LSB of v */
|
||||||
for (value >>= 1U; value; value >>= 1U)
|
for (value >>= 1U; value != 0U; value >>= 1U)
|
||||||
{
|
{
|
||||||
result <<= 1U;
|
result <<= 1U;
|
||||||
result |= value & 1U;
|
result |= value & 1U;
|
||||||
s--;
|
s--;
|
||||||
}
|
}
|
||||||
result <<= s; /* shift when v's highest bits are zero */
|
result <<= s; /* shift when v's highest bits are zero */
|
||||||
return(result);
|
return result;
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
@ -463,7 +540,8 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||||
#define __CLZ __clz
|
#define __CLZ __clz
|
||||||
|
|
||||||
|
|
||||||
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
|
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||||
|
|
||||||
/**
|
/**
|
||||||
\brief LDR Exclusive (8 bit)
|
\brief LDR Exclusive (8 bit)
|
||||||
|
@ -645,7 +723,60 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
|
||||||
*/
|
*/
|
||||||
#define __STRT(value, ptr) __strt(value, ptr)
|
#define __STRT(value, ptr) __strt(value, ptr)
|
||||||
|
|
||||||
#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
|
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Signed Saturate
|
||||||
|
\details Saturates a signed value.
|
||||||
|
\param [in] value Value to be saturated
|
||||||
|
\param [in] sat Bit position to saturate to (1..32)
|
||||||
|
\return Saturated value
|
||||||
|
*/
|
||||||
|
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
|
||||||
|
{
|
||||||
|
if ((sat >= 1U) && (sat <= 32U))
|
||||||
|
{
|
||||||
|
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
|
||||||
|
const int32_t min = -1 - max ;
|
||||||
|
if (val > max)
|
||||||
|
{
|
||||||
|
return max;
|
||||||
|
}
|
||||||
|
else if (val < min)
|
||||||
|
{
|
||||||
|
return min;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return val;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Unsigned Saturate
|
||||||
|
\details Saturates an unsigned value.
|
||||||
|
\param [in] value Value to be saturated
|
||||||
|
\param [in] sat Bit position to saturate to (0..31)
|
||||||
|
\return Saturated value
|
||||||
|
*/
|
||||||
|
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
|
||||||
|
{
|
||||||
|
if (sat <= 31U)
|
||||||
|
{
|
||||||
|
const uint32_t max = ((1U << sat) - 1U);
|
||||||
|
if (val > (int32_t)max)
|
||||||
|
{
|
||||||
|
return max;
|
||||||
|
}
|
||||||
|
else if (val < 0)
|
||||||
|
{
|
||||||
|
return 0U;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return (uint32_t)val;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||||
|
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||||
|
|
||||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||||
|
|
||||||
|
@ -656,7 +787,7 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
|
||||||
@{
|
@{
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */
|
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||||
|
|
||||||
#define __SADD8 __sadd8
|
#define __SADD8 __sadd8
|
||||||
#define __QADD8 __qadd8
|
#define __QADD8 __qadd8
|
||||||
|
@ -727,7 +858,7 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
|
||||||
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
|
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
|
||||||
((int64_t)(ARG3) << 32U) ) >> 32U))
|
((int64_t)(ARG3) << 32U) ) >> 32U))
|
||||||
|
|
||||||
#endif /* (__CORTEX_M >= 0x04) */
|
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||||
/*@} end of group CMSIS_SIMD_intrinsics */
|
/*@} end of group CMSIS_SIMD_intrinsics */
|
||||||
|
|
||||||
|
|
||||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,266 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file cmsis_compiler.h
|
||||||
|
* @brief CMSIS compiler generic header file
|
||||||
|
* @version V5.0.4
|
||||||
|
* @date 10. January 2018
|
||||||
|
******************************************************************************/
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __CMSIS_COMPILER_H
|
||||||
|
#define __CMSIS_COMPILER_H
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Arm Compiler 4/5
|
||||||
|
*/
|
||||||
|
#if defined ( __CC_ARM )
|
||||||
|
#include "cmsis_armcc.h"
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Arm Compiler 6 (armclang)
|
||||||
|
*/
|
||||||
|
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||||
|
#include "cmsis_armclang.h"
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* GNU Compiler
|
||||||
|
*/
|
||||||
|
#elif defined ( __GNUC__ )
|
||||||
|
#include "cmsis_gcc.h"
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* IAR Compiler
|
||||||
|
*/
|
||||||
|
#elif defined ( __ICCARM__ )
|
||||||
|
#include <cmsis_iccarm.h>
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* TI Arm Compiler
|
||||||
|
*/
|
||||||
|
#elif defined ( __TI_ARM__ )
|
||||||
|
#include <cmsis_ccs.h>
|
||||||
|
|
||||||
|
#ifndef __ASM
|
||||||
|
#define __ASM __asm
|
||||||
|
#endif
|
||||||
|
#ifndef __INLINE
|
||||||
|
#define __INLINE inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_INLINE
|
||||||
|
#define __STATIC_INLINE static inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_FORCEINLINE
|
||||||
|
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||||
|
#endif
|
||||||
|
#ifndef __NO_RETURN
|
||||||
|
#define __NO_RETURN __attribute__((noreturn))
|
||||||
|
#endif
|
||||||
|
#ifndef __USED
|
||||||
|
#define __USED __attribute__((used))
|
||||||
|
#endif
|
||||||
|
#ifndef __WEAK
|
||||||
|
#define __WEAK __attribute__((weak))
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED
|
||||||
|
#define __PACKED __attribute__((packed))
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_STRUCT
|
||||||
|
#define __PACKED_STRUCT struct __attribute__((packed))
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_UNION
|
||||||
|
#define __PACKED_UNION union __attribute__((packed))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||||
|
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_WRITE
|
||||||
|
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||||
|
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_READ
|
||||||
|
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||||
|
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_WRITE
|
||||||
|
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_READ
|
||||||
|
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __ALIGNED
|
||||||
|
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||||
|
#endif
|
||||||
|
#ifndef __RESTRICT
|
||||||
|
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||||
|
#define __RESTRICT
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* TASKING Compiler
|
||||||
|
*/
|
||||||
|
#elif defined ( __TASKING__ )
|
||||||
|
/*
|
||||||
|
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||||
|
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||||
|
* Including the CMSIS ones.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __ASM
|
||||||
|
#define __ASM __asm
|
||||||
|
#endif
|
||||||
|
#ifndef __INLINE
|
||||||
|
#define __INLINE inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_INLINE
|
||||||
|
#define __STATIC_INLINE static inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_FORCEINLINE
|
||||||
|
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||||
|
#endif
|
||||||
|
#ifndef __NO_RETURN
|
||||||
|
#define __NO_RETURN __attribute__((noreturn))
|
||||||
|
#endif
|
||||||
|
#ifndef __USED
|
||||||
|
#define __USED __attribute__((used))
|
||||||
|
#endif
|
||||||
|
#ifndef __WEAK
|
||||||
|
#define __WEAK __attribute__((weak))
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED
|
||||||
|
#define __PACKED __packed__
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_STRUCT
|
||||||
|
#define __PACKED_STRUCT struct __packed__
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_UNION
|
||||||
|
#define __PACKED_UNION union __packed__
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||||
|
struct __packed__ T_UINT32 { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_WRITE
|
||||||
|
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||||
|
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_READ
|
||||||
|
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||||
|
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_WRITE
|
||||||
|
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_READ
|
||||||
|
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __ALIGNED
|
||||||
|
#define __ALIGNED(x) __align(x)
|
||||||
|
#endif
|
||||||
|
#ifndef __RESTRICT
|
||||||
|
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||||
|
#define __RESTRICT
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* COSMIC Compiler
|
||||||
|
*/
|
||||||
|
#elif defined ( __CSMC__ )
|
||||||
|
#include <cmsis_csm.h>
|
||||||
|
|
||||||
|
#ifndef __ASM
|
||||||
|
#define __ASM _asm
|
||||||
|
#endif
|
||||||
|
#ifndef __INLINE
|
||||||
|
#define __INLINE inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_INLINE
|
||||||
|
#define __STATIC_INLINE static inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_FORCEINLINE
|
||||||
|
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||||
|
#endif
|
||||||
|
#ifndef __NO_RETURN
|
||||||
|
// NO RETURN is automatically detected hence no warning here
|
||||||
|
#define __NO_RETURN
|
||||||
|
#endif
|
||||||
|
#ifndef __USED
|
||||||
|
#warning No compiler specific solution for __USED. __USED is ignored.
|
||||||
|
#define __USED
|
||||||
|
#endif
|
||||||
|
#ifndef __WEAK
|
||||||
|
#define __WEAK __weak
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED
|
||||||
|
#define __PACKED @packed
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_STRUCT
|
||||||
|
#define __PACKED_STRUCT @packed struct
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_UNION
|
||||||
|
#define __PACKED_UNION @packed union
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||||
|
@packed struct T_UINT32 { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_WRITE
|
||||||
|
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||||
|
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_READ
|
||||||
|
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||||
|
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_WRITE
|
||||||
|
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_READ
|
||||||
|
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __ALIGNED
|
||||||
|
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
|
||||||
|
#define __ALIGNED(x)
|
||||||
|
#endif
|
||||||
|
#ifndef __RESTRICT
|
||||||
|
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||||
|
#define __RESTRICT
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#else
|
||||||
|
#error Unknown compiler.
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* __CMSIS_COMPILER_H */
|
||||||
|
|
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Reference in New Issue